FSTU6800 [FAIRCHILD]
10-Bit Bus Switch with Pre-Charged Outputs and −2V Undershoot Hardened Circuit (UHC) Protection; 10位总线开关与预充电输出和-2V下冲硬化电路（ UHC ）保护
| 型号： | FSTU6800 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 10-Bit Bus Switch with Pre-Charged Outputs and −2V Undershoot Hardened Circuit (UHC) Protection |
| 文件： | 总5页 (文件大小：184K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
December 1998
Revised December 1999
FSTU6800
10-Bit Bus Switch with Pre-Charged Outputs
and −2V Undershoot Hardened Circuit (UHC ) Protection
General Description
Features
■ 4Ω switch connection between two ports.
The Fairchild Switch FSTU6800 provides 10-bits of high-
speed CMOS TTL-compatible bus switching. The low on
resistance of the switch allows inputs to be connected to
outputs without adding propagation delay or generating
additional ground bounce noise. Both the A Ports and the B
Ports are “undershoot hardened” with UHC protection to
support an extended input range to 2.0V below ground.
Fairchild’s integrated Undershoot Hardened Circuit, UHC
senses undershoot at the I/Os, and responds by preventing
voltage differentials from developing and turning on the
switch. The device also precharges the B Port to a select-
able bias voltage (BiasV) to minimize live insertion noise.
■ Undershoot Hardened to -2.0V.
■ Soft enable turn-on to minimize bus-to-bus charge
sharing during enable.
■ Low lCC
.
■ Zero bounce in flow-through mode.
■ Output precharge to minimize live insertion noise.
■ Control inputs compatible with TTL level.
■ See Applications Note AN-5008 for details.
The device is organized as a 10-bit switch with a bus
enable (OE) signal. When OE is LOW, the switch is ON
and Port A is connected to Port B. When OE is HIGH, the
switch is OPEN and the B Port is precharged to BiasV
through an equivalent 10-kΩ resistor.
Ordering Code:
Order Number
FSTU6800WM
FSTU6800QSC
FSTU6800MTC
Package Number
M24B
Package Description
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MO-153 4.4mm Wide
24-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150” Wide
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MQA24
MTC24
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Diagram
Connection Diagram
Pin Descriptions
Pin Name
Description
Truth Table
OE
A
Bus Switch Enable
Bus A
B0–B9
OE
L
Function
Connect
A0–A9
B
Bus B
H
BiasV
Precharge
BiasV
Bus B Voltage Bias
UHC is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS500194
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Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions (Note 3)
Supply Voltage (VCC
)
−0.5V to +7.0V
−2.0V to +7.0V
−0.5V to +7.0V
−0.5V to +7.0V
−50mA
DC Switch Voltage (VS)
Power Supply Operating (VCC
Precharge Supply (BiasV)
)
4.0V to 5.5V
1.5V to VCC
0V to 5.5V
0V to 5.5V
Bias V Voltage Range
DC Input Voltage (VIN) (Note 2)
DC Input Diode Current (lIK) VIN< 0V
DC Output (IOUT) Sink Current
Input Voltage (VIN
)
Output Voltage (VOUT
)
128mA
Input Rise and Fall Time (tr, tf)
Switch Control Input
DC VCC/GND Current (ICC/IGND
)
+/− 100mA
0 nS/V to 5 nS/V
0nS/V to DC
Storage Temperature Range (TSTG
)
−65°C to +150 °C
Switch I/O
Free Air Operating Temperature (TA)
−40 °C to +85 °C
Note 1: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The Recommended Operating Conditions tables will define the conditions
for actual device operation.
Note 2: The input and output negative voltage ratings may be exceeded if
the input and output diode current ratings are observed.
Note 3: Unused control inputs must be held HIGH or LOW. They may not
float.
DC Electrical Characteristics
TA = −40 °C to +85 °C
VCC
Symbol
Parameter
Units
Conditions
Typ
(Note 5)
(V)
Min
Max
VIK
Clamp Diode Voltage
HIGH Level Input Voltage
LOW Level Input Voltage
Input Leakage Current
Output Current
4.5
4.0–5.5
4.0–5.5
5.5
−1.2
V
V
IIN = −18mA
VIH
VIL
II
2.0
0.8
V
±1.0
µA
mA
µA
Ω
0 ≤ VIN ≤ 5.5V
IO
4.5
0.25
BiasV = 2.4V, B = 0
0 ≤ A ≤ VCC, VIN = VIH
IOZ
RON
OFF-STATE Leakage Current
Switch On Resistance
(Note 4)
5.5
±1.0
7
4.5
4
4
V
V
V
V
V
S = 0V, IIN = 64 mA
4.5
7
Ω
S = 0V, IIN = 30 mA
4.5
8
15
20
3
Ω
S = 2.4V, IIN = 15 mA
S = 2.4V, IIN = 15 mA
S = VCC or GND, IOUT = 0
4.0
11
Ω
ICC
Quiescent Supply Current
Increase in ICC per Input
5.5
µA
∆ ICC
5.5
2.5
mA
OE input at 3.4V
Other inputs at VCC or GND
IBIAS
IOZU
VIKU
Bias Pin Leakage Current
Switch Undershoot Current
Voltage Undershoot
5.5
5.5
5.5
±1.0
100
µA
µA
V
OE = 0V, B = 0V, BiasV = 5.5V
I
IN = −20 mA, OE = 5.5V, VOUT ≥ VIH
−2.0
0.0 mA ≥ IIN ≥ −50 mA, OE = 5.5V
Note 4: Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lower of the
voltages on the two (A or B) pins.
Note 5: Typical values are at VCC = 5.0V and TA= +25°C
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2
AC Electrical Characteristics
T
A = −40 °C to +85 °C,
CL = 50 pF, RU = RD = 500Ω
Symbol
Parameter
Units
Conditions
Figure No.
V
CC = 4.5 – 5.5V
V
CC = 4.0V
Min
Max
Min
Max
t
PHL,tPLH
Prop Delay Bus to Bus (Note 6)
Output Enable Time
0.25
0.25
ns
ns
ns
ns
ns
VI = OPEN
Figure 1
Figure 2
tPZH
tPZL
tPHZ
tPLZ
7.0
7.0
1.0
1.0
30.0
30.0
6.1
35.0
35.0
6.5
VI = OPEN
BiasV = GND
Figure 1
Figure 2
VI = 7V
BiasV = 3V
Output Disable Time
VI = OPEN
BiasV = GND
Figure 1
Figure 2
7.3
6.8
VI = 7V
BiasV = 3V
Note 6: This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On
resistance of the switch and the 50 pF load capacitance, when driven by an ideal voltage the source (zero output impedance).
Capacitance (Note 7)
Symbol
CIN
CI/O
Parameter
Typ
Max
Units
Conditions
CC = 5.0V
VCC, OE = 5.0V
Control Pin Input Capacitance
Input/Output Capacitance
3
5
pF
pF
V
Note 7: TA = +25°C, f = 1 MHz, Capacitance is characterized but not tested.
AC Loading and Waveforms
Note: Input driven by 50 Ω source terminated in 50 Ω, RU = RD = 500 Ω
Note: CL includes load and stray capacitance, CL= 50 pF
Note: Input PRR = 1.0 MHz, tW = 500 nS
FIGURE 1. AC Test Circuit
FIGURE 2. AC Waveforms
3
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Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MO-153 4.4mm Wide
Package Number M24B
24-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150” Wide
Package Number MQA24
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4
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC24
Technology Description
The Fairchild Switch family derives from and embodies Fairchild’s proven switch technology used for several years in its
74LVX3L384 (FST3384) bus switch product.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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5
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