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FSUSB11_09 [FAIRCHILD]

Low-Power, Full-Speed (12Mbps) Switch; 低功耗，全速（ 12Mbps的）开关
FSUSB11_09
型号： FSUSB11_09
厂家： FAIRCHILD SEMICONDUCTOR    FAIRCHILD SEMICONDUCTOR
描述：

Low-Power, Full-Speed (12Mbps) Switch
低功耗，全速（ 12Mbps的）开关

开关
文件： 总10页 (文件大小：557K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
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November 2009  
FSUSB11 — Low-Power, Full-Speed (12Mbps) Switch  
Features  
Description  
The FSUSB11 is a high-performance, dual Single-Pole  
Double-Throw (SPDT) switch designed for switching  
USB 1.1 signals. The device features ultra-low on  
resistance (RON) of 1.15Ω maximum at 4.5V VCC and  
ƒ
ƒ
ƒ
ƒ
Space Saving MicroPak™ (1.6 x 2.1mm)  
USB 1.1 Signal Switching Compliant  
3db Bandwidth: >350MHz  
4.3Ω at 2.7V supply. High bandwidth and ultra low (RON  
)
Maximum 1.15Ω RON at 4.5V VCC and 4Ω for  
2.7V Supply  
make this switch able to pass both USB low- and full-  
speed signal with minimum signal distortion. The device  
is fabricated with sub-micron CMOS technology to  
achieve fast switching speeds and designed for break-  
before-make operation. The select input is TTL-level  
compatible.  
ƒ
ƒ
ƒ
ƒ
ƒ
0.3Ω Maximum RON Flatness for +5V Supply  
Broad VCC Operating Range: 1.65V to 5.5V  
Fast Turn-On and Turn-Off Time  
Break-Before-Make Enable Circuitry  
Over-Voltage Tolerant, TTL-Compatible  
Control Input  
Applications  
ƒ
Cell Phones, PDAs, Digital Cameras, Notebook  
Computers  
Ordering Information  
Operating  
Part Number Temperature  
Range  
Packing  
Eco  
Status  
Package  
Method  
FSUSB11L10X  
-40 to +85°C  
RoHS  
RoHS  
10-Lead, MicroPak™, JEDEC MO255,1.6 X 2.1mm Tape and Reel  
14-Lead Thin Shrink Small Outline Package  
Tape and Reel  
FSUSB11MTCX -40 to +85°C  
(TSSOP), JEDEC MO-153, 4.4mm Wide  
For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.  
Figure 1. Block Diagram  
MicroPak™ is a trademark of Fairchild Semiconductor Corporation.  
©2005 Fairchild Semiconductor Corporation  
FSUSB11 • Rev. 1.0.4  
www.fairchildsemi.com  
Pin Configuration  
Figure 2. TSSOP Pin Assignment (Top View)  
Figure 3. Micropak™ Pin Assignment (Top View)  
Analog Symbol  
Figure 4. Analog Symbol  
Pin Descriptions  
TSSOP Pin #  
1, 3, 4, 6, 9, 12  
2, 5  
MicroPak™ Pin #  
1, 3, 4, 6, 7, 9  
10  
Pin Names  
Description  
Data Ports  
D+, D1+, D-, D1-, D2-, D2+  
GND  
NC  
Ground  
7, 8  
No Connect  
Control Input  
Supply Voltage  
10, 13  
2, 8  
5
S1, S2  
VCC  
11, 14  
Truth Table  
Control Inputs  
Function  
Low Logic Level  
High Logic Level  
D1 Connected to D+/D-  
D2 Connected to D+/D-  
© 2005 Fairchild Semiconductor Corporation  
FSUSB11 • Rev. 1.0.4  
www.fairchildsemi.com  
2
Absolute Maximum Ratings  
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be  
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.  
In addition, extended exposure to stresses above the recommended operating conditions may affect device  
reliability. The absolute maximum ratings are stress ratings only.  
Symbol  
VCC  
VS  
Parameter  
Min.  
-0.5  
-0.5  
-0.5  
-50  
Max.  
6.0  
Unit  
V
Supply Voltage  
Switch Voltage  
Input Voltage(1)  
VCC + 0.5  
6.0  
V
VIN  
V
IIK  
Input Diode Current  
Switch Current  
mA  
mA  
ISW  
200  
400  
Peak Switch Current  
ISWPEAK  
mA  
(Pulsed at 1ms Duration, <10% Duty Cycle)  
TSTG  
TJ  
Storage Temperature Range  
-65  
+150  
+150  
+260  
8
°C  
°C  
°C  
kV  
Maximum Junction Temperature  
TL  
Lead Temperature (Soldering, 10 Seconds)  
Human Body Model, JESD22-A114  
ESD  
Note:  
1. The input and output negative voltage ratings may be exceeded if the input and output diode current ratings are  
observed.  
Recommended Operating Conditions  
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended  
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not  
recommend exceeding them or designing to Absolute Maximum Ratings.  
Symbol  
VCC  
Parameter  
Min.  
1.65  
0
Max.  
5.50  
VCC  
Unit  
V
Power Supply  
VIN  
Control Input Voltage(2)  
Switch Input Voltage  
Operating Temperature  
VCC  
VCC  
°C  
VSW  
0
VCC  
TA  
-40  
+85  
Note:  
2. Unused inputs must be held HIGH or LOW. They may not float.  
© 2005 Fairchild Semiconductor Corporation  
www.fairchildsemi.com  
FSUSB11 • Rev. 1.0.4  
3
DC Electrical Characteristics  
Unless otherwise specified, typical values are at +25°C.  
TA=-40 to  
+85°C  
TA=+25°C  
Symbol  
Parameter  
Conditions  
VCC (V)  
Units  
Min. Typ. Max. Min. Max.  
2.7 to 3.6  
4.5 to 5.5  
2.7 to 3.6  
4.5 to 5.5  
2.7 to 3.6  
4.5 to 5.5  
2.0  
4.0  
VIH  
VIL  
IIN  
Input Voltage High  
Input Voltage Low  
Control Input Leakage  
V
V
VIN=0V to VCC  
µA  
nA  
INO(OFF), Off-Leakage Current of Port  
INO(OFF) D1 and D2  
A=1V, 4.5V, B0 or  
B1=1V, 4.5V  
5.5  
-50  
50  
50  
50  
-100 100  
-100 100  
A=1V, 4.5V, B0 or  
B1=1V, 4.5V or  
Floating  
On-Leakage Current of  
Port D  
IA(ON)  
5.5  
nA  
I
OUT= 100mA,  
2.7  
4.5  
2.7  
4.5  
2.60 4.00  
0.95 1.15  
2.80  
4.30  
1.30  
4.50  
3.00  
D1 or D2=1.5V  
Micropak  
IOUT= 100mA,  
D1 or D2=3.5V  
Switch On  
RON  
Ω
Resistance(3)  
I
OUT= 100mA,  
D1 or D2=1.5V  
TSSOP  
IOUT= 100mA,  
D1 or D2=3.5V  
1.50  
On Resistance  
Matching Between  
Channel(4)  
Micropak  
TSSOP  
0.06 0.12  
0.07  
0.15  
0.30  
I
OUT= 100mA,  
4.5  
ΔRON  
Ω
D1 or D2=3.5V  
I
OUT=100mA, D1 or  
2.7  
4.5  
1.4  
D2=0V, 0.75V, 1.5V  
RFLAT(ON) On Resistance Flatness(5)  
Ω
IOUT=100mA, B0 or  
B1=0V, 1V, 2V  
0.2  
0.3  
0.4  
3.6  
5.5  
0.1  
0.1  
0.5  
0.5  
1.0  
1.0  
VIN=0V or VCC  
,
ICC  
Quiescent Supply Current  
µA  
I
OUT=0  
Notes:  
3. On resistance is determined by the voltage drop between D and Dn pins at the indicated current through the  
switch.  
4. ΔRON = RONmax - RONmin measured at identical VCC, temperature, and voltage.  
5. Flatness is defined as the difference between the maximum and minimum value of on resistance over the  
specified range of conditions.  
© 2005 Fairchild Semiconductor Corporation  
FSUSB11 • Rev. 1.0.4  
www.fairchildsemi.com  
4
AC Electrical Characteristics  
Unless otherwise specified, typical values are at +25°C.  
TA=-40 to  
+85°C  
TA=+25°C  
Symbol  
Parameter  
Conditions  
V
CC(V)  
Units Figure  
Min. Typ. Max.  
Min. Max.  
D1 or D2=1.5V,  
RL=50Ω, CL=35pF  
2.7 to 3.6  
4.5 to 5.5  
2.7 to 3.6  
4.5 to 5.5  
2.7 to 3.6  
4.5 to 5.5  
50  
35  
20  
15  
60  
Turn-on Time  
S-to-Bus B  
tON  
ns  
ns  
ns  
Figure 5  
Figure 5  
Figure 6  
D1 or D2=3.0V,  
RL=50Ω, CL=35pF  
30  
20  
D1 or D2=1.5V,  
RL=50Ω, CL=35pF  
Turn-off Time  
S-to-Bus B  
tOFF  
D1 or D2=3.0V,  
RL=50Ω, CL=35pF  
D1 or D2=1.5V,  
RL=50Ω, CL=35pF  
1
1
Break-Before-Make  
Time  
tBBM  
D1 or D2=3.0V,  
RL=50Ω, CL=35pF  
20  
2.7 to 3.6  
4.5 to 5.5  
20  
10  
CL=1.0nF,  
VGEN=0V, RGEN=0Ω  
Q
Charge Injection  
Off Isolation  
pC  
dB  
dB  
Figure 8  
Figure 7  
Figure 7  
2.7 to 3.6  
4.5 to 5.5  
-70  
-70  
OIRR  
XTALK  
BW  
f=1MHz, RL=50Ω  
f=1MHz, RL=50Ω  
RL=50Ω  
2.7 to 3.6  
4.5 to 5.5  
-75  
-75  
Non-Adjacent  
Channel Crosstalk  
2.7 to 3.6  
4.5 to 5.5  
350  
350  
-3dB Bandwidth  
MHz Figure 10  
USB Related AC Electrical Characteristics  
Unless otherwise specified, typical values are at 25°C.  
TA=+25°C  
Symbol  
tSK(O)  
Parameter  
Skew  
Conditions  
V
CC (V)  
Units Figure  
Min.  
Typ. Max.  
2.7 to 3.6  
4.5 to 5.5  
2.7 to 3.6  
4.5 to 5.5  
0.15  
0.15  
30  
RS=39, CL=50pF, tR=tF=12ns  
at 12Mbps  
ns  
ps  
Figure 11  
Figure 12  
Rising/Fall Time  
Mismatch  
tSK(P)  
(Duty Cycle=50%)  
20  
2.7 to 3.6  
4.5 to 5.5  
1.7  
1.6  
RS=39, CL=50pF, tR=tF=12ns at  
12Mbps (PRBS=215 1)  
TJ  
Total Jitter  
ps  
Figure 12  
Capacitance  
TA=+25°C  
Symbol  
Parameter  
Conditions  
VCC (V)  
Units Figure  
Min.  
Typ. Max.  
CIN  
COFF  
CON  
Control Pin Input Capacitance f=1MHz  
0.0  
4.5  
4.5  
3.5  
pF  
pF  
pF  
Figure 9  
Figure 9  
Figure 9  
Dn Port Off Capacitance  
D Port On Capacitance  
f=1MHz  
f=1MHz  
12.0  
40.0  
© 2005 Fairchild Semiconductor Corporation  
FSUSB11 • Rev. 1.0.4  
www.fairchildsemi.com  
5
AC Loadings and Waveforms  
Note:  
7. Logic input waveforms inverted for switches that have  
the opposite logic sense.  
Note:  
6. CL includes fixture and stray capacitance.  
Figure 5. Turn On/ Turn Off Timing  
Note:  
8. CL includes fixture and stray capacitance.  
Figure 6. Break-Before-Make Timing  
Figure 7. Off Isolation and Crosstalk  
© 2005 Fairchild Semiconductor Corporation  
FSUSB11 • Rev. 1.0.4  
www.fairchildsemi.com  
6
AC Loadings and Waveforms (Continued)  
Note:  
9. Q=(ΔVOUT) (CL).  
Figure 8. Charge Injection  
Figure 9. On/Off Capacitance Measurement Setup  
Figure 10. Bandwidth  
Figure 11. Skew Test  
Figure 12. Rise/Fall Time Mismatch Test  
© 2005 Fairchild Semiconductor Corporation  
FSUSB11 • Rev. 1.0.4  
www.fairchildsemi.com  
7
Physical Dimensions  
0.10  
C
2.10  
A
2X  
1.62  
B
KEEPOUT ZONE, NO TRACES  
OR VIAS ALLOWED  
(0.11)  
0.56  
1.12  
1.60  
PIN1 IDENT IS  
2X LONGER THAN  
OTHER LINES  
0.10  
C
10X  
(0.35)  
(0.25)  
2X  
10X  
0.50  
TOP VIEW  
RECOMMENDED LAND PATTERN  
0.55 MAX  
0.05 C  
0.05 C  
0.05  
0.00  
(0.20)  
C
0.35  
0.25  
SIDE VIEW  
(0.15)  
D
DETAIL A  
(0.36)  
0.35  
0.25  
0.65  
0.55  
0.35  
0.25  
DETAIL A 2X SCALE  
1
4
0.56  
NOTES:  
10  
5
A. PACKAGE CONFORMS TO JEDEC  
REGISTRATION MO-255, VARIATION UABD .  
B. DIMENSIONS ARE IN MILLIMETERS.  
C. DIMENSIONS AND TOLERANCES PER  
ASME Y14.5M, 1994.  
D. PRESENCE OF CENTER PAD IS PACKAGE  
SUPPLIER DEPENDENT. IF PRESENT IT  
IS NOT INTENDED TO BE SOLDERED AND  
HAS A BLACK OXIDE FINISH.  
(0.29)  
0.35  
6
9
9X  
0.25  
0.50  
0.25  
0.15  
9X  
1.62  
0.10  
0.05  
C
C
A B  
ALL FEATURES  
E. DRAWING FILENAME: MKT-MAC10Arev5.  
BOTTOM VIEW  
Figure 13. 10-Lead, MicroPak™, JEDEC MO255,1.6 X 2.1mm  
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner  
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify  
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically  
the warranty therein, which covers Fairchild products.  
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:  
http://www.fairchildsemi.com/packaging/.  
Tape and Reel Specification  
Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:  
http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf.  
Package Designator  
Tape Section  
Leader (Start End)  
Carrier  
Cavity Number  
125 (Typical)  
5000  
Cavity Status Cover Type Status  
Empty  
Filled  
Sealed  
Sealed  
Sealed  
L10X  
Trailer (Hub End)  
75 (Typical)  
Empty  
© 2005 Fairchild Semiconductor Corporation  
FSUSB11 • Rev. 1.0.4  
www.fairchildsemi.com  
8
Physical Dimensions  
0.43 TYP  
0.65  
1.65  
6.10  
0.45  
12.00°TOP & BOTTOM  
R0.09 min  
A. CONFORMS TO JEDEC REGISTRATION MO-153,  
VARIATION AB, REF NOTE 6  
B. DIMENSIONS ARE IN MILLIMETERS  
R0.09min  
1.00  
C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,  
AND TIE BAR EXTRUSIONS  
D. DIMENSIONING AND TOLERANCES PER ANSI  
Y14.5M, 1982  
E. LANDPATTERN STANDARD: SOP65P640X110-14M  
F. DRAWING FILE NAME: MTC14REV6  
Figure 14. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner  
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify  
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically  
the warranty therein, which covers Fairchild products.  
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:  
http://www.fairchildsemi.com/packaging/  
© 2005 Fairchild Semiconductor Corporation  
FSUSB11 • Rev. 1.0.4  
www.fairchildsemi.com  
9
© 2005 Fairchild Semiconductor Corporation  
FSUSB11 • Rev. 1.0.4  
www.fairchildsemi.com  
10  

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