GTLP6C816 [FAIRCHILD]
GTLP-to-TTL 1:6 Clock Driver; GTLP至TTL 1 ： 6时钟驱动器
| 型号： | GTLP6C816 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | GTLP-to-TTL 1:6 Clock Driver |
| 文件： | 总7页 (文件大小：48K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 1998
Revised October 1998
GTLP6C816
GTLP-to-TTL 1:6 Clock Driver
typically less than 0.5V, the output level HIGH is 1.5V and
the receiver threshold is 1.0V.
General Description
The GTLP6C816 is a clock driver that provides TTL to
GTLP signal level translation (and vice versa). The device
provides a high speed interface between cards operating at
TTL logic levels and a backplane operating at GTLP logic
levels. High speed backplane operation is a direct result of
GTLP’s reduced output swing (<1V), reduced input thresh-
old levels and output edge rate control. The edge rate con-
Features
■ Interface between TTL and GTLP logic levels
■ Edge Rate Control to minimize noise on the GTLP port
■ Power up/down high impedance for live insertion
■ 1:6 fanout clock driver for TTL port
trol minimizes bus settling time. GTLP is
a Fairchild
■ 1:2 fanout clock driver for GTLP port
Semiconductor derivative of the Gunning Transceiver logic
(GTL) JEDEC standard JESD8-3.
■ TTL compatible driver and control inputs
Fairchild’s GTLP has internal edge-rate control and is pro-
cess, voltage, and temperature (PVT) compensated. Its
function is similar to BTL and GTL but with different output
levels and receiver threshold. GTLP output LOW level is
■ Flow through pinout optimizes PCB layout
■ Open drain on GTLP to support wired-or connection
■ Recommended Operating Temperature −40°C to +85°C
Ordering Code:
Order Number
Package Number Package Description
GTLP6C816MTC MTC24
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Descriptions
Connection Diagram
Pin Names
Description
TTLIN, GTLPIN Clock Inputs (TTL and GTLP respectively)
OEB
Output Enable (Active LOW)
GTLP Port (TTL Levels)
OEA
Output Enable (Active LOW)
TTL Port (TTL Levels)
VCCT.GNDT
VCC
TTL Output Supplies (5V)
Internal Circuitry VCC (5V)
OBn GTLP Output Grounds
Voltage Reference Input
GNDG
VREF
OA0–OA5
OB0–OB1
TTL Buffered Clock Outputs
GTLP Buffered Clock Outputs
© 1998 Fairchild Semiconductor Corporation
DS500129.prf
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Functional Description
The GTLP6C816 is a clock driver providing TTL-to-GTLP clock translation, and GTLP-to-TTL clock translation in the same
package. The TTL-to-GTLP direction is a 1:2 clock driver path with a single Enable pin (OEB). For the GTLP-to-TTL direc-
tion the clock receiver path is a 1:6 buffer with a single Enable control (OEA). Data polarity is inverting for both directions.
Truth Tables
Inputs
Outputs
OBn
L
TTLIN
OEB
H
L
L
L
H
X
H
High Z
Inputs
Outputs
OAn
L
GTLPIN
OEA
H
L
L
L
H
X
H
High Z
Logic Diagram
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions (Note 3)
Supply Voltage (VCC
)
−0.5V to +7.0V
−0.5V to +7.0V
DC Input Voltage (VI)
DC Output Voltage (VO)
Outputs 3-STATE
Supply Voltage VCC
4.75V to 5.25V
Bus Termination Voltage (VTT
)
−0.5V to +7.0V
−0.5V to +7.0V
GTLP
VREF
1.47V to 1.53V
0.98V to 1.02V
Outputs Active (Note 2)
DC Output Sink Current into
OA-Port IOL
Input Voltage (VI) on INA-Port
and Control Pins
48 mA
−48 mA
80 mA
0.0V to 5.5V
DC Output Source Current
from OA-Port IOH
HIGH Level Output Current (IOH
)
OA-Port
−24 mA
DC Output Sink Current into
OB-Port in the LOW State IOL
LOW Level Output Current (IOL
OA-Port
)
+24 mA
+34 mA
DC Input Diode Current (IIK
)
OB-Port
VI < 0V
−50 mA
Operating Temperature (TA)
−40°C to +85°C
Note 1: Absolute Maximum continuous ratings are those values beyond
which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability.
Functional operation under absolute maximum rated conditions is not
implied.
DC Output Diode Current (IOK
)
V
V
O < 0V
−50 mA
+50 mA
O > VCC
ESD Rating
> 2000V
Note 2: I Absolute Maximum Rating must be observed.
o
Storage Temperature (TSTG
)
−65°C to +150°C
Note 3: Unused input must be held high or low.
3
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DC Electrical Characteristics
Over Recommended Operating Free-Air Temperature Range, V
= 1.0V (unless otherwise noted).
REF
Typ
Symbol
Test Conditions
Min
Max
Units
(Note 4)
V
V
V
GTLPIN
V
+0.05
V
IH
REF
TT
V
V
V
Others
GTLPIN
Others
GTLP
2.0
0.0
V
−0.05
IL
REF
0.8
1.0
0.8
1.5
1.2
REF
(Note 5) GTL
GTLP
(Note 5) GTL
V
TT
V
V
V
V
V
V
= 4.75V
= 4.75V
I = −18 mA
−1.2
IK
CC
CC
I
OAn-Port
OAn-Port
OBn-Port
I
I
I
I
I
I
I
I
= −100 µA
= −18 mA
= −24 mA
= 100 µA
= 18 mA
= 24 mA
= 100 µA
= 34 mA
V
−0.2
CC
OH
OH
OH
OH
OL
OL
OL
OL
OL
2.4
2.2
V
V
V
V
= 4.75V
0.2
0.4
0.5
0.2
0.65
5
OL
OL
CC
V
V
V
V
= 4.75V
= 5.25V
= 5.25V
CC
CC
CC
V
I
TTLIN/
V = 5.25V
I
I
µA
Control Pins
GTLPIN
V = 0V
−5
I
V = V
5
I
TT
µA
µA
V = 0
−5
I
I
I
TTLIN
V
V
= 0
V or V = 0V to
OFF
OZH
CC
CC
I
O
100
5.25V
OAn-Port
OBn-Port
OAn-Port
OAn or
= 5.25V
V
V
V
= 5.25V
= 1.5V
= 0
5
5
O
O
O
µA
µA
I
I
V
V
= 5.25V
= 5.25V
−5
18
20
20
6
OZL
CC
CC
CC
Outputs HIGH
Outputs LOW
7
7
7
OBn Ports
mA
V = V or GND
Outputs Disabled
I
CC
∆I
TTLIN
V
= 5.25V
V = V −2.1
mA
pF
CC
CC
I
CC
C
Control Pins/GTLPIN/
TTLIN
V = V or 0
I CC
IN
3.7
C
OAn-Port
OBn-Port
V = V or 0
7
7
OUT
I
CC
pF
V = V or 0
I
CC
Note 4: All typical values are at V = 5.0V and T = 25°C.
CC
A
Note 5: GTLP V
and V are specified to 2% tolerance since signal integrity and noise margin can be significantly degraded if these supplies are noisy.
TT
REF
In addition, V and R
can be adjusted to accommodate backplane impedances other than 50Ω, within the boundaries of not exceeding the DC Abso-
TERM
TT
lute I ratings. Similarly V
OL
can be adjusted to compensate for changes in V
.
TT
REF
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4
AC Electrical Characteristics
Over recommended range of supply voltage and operating free air temperature. V
= 1.0V (unless otherwise noted).
REF
C
L = 30 pF for OBn-Port and CL = 50 pF for OAn-Port.
Typ
Min
Symbol
From (Input)
To (Output)
Max
Units
(Note 6)
t
TTLIN
OBn
1.5
1.5
1.5
1.5
3.8
2.8
6.4
3.2
2.3
2.3
2.0
2.0
3.6
3.8
4.4
4.0
0.2
6.0
5.0
PLH
ns
t
PHL
t
OEB
OBn
10.5
6.0
PLH
ns
t
PHL
t
Transition Time, OB Outputs (20% to 80%)
Transition Time, OB outputs (20% to 80%)
Transition Time, OA outputs (10% to 90%)
Transition Time, OA outputs (10% to 90%)
ns
ns
ns
ns
RISE
t
FALL
t
RISE
t
FALL
t
, t
OEA
OAn
0.5
0.5
1.5
1.5
6.5
6.5
6.5
6.0
1.0
PZH PZL
ns
t
, t
PLZ PHZ
t
GTLPIN
OAn
PLH
ns
ns
t
PHL
t
, t
Common Edge Skew
OSHL OSLH
(Note 7)
Note 6: All typical values are at V = 5.0V and T = 25°C.
CC
A
Note 7: Skew specs are given for specific worst case V
Temp. Skew values between the OBn outputs could vary on the backplane due to loading and
CC
impedance seen by the device.
5
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Test Circuit and Timing Waveforms
Test Circuit for A Outputs
Test Circuit for B Outputs
Note A: CL includes probes and jig capacitance.
Note B: For B-Port CL = 30 pF is used for worst case.
Note A: CL includes probes and jig capacitance.
Voltage Waveforms Enable and Disable Times A-Port
Voltage Waveforms Propagation Delay (Vm = VCC/2 for A-Port and 1.0 for B-Port)
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6
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC24
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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