HUF75321S3S_NL [FAIRCHILD]
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| 型号： | HUF75321S3S_NL |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 暂无描述 晶体 晶体管 功率场效应晶体管 开关 |
| 文件： | 总10页 (文件大小：234K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HUF75321P3, HUF75321S3S
Data Sheet
December 2001
35A, 55V, 0.034 Ohm, N-Channel UltraFET
Power MOSFETs
Features
• 35A, 55V
These N-Channel power MOSFETs
are manufactured using the
innovative UltraFET® process. This
• Simulation Models
- Temperature Compensated PSPICE® and SABER™
Models
advanced process technology
- Thermal Impedance SPICE and SABER Models
Available on the WEB at: www.fairchildsemi.com
achieves the lowest possible on-resistance per silicon area,
resulting in outstanding performance. This device is capable
of withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators,
switching converters, motor drivers, relay drivers, low-
voltage bus switches, and power management in portable
and battery-operated products.
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
Formerly developmental type TA75321.
D
Ordering Information
G
PART NUMBER
PACKAGE
TO-220AB
TO-263AB
BRAND
75321P
75321S
HUF75321P3
S
HUF75321S3S
NOTE: When ordering, use the entire part number. Add the suffix T to
obtain the TO-263AB variant in tape and reel, e.g., HUF75321S3ST.
Packaging
JEDEC TO-220AB
JEDEC TO-263AB
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
GATE
DRAIN
(FLANGE)
SOURCE
Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html
For severe environments, see our Automotive HUFA series.
All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
©2001 Fairchild Semiconductor Corporation
HUF75321P3, HUF75321S3S Rev. B
HUF75321P3, HUF75321S3S
o
Absolute Maximum Ratings
T = 25 C, Unless Otherwise Specified
C
UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . V
55
55
V
V
V
DSS
DGR
Drain to Gate Voltage (R
= 20kΩ) (Note 1) . . . . . . . . . . . . . V
GS
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
±20
GS
Drain Current
Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
35
Figure 4
Figures 6, 14, 15
93
A
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
AS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
W
D
o
o
Derate Above 25 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0.625
W/ C
o
Operating and Storage Temperature . . . . . . . . . . . . . . . . . .T , T
-55 to 175
C
J
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . T
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . T
o
300
260
C
C
L
o
pkg
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
o
o
1. T = 25 C to 150 C.
J
o
Electrical Specifications
T = 25 C, Unless Otherwise Specified
C
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
BV
I
= 250µA, V
= 0V (Figure 11)
55
-
-
-
-
-
-
V
DSS
D
GS
GS
GS
I
V
V
V
= 50V, V
= 45V, V
= ±20V
= 0V
= 0V, T = 150 C
1
µA
µA
nA
DSS
DS
DS
GS
o
-
250
±100
C
Gate to Source Leakage Current
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
Drain to Source On Resistance
THERMAL SPECIFICATIONS
I
-
GSS
V
V
= V , I = 250µA (Figure 10)
2
-
-
4
V
GS(TH)
GS
DS
D
r
I
= 35A, V
= 10V (Figure 9)
0.028
0.034
Ω
DS(ON)
D
GS
o
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
R
R
(Figure 3)
TO-220, TO-263
-
-
-
-
1.6
62
C/W
θJC
o
C/W
θJA
SWITCHING SPECIFICATIONS (V
Turn-On Time
= 10V)
GS
t
V
R
R
= 30V, I
D
35A,
= 10V,
-
-
-
-
-
-
-
100
ns
ns
ns
ns
ns
ns
ON
DD
= 0.86Ω, V
L
GS
Turn-On Delay Time
Rise Time
t
11
55
47
66
-
-
d(ON)
= 25Ω
GS
t
-
r
Turn-Off Delay Time
Fall Time
t
-
-
d(OFF)
t
f
Turn-Off Time
t
170
OFF
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Q
V
V
V
= 0V to 20V
= 0V to 10V
= 0V to 2V
V
DD
= 30V,
35A,
-
-
-
-
-
36
21
1.3
3
44
26
1.6
-
nC
nC
nC
nC
nC
g(TOT)
GS
GS
GS
I
D
Gate Charge at 10V
Q
g(10)
R
= 0.86Ω
L
I
= 1.0mA
g(REF)
(Figure 13)
Threshold Gate Charge
Q
g(TH)
Gate to Source Gate Charge
Reverse Transfer Capacitance
Q
Q
gs
9
-
gd
©2001 Fairchild Semiconductor Corporation
HUF75321P3, HUF75321S3S Rev. B
HUF75321P3, HUF75321S3S
o
Electrical Specifications
T = 25 C, Unless Otherwise Specified
C
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
CAPACITANCE SPECIFICATIONS
Input Capacitance
C
V
= 25V, V = 0V,
GS
-
-
-
680
270
60
-
-
-
pF
pF
pF
ISS
DS
f = 1MHz
(Figure 12)
Output Capacitance
C
C
OSS
RSS
Reverse Transfer Capacitance
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Reverse Recovery Time
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
1.25
59
UNITS
V
V
I
I
I
= 35A
-
-
-
-
-
-
SD
SD
SD
SD
t
= 35A, dI /dt = 100A/µs
SD
ns
rr
Reverse Recovered Charge
Q
= 35A, dI /dt = 100A/µs
82
nC
RR
SD
Typical Performance Curves
1.2
1.0
0.8
40
30
20
10
0.6
0.4
0.2
0
0
25
50
75
100
125
150
175
0
25
50
75
100
125
o
150
175
o
T , CASE TEMPERATURE ( C)
T
, CASE TEMPERATURE ( C)
C
C
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
1
0.1
0.05
0.02
0.01
P
DM
0.1
t
1
t
2
NOTES:
DUTY FACTOR: D = t /t
1
2
PEAK T = P
x Z
x R + T
J
DM
θJC
θJC C
SINGLE PULSE
0.01
-5
10
-4
10
-3
10
-2
10
-1
0
1
10
t, RECTANGULAR PULSE DURATION (s)
10
10
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
©2001 Fairchild Semiconductor Corporation
HUF75321P3, HUF75321S3S Rev. B
HUF75321P3, HUF75321S3S
Typical Performance Curves (Continued)
500
o
T
= 25 C
FOR TEMPERATURES
C
o
ABOVE 25 C DERATE PEAK
CURRENT AS FOLLOWS:
175 - T
150
C
I = I
25
100
V
= 20V
= 10V
GS
V
GS
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10
10
-5
-4
10
-3
-2
-1
0
1
10
10
t, PULSE WIDTH (s)
10
10
10
FIGURE 4. PEAK CURRENT CAPABILITY
300
If R = 0
= (L)(I )/(1.3*RATED BV
300
100
SINGLE PULSE
t
- V
)
DD
AV
If R ≠ 0
= (L/R)ln[(I *R)/(1.3*RATED BV - V ) +1]
DSS DD
AS
DSS
T
T
= MAX RATED
J
o
= 25 C
t
AV
C
AS
100
100µs
o
STARTING T = 25 C
J
10
o
STARTING T = 150 C
J
1ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY r
DS(ON)
= 55V
10ms
V
DSS(MAX)
10
0.001
1
0.01
0.1
1
1
10
, DRAIN TO SOURCE VOLTAGE (V)
100
200
t
, TIME IN AVALANCHE (ms)
AV
V
DS
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
75
75
V
= 20V
= 10V
= 8V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
o
GS
V
-55 C
GS
V
GS
60
45
30
15
0
60
45
30
15
0
V
= 7V
GS
V
= 6V
= 5V
GS
o
175 C
V
GS
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
o
o
V
= 15V
T
= 25 C
6.0
25 C
DD
C
0
1.5
3.0
4.5
7.5
0
1.5
3.0
4.5
6.0
7.5
V
, DRAIN TO SOURCE VOLTAGE (V)
V , GATE TO SOURCE VOLTAGE (V)
GS
DS
FIGURE 7. SATURATION CHARACTERISTICS
FIGURE 8. TRANSFER CHARACTERISTICS
©2001 Fairchild Semiconductor Corporation
HUF75321P3, HUF75321S3S Rev. B
HUF75321P3, HUF75321S3S
Typical Performance Curves (Continued)
2.5
2.0
1.5
1.0
0.5
1.2
1.0
0.8
0.6
PULSE DURATION = 80µs
V
= V , I = 250µA
DS
GS
D
DUTY CYCLE = 0.5% MAX
V
= 10V, I = 35A
GS
D
-80
-40
0
40
80
120
160
200
-80
-40
0
40
80
120
160
200
o
o
T , JUNCTION TEMPERATURE ( C)
T , JUNCTION TEMPERATURE ( C)
J
J
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
RESISTANCE vs JUNCTION TEMPERATURE
1.2
1.1
1.0
0.9
1000
V
= 0V, f = 1MHz
I
= 250µA
GS
D
C
C
C
= C
+ C
ISS
GS
= C
GD
RSS
OSS
GD
DS
800
600
400
200
0
≈ C + C
GD
C
ISS
C
C
OSS
RSS
-80
-40
0
40
80
120
160
200
0
10
20
30
40
50
60
o
T , JUNCTION TEMPERATURE ( C)
V
, DRAIN TO SOURCE VOLTAGE (V)
J
DS
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
10
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
I
I
I
= 35A
= 17.5A
= 8.75A
2
D
D
D
V
= 30V
DD
0
0
5
10
15
20
25
Q , GATE CHARGE (nC)
g
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
©2001 Fairchild Semiconductor Corporation
HUF75321P3, HUF75321S3S Rev. B
HUF75321P3, HUF75321S3S
Test Circuits and Waveforms
V
DS
BV
DSS
L
t
P
V
DS
I
VARY t TO OBTAIN
P
AS
+
V
DD
R
REQUIRED PEAK I
G
AS
V
DD
-
V
GS
DUT
t
P
I
AS
0V
0
0.01Ω
t
AV
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
V
DS
V
Q
DD
R
g(TOT)
L
V
DS
V
= 20V
GS
V
Q
GS
g(10)
+
-
V
DD
V
= 10V
V
GS
GS
DUT
V
= 2V
GS
I
0
G(REF)
Q
g(TH)
Q
Q
gd
gs
I
g(REF)
0
FIGURE 16. GATE CHARGE TEST CIRCUIT
FIGURE 17. GATE CHARGE WAVEFORM
V
t
t
DS
ON
OFF
t
d(OFF)
t
d(ON)
t
t
f
R
L
r
V
DS
90%
90%
+
V
GS
V
DD
10%
10%
0
-
DUT
90%
50%
R
GS
V
GS
50%
PULSE WIDTH
10%
V
GS
0
FIGURE 18. SWITCHING TIME TEST CIRCUIT
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
©2001 Fairchild Semiconductor Corporation
HUF75321P3, HUF75321S3S Rev. B
HUF75321P3, HUF75321S3S
PSPICE Electrical Model
.SUBCKT HUF75321P 2 1 3 ;
rev 4/29/98
CA 12 8 9.96e-10
CB 15 14 9.83e-10
CIN 6 8 6.18e-10
LDRAIN
DPLCAP
5
DRAIN
2
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
10
RLDRAIN
RSLC1
51
+
DBREAK
RSLC2
5
EBREAK 11 7 17 18 59.54
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
ESLC
11
51
-
50
+
-
17
DBODY
RDRAIN
6
8
EBREAK 18
ESG
EVTEMP 20 6 18 22 1
-
EVTHRES
+
+
16
21
-
19
8
MWEAK
LGATE
EVTEMP
+
IT 8 17 1
RGATE
GATE
1
6
-
18
22
MMED
9
LDRAIN 2 5 1e-9
LGATE 1 9 3.57e-9
LSOURCE 3 7 4.25e-9
20
MSTRO
8
RLGATE
LSOURCE
CIN
SOURCE
3
7
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RSOURCE
RLSOURCE
S1A
S2A
RBREAK
12
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 5.50e-3
RGATE 9 20 2.25
RLDRAIN 2 5 10
RLGATE 1 9 35.7
RLSOURCE 3 7 42.5
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
15
13
8
14
13
17
18
RVTEMP
19
-
S1B
S2B
13
CB
CA
IT
14
+
+
VBAT
6
8
5
8
EGS
EDS
+
RSOURCE 8 7 RSOURCEMOD 16.30e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
-
-
8
22
RVTHRES
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*101),2.5))}
.MODEL DBODYMOD D (IS = 7.47e-13 RS = 6.45e-3 TRS1 = 2.01e-3 TRS2 = 1.21e-6 CJO = 1.02e-9 TT = 3.21e-8 M = 0.50)
.MODEL DBREAKMOD D (RS = 2.01e- 1TRS1 = 3.62e- 3TRS2 = 6.01e-7)
.MODEL DPLCAPMOD D (CJO = 9.0e-1 0IS = 1e-3 0N = 10 M = 0.85)
.MODEL MMEDMOD NMOS (VTO = 3.25 KP = 1.75 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.25)
.MODEL MSTROMOD NMOS (VTO = 3.65 KP = 32.00 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 2.91 KP = 0.07 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 22.5 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1.05e- 3TC2 = 1.21e-7)
.MODEL RDRAINMOD RES (TC1 = 2.40e-2 TC2 = 1.02e-6)
.MODEL RSLCMOD RES (TC1 = 2.07e-4 TC2 = 4.67e-5)
.MODEL RSOURCEMOD RES (TC1 = 0 TC2 =0)
.MODEL RVTHRESMOD RES (TC = -3.01e-3 TC2 = -8.85e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.96e- 3TC2 = 1.39e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -7.85 VOFF= -4.85)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.85 VOFF= -7.85)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.00 VOFF= 3.00)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 3.00 VOFF= 0.00)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
©2001 Fairchild Semiconductor Corporation
HUF75321P3, HUF75321S3S Rev. B
HUF75321P3, HUF75321S3S
SABER Electrical Model
REV April 1998
template huf75321p n2, n1, n3
electrical n2, n1, n3
{
var i iscl
d..model dbodymod = (is = 7.47e-13, cjo = 1.02e-9, tt = 3.21e-8, m = 0.5)
d..model dbreakmod = ()
d..model dplcapmod = (cjo = 9e-10, is = 1e-30, n = 10, m = 0.85)
m..model mmedmod = (type=_n, vto = 3.25, kp = 1.75, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 3.65, kp = 32, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 2.91, kp = 0.07, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -7.85, voff = -4.85)
sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -4.85, voff = -7.85)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = 0, voff = 3.0)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 3.0, voff = 0)
LDRAIN
RLDRAIN
RDBODY
DPLCAP
DRAIN
2
5
10
RSLC1
51
RDBREAK
72
DBREAK
11
RSLC2
c.ca n12 n8 = 9.96e-10
c.cb n15 n14 = 9.83e-10
c.cin n6 n8 = 6.18e-10
ISCL
50
-
71
RDRAIN
6
8
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
ESG
EVTHRES
+
+
16
21
d.dplcap n10 n5 = model=dplcapmod
-
19
8
MWEAK
LGATE
EVTEMP
+
DBODY
i.it n8 n17 = 1
RGATE
GATE
1
6
-
18
22
EBREAK
+
MMED
9
20
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 =3.57e-9
l.lsource n3 n7 = 4.25e-9
MSTRO
8
17
18
-
RLGATE
LSOURCE
CIN
SOURCE
3
7
m.mmed n16 n6 n8 n8 = model=mmedmod, l = 1u, w = 1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l = 1u, w = 1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l = 1u, w = 1u
RSOURCE
RLSOURCE
S1A
S2A
14
13
S2B
RBREAK
12
15
13
17
18
res.rbreak n17 n18 = 1, tc1 = 1.05e-3, tc2 = 1.21e-7
res.rdbody n71 n5 = 6.45e-3, tc1 = 2.01e-3, tc2 = 1.21e-6
res.rdbreak n72 n5 = 2.01e-1, tc1 = 3.62e-3, tc2 = 6.01e-7
res.rdrain n50 n16 = 5.5e-3, tc1 = 2.4e-2, tc2 = 1.02e-6
res.rgate n9 n20 = 2.25
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 35.7
res.rlsource n3 n7 = 42.5
res.rslc1 n5 n51 = 1e-6, tc1 = 2.07e-4, tc2 = 4.67e-5
res.rslc2 n5 n50 = 1e3
8
RVTEMP
19
S1B
13
CB
CA
IT
14
-
+
+
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
22
RVTHRES
res.rsource n8 n7 = 16.3e-3, tc1 = 0, tc2 = 0
res.rvtemp n18 n19 = 1, tc1 = -1.96e-3, tc2 = 1.39e-6
res.rvthres n22 n8 = 1, tc1 = -3.01e-3, tc2 = -8.85e-6
spe.ebreak n11 n7 n17 n18 = 59.54
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc = 1
equations {
i (n51->n50) + = iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/101))** 2.5))
}
}
©2001 Fairchild Semiconductor Corporation
HUF75321P3, HUF75321S3S Rev. B
HUF75321P3, HUF75321S3S
SPICE Thermal Model
JUNCTION
th
REV 24 February 1999
HUF75321P
RTHERM1
RTHERM2
RTHERM3
RTHERM4
RTHERM5
RTHERM6
CTHERM1
CTHERM1 th 6 2.7e-3
CTHERM2 6 5 3.7e-3
CTHERM3 5 4 1.2e-2
CTHERM4 4 3 3.8e-3
CTHERM5 3 2 1.4e-2
CTHERM6 2 tl 10.55
6
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
RTHERM1 th 6 1.10e-2
RTHERM2 6 5 2.72e-2
RTHERM3 5 4 7.67e-2
RTHERM4 4 3 4.30e-1
RTHERM5 3 2 6.49e-1
RTHERM6 2 tl 8.61e-2
5
SABER Thermal Model
SABER thermal model HUF75321P
4
3
2
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 2.7e-3
ctherm.ctherm2 6 5 = 3.7e-3
ctherm.ctherm3 5 4 = 1.2e-2
ctherm.ctherm4 4 3 = 3.8-3
ctherm.ctherm5 3 2 = 1.4e-2
ctherm.ctherm6 2 tl = 10.55
rtherm.rtherm1 th 6 = 1.10e-3
rtherm.rtherm2 6 5 = 2.72e-2
rtherm.rtherm3 5 4 = 7.67e-2
rtherm.rtherm4 4 3 = 4.30e-1
rtherm.rtherm5 3 2 = 6.49e-1
rtherm.rtherm6 2 tl = 8.61e-2
}
tl
CASE
©2001 Fairchild Semiconductor Corporation
HUF75321P3, HUF75321S3S Rev. B
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Rev. H4
相关型号：
HUF75329D3S_NL
Power Field-Effect Transistor, 20A I(D), 55V, 0.026ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-252AA,
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