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HUF75545P3 [FAIRCHILD]

75A, 80V, 0.010 Ohm, N-Channel, UltraFET Power MOSFET; 75A ， 80V ， 0.010 Ohm的N通道， UltraFET功率MOSFET
HUF75545P3
型号： HUF75545P3
厂家： FAIRCHILD SEMICONDUCTOR    FAIRCHILD SEMICONDUCTOR
描述：

75A, 80V, 0.010 Ohm, N-Channel, UltraFET Power MOSFET
75A ， 80V ， 0.010 Ohm的N通道， UltraFET功率MOSFET
文件： 总10页 (文件大小：266K)
中文：  中文翻译
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HUF75545P3, HUF75545S3, HUF75545S3S  
Data Sheet  
September 2002  
75A, 80V, 0.010 Ohm, N-Channel,  
®
UltraFET Power MOSFET  
Packaging  
JEDEC TO-220AB  
JEDEC TO-263AB  
DRAIN  
(FLANGE)  
Features  
SOURCE  
DRAIN  
GATE  
• Ultra Low On-Resistance  
- r  
= 0.010Ω, VGS = 10V  
DS(ON)  
• Simulation Models  
GATE  
SOURCE  
- Temperature Compensated PSPICE® and SABER™  
Electrical Models  
DRAIN  
(FLANGE)  
HUF75545S3S  
- Spice and SABER Thermal Impedance Models  
- www.fairchildsemi.com  
HUF75545P3  
JEDEC TO-262AA  
SOURCE  
• Peak Current vs Pulse Width Curve  
• UIS Rating Curve  
DRAIN  
DRAIN  
(FLANGE)  
GATE  
Ordering Information  
HUF75545S3  
PART NUMBER  
HUF75545P3  
PACKAGE  
TO-220AB  
BRAND  
75545P  
Symbol  
D
S
HUF75545S3  
TO-262AA  
TO-263AB  
75545S  
75545S  
HUF75545S3S  
NOTE: When ordering, use the entire part number. Add the suffix T to  
obtain the TO-263AB variant in tape and reel, e.g., HUF75545S3ST.  
G
o
Absolute Maximum Ratings  
T
= 25 C, Unless Otherwise Specified  
C
HUF75545P3, HUF75545S3,  
HUF75545S3S  
UNITS  
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V  
80  
80  
V
V
V
DSS  
Drain to Gate Voltage (R  
= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V  
GS  
DGR  
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V  
±20  
GS  
Drain Current  
o
Continuous (T = 25 C, V  
C
= 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I  
75  
73  
A
A
GS  
D
D
o
Continuous (T = 100 C, V  
= 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I  
C
GS  
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I  
Figure 4  
Figure 6  
270  
DM  
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UIS  
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P  
W
D
o
o
Derate Above 25 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
1.8  
W/ C  
o
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T , T  
J
-55 to 175  
C
STG  
Maximum Temperature for Soldering  
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T  
Package Body for 10s, See Techbrief TB334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T  
o
300  
260  
C
C
L
o
pkg  
NOTES:  
1. T = 25 C to 150 C.  
o
o
J
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the  
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html  
For severe environments, see our Automotive HUFA series.  
All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.  
©2002 Fairchild Semiconductor Corporation  
HUF75545P3 / HUF75545S3 / HUF75545S3S Rev. C  
HUF75545P3, HUF75545S3, HUF75545S3S  
o
Electrical Specifications  
PARAMETER  
T
= 25 C, Unless Otherwise Specified  
C
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
OFF STATE SPECIFICATIONS  
Drain to Source Breakdown Voltage  
Zero Gate Voltage Drain Current  
BV  
I
= 250µA, V  
= 0V (Figure 11)  
80  
-
-
-
-
-
-
V
DSS  
D
GS  
GS  
GS  
I
V
V
V
= 75V, V  
= 70V, V  
= ±20V  
= 0V  
1
µA  
µA  
nA  
DSS  
DS  
DS  
GS  
o
= 0V, T = 150 C  
-
250  
±100  
C
Gate to Source Leakage Current  
ON STATE SPECIFICATIONS  
Gate to Source Threshold Voltage  
Drain to Source On Resistance  
THERMAL SPECIFICATIONS  
I
-
GSS  
V
V
= V , I = 250µA (Figure 10)  
2
-
-
4
V
GS(TH)  
GS  
DS  
D
r
I
= 75A, V  
= 10V (Figure 9)  
0.0082 0.010  
Ω
DS(ON)  
D
GS  
o
Thermal Resistance Junction to Case  
R
R
TO-220 and TO-263  
-
-
-
-
0.55  
62  
C/W  
θJC  
o
Thermal Resistance Junction to  
Ambient  
C/W  
θJA  
SWITCHING SPECIFICATIONS (V  
Turn-On Time  
= 10V)  
t
GS  
V
V
R
= 40V, I = 75A  
D
= 10V,  
= 2.5Ω  
-
-
-
-
-
-
-
14  
125  
40  
90  
-
210  
ns  
ns  
ns  
ns  
ns  
ns  
ON  
DD  
GS  
Turn-On Delay Time  
Rise Time  
t
-
d(ON)  
GS  
t
-
r
Turn-Off Delay Time  
Fall Time  
t
-
-
d(OFF)  
t
f
Turn-Off Time  
t
195  
OFF  
GATE CHARGE SPECIFICATIONS  
Total Gate Charge  
Q
V
V
V
= 0V to 20V  
= 0V to 10V  
= 0V to 2V  
V
= 40V,  
-
-
-
-
-
195  
105  
6.8  
15  
235  
125  
8.2  
-
nC  
nC  
nC  
nC  
nC  
g(TOT)  
GS  
GS  
GS  
DD  
= 75A,  
I
I
D
Gate Charge at 10V  
Q
g(10)  
g(TH)  
= 1.0mA  
g(REF)  
(Figure 13)  
Threshold Gate Charge  
Q
Gate to Source Gate Charge  
Gate to Drain “Miller” Charge  
CAPACITANCE SPECIFICATIONS  
Input Capacitance  
Q
gs  
gd  
Q
43  
-
C
V
= 25V, V = 0V,  
GS  
-
-
-
3750  
1100  
350  
-
-
-
pF  
pF  
pF  
ISS  
DS  
f = 1MHz  
(Figure 12)  
Output Capacitance  
C
OSS  
RSS  
Reverse Transfer Capacitance  
C
Source to Drain Diode Specifications  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
1.25  
1.00  
100  
UNITS  
Source to Drain Diode Voltage  
V
I
I
I
I
= 75A  
= 35A  
-
-
-
-
-
-
-
-
V
V
SD  
SD  
SD  
SD  
SD  
Reverse Recovery Time  
t
= 75A, dI /dt = 100A/µs  
SD  
ns  
nC  
rr  
Reverse Recovered Charge  
Q
= 75A, dI /dt = 100A/µs  
SD  
300  
RR  
©2002 Fairchild Semiconductor Corporation  
HUF75545P3 / HUF75545S3 / HUF75545S3S Rev. C  
HUF75545P3, HUF75545S3, HUF75545S3S  
Typical Performance Curves  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0
80  
60  
40  
20  
0
V
= 10V  
GS  
175  
0
25  
50  
75  
100  
150  
175  
25  
50  
75  
100  
125  
o
150  
125  
o
T
, CASE TEMPERATURE ( C)  
T , CASE TEMPERATURE ( C)  
C
C
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE  
TEMPERATURE  
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs  
CASE TEMPERATURE  
2
DUTY CYCLE - DESCENDING ORDER  
0.5  
1
0.2  
0.1  
0.05  
0.02  
0.01  
P
DM  
0.1  
t
1
t
2
NOTES:  
DUTY FACTOR: D = t /t  
SINGLE PULSE  
1
2
PEAK T = P  
x Z  
x R  
+ T  
θJC C  
J
DM  
θJC  
0.01  
-5  
-4  
10  
-3  
10  
-2  
10  
-1  
10  
0
1
10  
10  
10  
t, RECTANGULAR PULSE DURATION (s)  
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE  
2000  
1000  
o
T
= 25 C  
C
FOR TEMPERATURES  
o
ABOVE 25 C DERATE PEAK  
CURRENT AS FOLLOWS:  
175 - T  
150  
C
I = I  
25  
V
= 10V  
GS  
100  
50  
TRANSCONDUCTANCE  
MAY LIMIT CURRENT  
IN THIS REGION  
-5  
-4  
-3  
10  
-2  
10  
-1  
0
1
10  
10  
10  
10  
10  
t, PULSE WIDTH (s)  
FIGURE 4. PEAK CURRENT CAPABILITY  
©2002 Fairchild Semiconductor Corporation  
HUF75545P3 / HUF75545S3 / HUF75545S3S Rev. C  
HUF75545P3, HUF75545S3, HUF75545S3S  
Typical Performance Curves (Continued)  
600  
100  
600  
If R = 0  
= (L)(I )/(1.3*RATED BV  
t
- V  
)
DD  
AV  
If R ≠ 0  
= (L/R)ln[(I *R)/(1.3*RATED BV - V ) +1]  
DSS DD  
AS  
DSS  
t
AV  
AS  
100  
100µs  
o
STARTING T = 25 C  
J
OPERATION IN THIS  
AREA MAY BE  
1ms  
10  
1
LIMITED BY r  
DS(ON)  
o
STARTING T = 150 C  
J
10ms  
SINGLE PULSE  
T
T
= MAX RATED  
J
C
o
= 25 C  
10  
0.001  
0.01  
0.1  
, TIME IN AVALANCHE (ms)  
10  
1
1
10  
, DRAIN TO SOURCE VOLTAGE (V)  
100  
200  
t
V
AV  
DS  
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.  
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING  
CAPABILITY  
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA  
150  
150  
V
= 7V  
= 6V  
V
= 20V  
= 10V  
GS  
GS  
PULSE DURATION = 80µs  
V
V
DUTY CYCLE = 0.5% MAX  
GS  
GS  
V
= 15V  
DD  
120  
90  
60  
30  
0
120  
90  
60  
30  
0
V
=5V  
GS  
o
T
= 175 C  
J
PULSE DURATION = 80µs  
DUTY CYCLE = 0.5% MAX  
o
T
= 25 C  
o
J
T
= -55 C  
J
o
T
= 25 C  
C
2
3
4
5
6
0
1
2
3
4
V
, GATE TO SOURCE VOLTAGE (V)  
V
, DRAIN TO SOURCE VOLTAGE (V)  
DS  
GS  
FIGURE 7. TRANSFER CHARACTERISTICS  
FIGURE 8. SATURATION CHARACTERISTICS  
2.5  
1.2  
V
= 10V, I = 75A  
V
= V , I = 250µA  
DS  
PULSE DURATION = 80µs  
GS  
D
GS  
D
DUTY CYCLE = 0.5% MAX  
2.0  
1.5  
1.0  
0.8  
1.0  
0.5  
0.6  
0.4  
-80  
-40  
0
40  
80  
120  
160  
200  
-80  
-40  
0
40  
80  
120  
160  
200  
o
o
T , JUNCTION TEMPERATURE ( C)  
T , JUNCTION TEMPERATURE ( C)  
J
J
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON  
RESISTANCE vs JUNCTION TEMPERATURE  
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs  
JUNCTION TEMPERATURE  
©2002 Fairchild Semiconductor Corporation  
HUF75545P3 / HUF75545S3 / HUF75545S3S Rev. C  
HUF75545P3, HUF75545S3, HUF75545S3S  
Typical Performance Curves (Continued)  
1.2  
1.1  
1.0  
0.9  
0.8  
10000  
1000  
100  
I
= 250µA  
D
C
= C  
+ C  
GS GD  
ISS  
C
C
+ C  
DS GD  
OSS  
C
= C  
GD  
RSS  
V
= 0V, f = 1MHz  
1
GS  
-80  
-40  
0
40  
80  
120  
160  
200  
0.1  
10  
80  
o
T , JUNCTION TEMPERATURE ( C)  
V
, DRAIN TO SOURCE VOLTAGE (V)  
DS  
J
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN  
VOLTAGE vs JUNCTION TEMPERATURE  
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE  
10  
V
= 40V  
DD  
8
6
4
2
0
WAVEFORMS IN  
DESCENDING ORDER:  
I
I
= 75A  
= 35A  
D
D
0
30  
60  
Q , GATE CHARGE (nC)  
90  
120  
g
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.  
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT  
©2002 Fairchild Semiconductor Corporation  
HUF75545P3 / HUF75545S3 / HUF75545S3S Rev. C  
HUF75545P3, HUF75545S3, HUF75545S3S  
Test Circuits and Waveforms  
V
DS  
BV  
DSS  
L
t
P
V
DS  
I
VARY t TO OBTAIN  
P
AS  
+
-
V
DD  
R
REQUIRED PEAK I  
G
AS  
V
DD  
V
GS  
DUT  
t
P
I
AS  
0V  
0
0.01Ω  
t
AV  
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT  
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS  
V
DS  
V
Q
DD  
R
g(TOT)  
L
V
DS  
V
= 20V  
GS  
V
Q
GS  
g(10)  
+
-
V
DD  
V
= 10V  
V
GS  
GS  
DUT  
V
= 2V  
GS  
I
0
g(REF)  
Q
g(TH)  
Q
Q
gd  
gs  
I
g(REF)  
0
FIGURE 16. GATE CHARGE TEST CIRCUIT  
FIGURE 17. GATE CHARGE WAVEFORMS  
V
t
t
DS  
ON  
OFF  
t
d(OFF)  
t
d(ON)  
t
t
f
R
L
r
V
DS  
90%  
90%  
+
V
GS  
V
DD  
10%  
10%  
0
-
DUT  
90%  
50%  
R
GS  
V
GS  
50%  
PULSE WIDTH  
10%  
V
GS  
0
FIGURE 18. SWITCHING TIME TEST CIRCUIT  
FIGURE 19. SWITCHING TIME WAVEFORM  
©2002 Fairchild Semiconductor Corporation  
HUF75545P3 / HUF75545S3 / HUF75545S3S Rev. C  
HUF75545P3, HUF75545S3, HUF75545S3S  
PSPICE Electrical Model  
.SUBCKT HUF75545 2 1 3 ;  
rev 21 May 1999  
CA 12 8 5.4e-9  
CB 15 14 5.3e-9  
CIN 6 8 3.4e-9  
DBODY 7 5 DBODYMOD  
DBREAK 5 11 DBREAKMOD  
DPLCAP 10 5 DPLCAPMOD  
LDRAIN  
DPLCAP  
DRAIN  
2
5
10  
RLDRAIN  
RSLC1  
51  
EBREAK 11 7 17 18 87.4  
EDS 14 8 5 8 1  
EGS 13 8 6 8 1  
ESG 6 10 6 8 1  
EVTHRES 6 21 19 8 1  
EVTEMP 20 6 18 22 1  
DBREAK  
+
RSLC2  
5
ESLC  
11  
51  
-
50  
+
-
17  
18  
-
DBODY  
RDRAIN  
6
8
EBREAK  
ESG  
IT 8 17 1  
EVTHRES  
+
+
16  
21  
-
19  
8
MWEAK  
LDRAIN 2 5 1.0e-9  
LGATE 1 9 5.1e-9  
LSOURCE 3 7 4.4e-9  
LGATE  
EVTEMP  
+
RGATE  
GATE  
1
6
-
18  
22  
MMED  
9
20  
MSTRO  
8
RLGATE  
MMED 16 6 8 8 MMEDMOD  
MSTRO 16 6 8 8 MSTROMOD  
MWEAK 16 21 8 8 MWEAKMOD  
LSOURCE  
CIN  
SOURCE  
3
7
RSOURCE  
RBREAK 17 18 RBREAKMOD 1  
RDRAIN 50 16 RDRAINMOD 4.80e-3  
RGATE 9 20 0.87  
RLDRAIN 2 5 10  
RLSOURCE  
S1A  
S2A  
RBREAK  
12  
15  
13  
8
14  
13  
17  
18  
RLGATE 1 9 51  
RLSOURCE 3 7 44  
RSLC1 5 51 RSLCMOD 1e-6  
RSLC2 5 50 1e3  
RSOURCE 8 7 RSOURCEMOD 1.6e-3  
RVTHRES 22 8 RVTHRESMOD 1  
RVTEMP 18 19 RVTEMPMOD 1  
RVTEMP  
19  
-
S1B  
S2B  
13  
CB  
CA  
IT  
14  
+
+
VBAT  
6
8
5
8
EGS  
EDS  
+
-
-
8
S1A 6 12 13 8 S1AMOD  
S1B 13 12 13 8 S1BMOD  
S2A 6 15 14 13 S2AMOD  
S2B 13 15 14 13 S2BMOD  
22  
RVTHRES  
VBAT 22 19 DC 1  
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*320),3))}  
.MODEL DBODYMOD D (IS = 3.6e-12 RS = 2.1e-3 TRS1 = 1.5e-3 TRS2 = 5.1e-6 CJO = 4.6e-9 TT = 3.3e-8 M = 0.55)  
.MODEL DBREAKMOD D (RS = 2.3e-1 TRS1 = 0 TRS2 = -1.8e-5)  
.MODEL DPLCAPMOD D (CJO = 4.8e-9 IS = 1e-30 N = 10 VJ = 1 M = 0.8)  
.MODEL MMEDMOD NMOS (VTO = 3.04 KP = 6 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 0.87)  
.MODEL MSTROMOD NMOS (VTO = 3.5 KP = 105 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)  
.MODEL MWEAKMOD NMOS (VTO = 2.65 KP = 0.12 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 8.7 )  
.MODEL RBREAKMOD RES (TC1 = 1.3e-3 TC2 = -1e-6)  
.MODEL RDRAINMOD RES (TC1 = 9e-3 TC2 = 2.8e-5)  
.MODEL RSLCMOD RES (TC1 = 1.53e-3 TC2 = 2e-5)  
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6)  
.MODEL RVTHRESMOD RES (TC1 = -2.3e-3 TC2 = -1.2e-5)  
.MODEL RVTEMPMOD RES (TC1 = -2.9e-3 TC2 = 5e-7)  
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5 VOFF= -3)  
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3 VOFF= -5)  
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.5 VOFF= 0.5)  
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.5 VOFF= -1.5)  
.ENDS  
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global  
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.  
©2002 Fairchild Semiconductor Corporation  
HUF75545P3 / HUF75545S3 / HUF75545S3S Rev. C  
HUF75545P3, HUF75545S3, HUF75545S3S  
SABER Electrical Model  
REV 21 may 1999  
template huf75545 n2,n1,n3  
electrical n2,n1,n3  
{
var i iscl  
d..model dbodymod = (is = 3.6e-12, cjo = 4.6e-9, tt = 3.3e-8, m = 0.55)  
d..model dbreakmod = ()  
d..model dplcapmod = (cjo = 4.8e-9, is = 1e-30, vj=1.0, m = 0.8 )  
m..model mmedmod = (type=_n, vto = 3.04, kp = 6, is = 1e-30, tox = 1)  
m..model mstrongmod = (type=_n, vto = 3.5, kp = 105, is = 1e-30, tox = 1)  
m..model mweakmod = (type=_n, vto = 2.65, kp = 0.12, is = 1e-30, tox = 1)  
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -5, voff = -3)  
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -3, voff = -5)  
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -1.5, voff = 0.5)  
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = -1.5)  
LDRAIN  
RLDRAIN  
RDBODY  
DPLCAP  
5
DRAIN  
2
10  
RSLC1  
51  
RDBREAK  
72  
DBREAK  
11  
RSLC2  
c.ca n12 n8 = 5.4e-9  
c.cb n15 n14 = 5.3e-9  
c.cin n6 n8 = 3.4e-9  
ISCL  
50  
-
d.dbody n7 n71 = model=dbodymod  
d.dbreak n72 n11 = model=dbreakmod  
d.dplcap n10 n5 = model=dplcapmod  
71  
RDRAIN  
6
8
ESG  
EVTHRES  
+
+
16  
21  
-
19  
8
MWEAK  
LGATE  
EVTEMP  
+
i.it n8 n17 = 1  
DBODY  
RGATE  
GATE  
1
6
-
18  
22  
EBREAK  
+
MMED  
l.ldrain n2 n5 = 1e-9  
l.lgate n1 n9 = 5.1e-9  
l.lsource n3 n7 = 4.4e-9  
9
20  
MSTRO  
8
17  
18  
-
RLGATE  
LSOURCE  
CIN  
SOURCE  
3
7
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u  
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u  
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u  
RSOURCE  
RLSOURCE  
S1A  
S2A  
RBREAK  
12  
res.rbreak n17 n18 = 1, tc1 = 1.3e-3, tc2 = -1e-6  
res.rdbody n71 n5 = 2.1e-3, tc1 = 1.5e-3, tc2 = 5.1e-6  
res.rdbreak n72 n5 = 2.3e-1, tc1 = 0, tc2 = -1.8e-5  
res.rdrain n50 n16 = 4.8e-3, tc1 = 9e-3, tc2 = 2.8e-5  
res.rgate n9 n20 = 0.87  
res.rldrain n2 n5 = 10  
res.rlgate n1 n9 = 51  
res.rlsource n3 n7 = 44  
15  
13  
14  
13  
17  
18  
8
RVTEMP  
19  
-
S1B  
S2B  
13  
CB  
CA  
IT  
14  
+
+
VBAT  
6
8
5
8
EGS  
EDS  
+
res.rslc1 n5 n51 = 1e-6, tc1 = 1.53e-3, tc2 = 2e-5  
res.rslc2 n5 n50 = 1e3  
-
-
8
22  
res.rsource n8 n7 = 1.6e-3, tc1 = 1e-3, tc2 = 1e-6  
res.rvtemp n18 n19 = 1, tc1 = -2.9e-3, tc2 = 5e-7  
res.rvthres n22 n8 = 1, tc1 = -2.3e-3, tc2 = -1.2e-5  
RVTHRES  
spe.ebreak n11 n7 n17 n18 = 87.4  
spe.eds n14 n8 n5 n8 = 1  
spe.egs n13 n8 n6 n8 = 1  
spe.esg n6 n10 n6 n8 = 1  
spe.evtemp n20 n6 n18 n22 = 1  
spe.evthres n6 n21 n19 n8 = 1  
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod  
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod  
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod  
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod  
v.vbat n22 n19 = dc=1  
equations {  
i (n51->n50) +=iscl  
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/320))** 3))  
}
}
©2002 Fairchild Semiconductor Corporation  
HUF75545P3 / HUF75545S3 / HUF75545S3S Rev. C  
HUF75545P3, HUF75545S3, HUF75545S3S  
SPICE Thermal Model  
JUNCTION  
th  
REV 21 May 1999  
HUF75545T  
RTHERM1  
RTHERM2  
RTHERM3  
RTHERM4  
RTHERM5  
RTHERM6  
CTHERM1  
CTHERM2  
CTHERM3  
CTHERM4  
CTHERM5  
CTHERM6  
CTHERM1 th 6 6.4e-3  
CTHERM2 6 5 3.0e-2  
CTHERM3 5 4 1.4e-2  
CTHERM4 4 3 1.6e-2  
CTHERM5 3 2 5.5e-2  
CTHERM6 2 tl 1.5  
6
RTHERM1 th 6 3.2e-3  
RTHERM2 6 5 8.1e-3  
RTHERM3 5 4 2.3e-2  
RTHERM4 4 3 1.3e-1  
RTHERM5 3 2 1.8e-1  
RTHERM6 2 tl 3.8e-2  
5
SABER Thermal Model  
SABER thermal model HUF75545T  
4
3
2
template thermal_model th tl  
thermal_c th, tl  
{
ctherm.ctherm1 th 6 = 6.4e-3  
ctherm.ctherm2 6 5 = 3.0e-2  
ctherm.ctherm3 5 4 = 1.4e-2  
ctherm.ctherm4 4 3 = 1.6e-2  
ctherm.ctherm5 3 2 = 5.5e-2  
ctherm.ctherm6 2 tl = 1.5  
rtherm.rtherm1 th 6 = 3.2e-3  
rtherm.rtherm2 6 5 = 8.1e-3  
rtherm.rtherm3 5 4 = 2.3e-2  
rtherm.rtherm4 4 3 = 1.3e-1  
rtherm.rtherm5 3 2 = 1.8e-1  
rtherm.rtherm6 2 tl = 3.8e-2  
}
tl  
CASE  
©2002 Fairchild Semiconductor Corporation  
HUF75545P3 / HUF75545S3 / HUF75545S3S Rev. C  
TRADEMARKS  
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not  
intended to be an exhaustive list of all such trademarks.  
ACEx™  
FACT™  
ImpliedDisconnect™ PACMAN™  
SPM™  
ActiveArray™  
Bottomless™  
CoolFET™  
CROSSVOLT™ FRFET™  
DOME™  
FACT Quiet Series™ ISOPLANAR™  
POP™  
Stealth™  
®
FAST  
FASTr™  
LittleFET™  
MicroFET™  
MicroPak™  
Power247™  
PowerTrench  
QFET™  
SuperSOT™-3  
SuperSOT™-6  
SuperSOT™-8  
SyncFET™  
®
GlobalOptoisolator™ MICROWIRE™  
QS™  
EcoSPARK™  
E CMOS™  
EnSigna™  
Across the board. Around the world.™ OCXPro™  
The Power Franchise™  
Programmable Active Droop™  
GTO™  
MSX™  
MSXPro™  
OCX™  
QT Optoelectronics™ TinyLogic™  
2
HiSeC™  
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TruTranslation™  
2
I C™  
RapidConfigure™  
RapidConnect™  
SILENT SWITCHER VCX™  
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UltraFET  
®
®
®
OPTOLOGIC  
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DISCLAIMER  
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY  
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY  
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;  
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.  
LIFE SUPPORT POLICY  
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT  
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR  
CORPORATION.  
As used herein:  
1. Life support devices or systems are devices or systems  
which, (a) are intended for surgical implant into the body,  
or (b) support or sustain life, or (c) whose failure to perform  
when properly used in accordance with instructions for use  
provided in the labeling, can be reasonably expected to  
result in significant injury to the user.  
2. A critical component is any component of a life support  
device or system whose failure to perform can be  
reasonably expected to cause the failure of the life support  
device or system, or to affect its safety or effectiveness.  
PRODUCT STATUS DEFINITIONS  
Definition of Terms  
Datasheet Identification  
Product Status  
Definition  
Advance Information  
Formative or In  
Design  
This datasheet contains the design specifications for  
product development. Specifications may change in  
any manner without notice.  
Preliminary  
First Production  
This datasheet contains preliminary data, and  
supplementary data will be published at a later date.  
Fairchild Semiconductor reserves the right to make  
changes at any time without notice in order to improve  
design.  
No Identification Needed  
Obsolete  
Full Production  
This datasheet contains final specifications. Fairchild  
Semiconductor reserves the right to make changes at  
any time without notice in order to improve design.  
Not In Production  
This datasheet contains specifications on a product  
that has been discontinued by Fairchild semiconductor.  
The datasheet is printed for reference information only.  
Rev. I1  

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