HUFA75307D3ST [FAIRCHILD]
TRANSISTOR | MOSFET | N-CHANNEL | 55V V(BR)DSS | 15A I(D) | TO-252AA ; 晶体管| MOSFET | N沟道| 55V V（ BR ） DSS | 15A I（ D） | TO- 252AA\n
| 型号： | HUFA75307D3ST |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | TRANSISTOR | MOSFET | N-CHANNEL | 55V V(BR)DSS | 15A I(D) | TO-252AA
|
| 文件： | 总10页 (文件大小：218K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HUFA75307P3, HUFA75307D3, HUFA75307D3S
Data Sheet
December 2001
15A, 55V, 0.090 Ohm, N-Channel UltraFET
Power MOSFETs
Features
• 15A, 55V
These N-Channel power MOSFETs
are manufactured using the
innovative UltraFET® process. This
• Simulation Models
®
™
- Temperature Compensated PSPICE and SABER
Models
advanced process technology
- SPICE and SABER Thermal Impedance Models
Available on the WEB at: www.fairchildsemi.com
achieves the lowest possible on-resistance per silicon area,
resulting in outstanding performance. This device is capable
of withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators,
switching converters, motor drivers, relay drivers, low-
voltage bus switches, and power management in portable
and battery-operated products.
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
Formerly developmental type TA75307.
D
Ordering Information
PART NUMBER
HUFA75307P3
HUFA75307D3
HUFA75307D3S
PACKAGE
BRAND
75307P
G
TO-220AB
TO-251AA
TO-252AA
75307D
75307D
S
NOTE: When ordering, use the entire part number. Add the suffix T to
obtain the TO-252AA variant in tape and reel, e.g., HUFA75307D3ST.
Packaging
JEDEC TO-220AB
JEDEC TO-251AA
SOURCE
DRAIN
GATE
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
DRAIN
(FLANGE)
JEDEC TO-252AA
DRAIN
(FLANGE)
GATE
SOURCE
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a copy
of the requirements, see AEC Q101 at: http://www.aecouncil.com/
Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.
All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
©2001 Fairchild Semiconductor Corporation
HUFA75307P3, HUFA75307D3, HUFA75307D3S Rev. B
HUFA75307P3, HUFA75307D3, HUFA75307D3S
o
Absolute Maximum Ratings
T
= 25 C, Unless Otherwise Specified
C
UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
55
55
V
V
V
DSS
DGR
Drain to Gate Voltage (R
= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
±20
GS
Drain Current
Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
15
Figure 4
Figures 6, 14, 15
45
A
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
AS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
W
D
o
o
Derate Above 25 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0.3
W/ C
o
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T , T
-55 to 175
C
J
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
o
300
260
C
C
L
o
pkg
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
o
o
1. T = 25 C to 150 C.
J
o
Electrical Specifications
PARAMETER
T = 25 C, Unless Otherwise Specified
C
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
BV
I
= 250µA, V
= 0V (Figure 11)
55
-
-
-
-
-
-
V
DSS
D
GS
GS
GS
I
V
V
V
= 50V, V
= 45V, V
= ±20V
= 0V
= 0V, T = 150 C
1
µA
µA
nA
DSS
DS
DS
GS
o
-
250
±100
C
Gate to Source Leakage Current
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
Drain to Source On Resistance
THERMAL SPECIFICATIONS
I
-
GSS
V
V
= V , I = 250µA (Figure 10)
2
-
-
4
V
GS(TH)
GS
DS
D
r
I
= 15A, V
= 10V (Figure 9)
0.075
0.090
Ω
DS(ON)
D
GS
o
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
R
R
(Figure 3)
TO-220AB
-
-
-
-
-
-
3.3
62
C/W
θJC
o
C/W
θJA
o
TO-251AA, TO-252AA
100
C/W
SWITCHING SPECIFICATIONS (V
Turn-On Time
= 10V)
GS
t
V
R
R
= 30V, I
= 2.0Ω, V
= 100Ω
15A,
= 10V,
-
-
-
-
-
-
-
60
ns
ns
ns
ns
ns
ns
ON
DD
D
L
GS
Turn-On Delay Time
Rise Time
t
7
-
d(ON)
GS
t
40
35
45
-
-
r
Turn-Off Delay Time
Fall Time
t
-
-
d(OFF)
t
f
Turn-Off Time
t
100
OFF
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Q
V
V
V
= 0V to 20V
= 0V to 10V
= 0V to 2V
V
DD
= 30V,
15A,
-
-
-
-
-
16
9
20
11
0.8
-
nC
nC
nC
nC
nC
g(TOT)
GS
GS
GS
I
D
Gate Charge at 10V
Q
g(10)
g(TH)
R
= 2.0Ω
L
I
= 1.0mA
g(REF)
(Figure13)
Threshold Gate Charge
Q
0.6
1.2
4
Gate to Source Gate Charge
Reverse Transfer Capacitance
Q
gs
gd
Q
-
©2001 Fairchild Semiconductor Corporation
HUFA75307P3, HUFA75307D3, HUFA75307D3S Rev. B
HUFA75307P3, HUFA75307D3, HUFA75307D3S
o
Electrical Specifications
T
= 25 C, Unless Otherwise Specified
C
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
CAPACITANCE SPECIFICATIONS
Input Capacitance
C
V
= 25V, V = 0V,
GS
-
-
-
250
100
25
-
-
-
pF
pF
pF
ISS
DS
f = 1MHz
(Figure 12)
Output Capacitance
C
OSS
RSS
Reverse Transfer Capacitance
C
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Reverse Recovery Time
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
1.25
45
UNITS
V
V
I
I
I
= 15A
-
-
-
-
-
-
SD
SD
SD
SD
t
= 15A, dI /dt = 100A/µs
SD
ns
rr
Reverse Recovered Charge
Q
= 15A, dI /dt = 100A/µs
55
nC
RR
SD
Typical Performance Curves
1.2
1.0
0.8
20
15
10
5
0.6
0.4
0.2
0
0
25
50
75
100
125
150
175
0
25
50
75
100
125
o
150
175
o
T
, CASE TEMPERATURE ( C)
T , CASE TEMPERATURE ( C)
C
C
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
1
0.1
0.05
0.02
0.01
P
DM
0.1
t
1
t
2
NOTES:
DUTY FACTOR: D = t /t
1
2
SINGLE PULSE
0.01
PEAK T = P
x Z
x R + T
J
DM
θJC
θJC C
-5
-4
-3
10
-2
-1
0
1
10
10
10
t, RECTANGULAR PULSE DURATION (s)
10
10
10
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
©2001 Fairchild Semiconductor Corporation
HUFA75307P3, HUFA75307D3, HUFA75307D3S Rev. B
HUFA75307P3, HUFA75307D3, HUFA75307D3S
Typical Performance Curves (Continued)
200
100
o
T
= 25 C
FOR TEMPERATURES
C
o
ABOVE 25 C DERATE PEAK
CURRENT AS FOLLOWS:
175 - T
150
C
I = I
25
V
= 10V
GS
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10
-5
-4
-3
-2
10
-1
10
0
1
10
10
10
10
10
t, PULSE WIDTH (s)
FIGURE 4. PEAK CURRENT CAPABILITY
100
10
1
200
If R = 0
= (L)(I )/(1.3*RATED BV
T
T
= MAX RATED
J
t
- V
)
DD
AV
If R ≠ 0
= (L/R)ln[(I *R)/(1.3*RATED BV - V ) +1]
DSS DD
o
AS
DSS
= 25 C
100
10
1
C
t
AV
AS
100µs
o
STARTING T = 25 C
1ms
J
10ms
OPERATION IN THIS
AREA MAY BE
o
LIMITED BY r
STARTING T = 150 C
J
DS(ON)
V
= 55V
DSS(MAX)
V
0.1
1
10
, DRAIN TO SOURCE VOLTAGE (V)
100
200
0.001
0.01
t
0.1
1
10
, TIME IN AVALANCHE (ms)
DS
AV
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
25
25
o
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
V
= 20V
= 10V
-55 C
GS
GS
V
= 15V
20
15
10
5
20
15
10
5
DD
V
= 7V
GS
V
= 6V
GS
o
25 C
o
175 C
V
= 5V
GS
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
o
T
= 25 C
C
0
0
0
1.5
3.0
4.5
6.0
7.5
0
1
2
3
4
5
V
, DRAIN TO SOURCE VOLTAGE (V)
V
, GATE TO SOURCE VOLTAGE (V)
DS
GS
FIGURE 7. SATURATION CHARACTERISTICS
FIGURE 8. TRANSFER CHARACTERISTICS
©2001 Fairchild Semiconductor Corporation
HUFA75307P3, HUFA75307D3, HUFA75307D3S Rev. B
HUFA75307P3, HUFA75307D3, HUFA75307D3S
Typical Performance Curves (Continued)
2.5
2.0
1.5
1.0
0.5
1.2
1.0
0.8
0.6
PULSE DURATION = 80µs
V
= V , I = 250µA
DS
GS
D
DUTY CYCLE = 0.5% MAX
V
= 10V, I = 15A
GS
D
-80
-40
0
40
80
120
160
200
-80
-40
0
40
80
120
160
200
o
o
T , JUNCTION TEMPERATURE ( C)
T , JUNCTION TEMPERATURE ( C)
J
J
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
RESISTANCE vs JUNCTION TEMPERATURE
1.2
1.1
1.0
0.9
400
V
= 0, f = 1MHz
GS
ISS
I
= 250µA
D
C
C
C
= C
+ C
GS
= C
GD
RSS
OSS
GD
≈ C + C
300
200
100
0
DS
GD
C
ISS
C
C
OSS
RSS
-80
-40
0
40
80
120
160
200
0
10
20
30
40
50
60
o
T , JUNCTION TEMPERATURE ( C)
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
J
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
10
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
I
I
I
I
= 15A
= 12A
= 7.5A
= 4A
D
D
D
D
2
V
DD
= 30V
0
0
2
4
6
8
10
Q , GATE CHARGE (nC)
g
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
©2001 Fairchild Semiconductor Corporation
HUFA75307P3, HUFA75307D3, HUFA75307D3S Rev. B
HUFA75307P3, HUFA75307D3, HUFA75307D3S
Test Circuits and Waveforms
V
DS
BV
DSS
L
t
P
V
DS
I
VARY t TO OBTAIN
P
AS
+
-
V
DD
R
REQUIRED PEAK I
G
AS
V
DD
V
GS
DUT
t
P
I
AS
0V
0
0.01Ω
t
AV
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
V
DS
V
Q
DD
R
g(TOT)
L
V
DS
V
= 20V
GS
V
Q
GS
g(10)
+
-
V
DD
V
= 10V
V
GS
GS
DUT
V
= 2V
GS
I
0
G(REF)
Q
g(TH)
Q
Q
gd
gs
I
g(REF)
0
FIGURE 16. GATE CHARGE TEST CIRCUIT
FIGURE 17. GATE CHARGE WAVEFORM
V
t
t
DS
ON
OFF
t
d(OFF)
t
d(ON)
t
t
f
R
L
r
V
DS
90%
90%
+
V
GS
V
DD
10%
10%
0
-
DUT
90%
50%
R
GS
V
GS
50%
PULSE WIDTH
10%
V
GS
0
FIGURE 18. SWITCHING TIME TEST CIRCUIT
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
©2001 Fairchild Semiconductor Corporation
HUFA75307P3, HUFA75307D3, HUFA75307D3S Rev. B
HUFA75307P3, HUFA75307D3, HUFA75307D3S
PSPICE Electrical Model
.SUBCKT HUFA75307 2 1 3 ;
rev June 1997
CA 12 8 4.5e-10
CB 15 14 4.1e-10
CIN 6 8 2.154e-10
LDRAIN
DPLCAP
DRAIN
2
5
10
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
RLDRAIN
RSLC1
51
DBREAK
+
RSLC2
5
ESLC
11
51
EBREAK 11 7 17 18 56
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
-
50
+
-
17
DBODY
RDRAIN
6
8
EBREAK 18
ESG
-
EVTHRES
+
EVTEMP 20 6 18 22 1
+
16
21
-
19
8
MWEAK
LGATE
EVTEMP
+
RGATE
GATE
1
6
IT 8 17 1
-
18
22
MMED
9
20
LDRAIN 2 5 1e-9
MSTRO
8
RLGATE
LGATE 1 9 5.97e-10
LSOURCE 3 7 2.39e-9
K1 LGATE LSOURCE 0.131
LSOURCE
CIN
SOURCE
3
7
RSOURCE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RLSOURCE
S1A
S2A
RBREAK
12
15
13
14
13
17
18
8
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 1e-3
RGATE 9 20 1.9
RLDRAIN 2 5 10
RLGATE 1 9 60
RLSOURCE 3 7 24
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 5.5e-2
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
RVTEMP
19
S1B
S2B
13
CB
CA
IT
14
-
+
+
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
22
RVTHRES
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*35),4))}
.MODEL DBODYMOD D (IS=1.6e-13 RS=1.28e-2 IKF=5.5 N=0.985 TRS1=2.9e-3 TRS2=-4e-6 CJO=3.5e-10 TT=3.1e-8 M=0.45 XTI=6)
.MODEL DBREAKMOD D (RS=2.5e- 1IKF=0.1 TRS1=-4e- 3TRS2=3e-5)
.MODEL DPLCAPMOD D (CJO=5e-1 0IS=1e-3 0N=10 M=0.95)
.MODEL MMEDMOD NMOS (VTO=3.25 KP=2.2 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.9)
.MODEL MSTROMOD NMOS (VTO=3.75 KP=14.75 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MWEAKMOD NMOS (VTO=2.88 KP=0.03 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=19 RS=0.1)
.MODEL RBREAKMOD RES (TC1=1.12e- 3TC2=1e-6)
.MODEL RDRAINMOD RES (TC1=2.3e-1 TC2=6e-4)
.MODEL RSLCMOD RES (TC1=4e-3 TC2=1e-6)
.MODEL RSOURCEMOD RES (TC1=1e-3 TC2=6e-6)
.MODEL RVTHRESMOD RES (TC=-3.31e-3 TC2=-1.49e-5)
.MODEL RVTEMPMOD RES (TC1=-1.4e- 3TC2=1e-9)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-8.1 VOFF=-4)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-8.1)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0 VOFF=2)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=2 VOFF=0)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
©2001 Fairchild Semiconductor Corporation
HUFA75307P3, HUFA75307D3, HUFA75307D3S Rev. B
HUFA75307P3, HUFA75307D3, HUFA75307D3S
SABER Electrical Model
REV February 1999
template HUFA75307 n2, n1, n3
electrical n2, n1, n3
{
var i iscl
d..model dbodymod = (is = 1.6e-13, xti = 6, cjo = 3.5e-10, tt = 3.1e-8, n = 0.985, m = 0.45)
LDRAIN
RLDRAIN
RDBODY
d..model dbreakmod = ()
DPLCAP
5
DRAIN
2
d..model dplcapmod = (cjo = 5e-10, is = 1e-30, n = 10, m = 0.95)
m..model mmedmod = (type=_n, vto = 3.25, kp = 2.2, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 3.75, kp = 14.75, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 2.88, kp = 0.03, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -8.1, voff = -4)
sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -4, voff = -8.1)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = 0, voff = 2)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 2, voff = 0)
10
RSLC1
51
RDBREAK
72
DBREAK
11
RSLC2
ISCL
50
-
c.ca n12 n8 = 4.5e-10
c.cb n15 n14 = 4.1e-10
c.cin n6 n8 = 2.154e-10
71
RDRAIN
6
8
ESG
EVTHRES
+
16
21
+
-
19
8
MWEAK
LGATE
EVTEMP
+
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
DBODY
RGATE
GATE
1
6
-
18
22
EBREAK
+
MMED
9
20
MSTRO
8
17
18
-
RLGATE
i.it n8 n17 = 1
LSOURCE
CIN
SOURCE
3
7
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 5.97e-10
l.lsource n3 n7 = 2.39e-9
RSOURCE
RLSOURCE
S1A
S2A
RBREAK
12
m.mmed n16 n6 n8 n8 = model=mmedmod, l = 1u, w = 1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l = 1u, w = 1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l = 1u, w = 1u
15
13
14
13
17
18
8
RVTEMP
19
-
S1B
S2B
13
CB
res.rbreak n17 n18 = 1, tc1 = 1.12e-3, tc2 = 1e-6
res.rdbody n71 n5 = 1.28e-2, tc1 = 2.9e-3, tc2 = -4e-6
res.rdbreak n72 n5 = 0.25, tc1 = -4e-3, tc2 = 3e-5
res.rdrain n50 n16 = 1e-3, tc1 = 2.31-1, tc2 = 6e-4
res.rgate n9 n20 = 1.9
CA
IT
14
+
+
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
res.rldrain n2 n5 = 10
22
res.rlgate n1 n9 = 60
RVTHRES
res.rlsource n3 n7 = 24
res.rslc1 n5 n51 = 1e-6, tc1 = 4e-3, tc2 = 1e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 5.5e-2, tc1 = 1e-3, tc2 = 6e-6
res.rvtemp n18 n19 = 1, tc1 = -1.4e-3, tc2 = 1e-9
res.rvthres n22 n8 = 1, tc1 = -3.31e-3, tc2 = -1.49e-5
spe.ebreak n11 n7 n17 n18 = 56
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc = 1
equations {
i (n51->n50) + = iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/35))** 4))
}
}
©2001 Fairchild Semiconductor Corporation
HUFA75307P3, HUFA75307D3, HUFA75307D3S Rev. B
HUFA75307P3, HUFA75307D3, HUFA75307D3S
SPICE Thermal Model
JUNCTION
th
REV February 1999
HUFA75307
CTHERM1 th 6 8.0e-4
CTHERM2 6 5 1.6e-3
CTHERM3 5 4 1.9e-3
CTHERM4 4 3 2.6e-3
CTHERM5 3 2 5.5e-3
CTHERM6 2 tl 1.8e-2
RTHERM1
CTHERM1
6
RTHERM1 th 6 8.0e-3
RTHERM2 6 5 2.1e-2
RTHERM3 5 4 2.2e-1
RTHERM4 4 3 6.4e-1
RTHERM5 3 2 7.7e-1
RTHERM6 2 tl 1.0
RTHERM2
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
5
SABER Thermal Model
SABER thermal model HUFA75307
RTHERM3
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 8.0e-4
ctherm.ctherm2 6 5 = 1.6e-3
ctherm.ctherm3 5 4 = 1.9e-3
ctherm.ctherm4 4 3 = 2.6e-3
ctherm.ctherm5 3 2 = 5.5e-3
ctherm.ctherm6 2 tl = 1.8e-2
4
RTHERM4
3
rtherm.rtherm1 th 6 = 8.0e-3
rtherm.rtherm2 6 5 = 2.1e-2
rtherm.rtherm3 5 4 = 2.2e-1
rtherm.rtherm4 4 3 = 6.4e-1
rtherm.rtherm5 3 2 = 7.7e-1
rtherm.rtherm6 2 tl = 1.0
}
RTHERM5
2
RTHERM6
tl
CASE
©2001 Fairchild Semiconductor Corporation
HUFA75307P3, HUFA75307D3, HUFA75307D3S Rev. B
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Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
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any manner without notice.
Preliminary
First Production
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Rev. H4
相关型号：
HUFA75307T3ST_NL
Power Field-Effect Transistor, 2.6A I(D), 55V, 0.09ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, LEAD FREE PACKAGE-4
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