HUFA75307T3ST_NL [FAIRCHILD]
Power Field-Effect Transistor, 2.6A I(D), 55V, 0.09ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, LEAD FREE PACKAGE-4;
| 型号： | HUFA75307T3ST_NL |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Power Field-Effect Transistor, 2.6A I(D), 55V, 0.09ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, LEAD FREE PACKAGE-4 晶体 晶体管 功率场效应晶体管 开关 光电二极管 |
| 文件： | 总9页 (文件大小：175K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HUFA75307T3ST
Data Sheet
December 2001
2.6A, 55V, 0.090 Ohm, N-Channel UltraFET
Power MOSFET
Features
• 2.6A, 55V
• Ultra Low On-Resistance, r
This N-Channel power MOSFET is
manufactured using the innovative
= 0.090Ω
DS(ON)
• Diode Exhibits Both High Speed and Soft Recovery
UltraFET® process. This advanced
®
process technology achieves the
• Temperature Compensating PSPICE Model
lowest possible on-resistance per silicon area, resulting in
outstanding performance. This device is capable of
withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators,
switching converters, motor drivers, relay drivers, low-
voltage bus switches, and power management in portable
and battery-operated products.
• Thermal Impedance SPICE Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
Formerly developmental type TA75307.
D
Ordering Information
PART NUMBER
PACKAGE
BRAND
G
HUFA75307T3ST
SOT-223
5307
S
NOTE: HUFA75307T3ST is available only in tape and reel.
Packaging
SOT-223
DRAIN
(FLANGE)
GATE
DRAIN
SOURCE
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a copy
of the requirements, see AEC Q101 at: http://www.aecouncil.com/
Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.
All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
©2001 Fairchild Semiconductor Corporation
HUFA75307T3ST Rev. B
HUFA75307T3ST
o
Absolute Maximum Ratings T = 25 C, Unless Otherwise Specified
A
UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
55
55
±20V
V
V
V
DSS
DGR
GS
Drain to Gate Voltage (R
= 20kΩ) (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
Drain Current
Continuous (Figure 2) (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
2.6
Figure 5
Figures 6, 14, 15
1.1
A
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
AS
Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
W
D
o
o
Derate Above 25 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.09
-55 to 150
mW/ C
o
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T , T
Maximum Temperature for Soldering
C
J
STG
o
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
300
260
C
L
o
Package Body for 10s, See Techbrief 334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
C
pkg
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
o
o
1. T = 25 C to 125 C.
J
o
Electrical Specifications
T = 25 C, Unless Otherwise Specified
A
PARAMETER
SYMBOL
TEST CONDITIONS
= 250µA, V = 0V (Figure 11)
MIN
TYP
MAX
UNITS
V
Drain to Source Breakdown Voltage
Gate to Source Threshold Voltage
Zero Gate Voltage Drain Current
BV
I
55
2
-
-
-
4
DSS
D
GS
= V , I = 250µA (Figure 10)
V
V
V
V
V
-
-
V
GS(TH)
GS
DS
DS
GS
DS D
I
= 50V, V
= 45V, V
= ±20V
= 0V
1
µA
µA
nA
Ω
DSS
GS
o
= 0V, T = 150 C
-
-
250
100
0.090
55
-
GS
A
Gate to Source Leakage Current
Drain to Source On Resistance
Turn-On Time
I
-
-
GSS
r
I
= 2.6A, V
= 10V) (Figure 9)
2.6A,
D
-
0.070
-
DS(ON)
D
GS
t
V
R
R
= 30V, I
-
ns
ON
DD
= 11.5Ω, V = 10V,
L
GS
Turn-On Delay Time
Rise Time
t
-
5
ns
d(ON)
= 25Ω
GS
t
-
30
35
25
-
-
ns
r
Turn-Off Delay Time
Fall Time
t
-
-
ns
d(OFF)
t
-
-
ns
f
Turn-Off Time
t
-
90
17
10
0.8
ns
OFF
Total Gate Charge
Gate Charge at 10V
Threshold Gate Charge
Q
V
V
V
= 0V to 20V
= 0V to 10V
= 0V to 2V
V
DD
= 30V,
2.6A,
-
14
8.3
0.6
nC
nC
nC
g(TOT)
GS
GS
GS
I
D
Q
-
g(10)
g(TH)
R
= 11.5Ω
L
Q
-
I
= 1.0mA
g(REF)
(Figure 13)
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
Input Capacitance
Qgs
Qgd
-
-
-
-
-
-
-
-
1.00
4.00
250
115
30
-
-
nC
nC
pF
pF
pF
-
-
C
V
= 25V, V = 0V,
GS
ISS
DS
f = 1MHz
(Figure 12)
Output Capacitance
C
C
-
OSS
RSS
Reverse Transfer Capacitance
-
2
o
Thermal Resistance Junction to Ambient
R
Pad Area = 0.171 in (see note 2)
110
128
147
C/W
θJA
2
o
Pad Area = 0.068 in
-
C/W
2
o
Pad Area = 0.026 in
-
C/W
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Reverse Recovery Time
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
1.25
40
UNITS
V
V
I
I
I
= 2.6A
-
-
-
-
-
-
SD
SD
SD
SD
t
= 2.6A, dI /dt = 100A/µs
SD
ns
rr
Reverse Recovered Charge
Q
= 2.6A, dI /dt = 100A/µs
SD
50
nC
RR
NOTE:
o
2
2. 110 C/W measured using FR-4 board with 0.171in footprint for 1000s.
©2001 Fairchild Semiconductor Corporation
HUFA75307T3ST Rev. B
HUFA75307T3ST
Typical Performance Curves
1.2
1.0
3.0
2.5
2.0
1.5
1.0
0.5
0
o
R
= 110 C/W
JA
θ
0.8
0.6
0.4
0.2
0
25
50
75
100
125
150
0
50
100
150
o
o
T , AMBIENT TEMPERATURE ( C)
T , AMBIENT TEMPERATURE ( C)
A
A
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
AMBIENT TEMPERATURE
10
DUTY CYCLE - DESCENDING ORDER
o
0.5
R
= 110 C/W
JA
θ
0.2
0.1
0.05
1
0.02
0.01
0.1
P
DM
t
1
0.01
t
2
NOTES:
DUTY FACTOR: D = t /t
SINGLE PULSE
1
2
PEAK T = P
x Z
x R
+ T
JA A
J
DM
JA
θ
θ
0.001
-5
10
-4
-3
-2
10
-1
10
0
1
2
3
10
10
10
t, RECTANGULAR PULSE DURATION (s)
10
10
10
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
100
10
30
o
= 25 C FOR TEMPERATURES
T
= MAX RATED
T
J
A
o
o
ABOVE 25 C DERATE PEAK
CURRENT AS FOLLOWS:
T
= 25 C
A
o
R
= 110 C/W
JA
θ
150 - T
I = I
A
25
100µs
10
125
o
1ms
R
= 110 C/W
JA
θ
1
10ms
0.1
0.01
OPERATION IN THIS
AREA MAY BE
LIMITED BY r
V
(
) = 55V
DS(ON)
DSS MAX
1
10
-3
-2
10
-1
0
1
2
3
200
10
10
10
10
10
1
10
, DRAIN TO SOURCE VOLTAGE (V)
100
V
DS
t, PULSE WIDTH (s)
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. PEAK CURRENT CAPABILITY
©2001 Fairchild Semiconductor Corporation
HUFA75307T3ST Rev. B
HUFA75307T3ST
Typical Performance Curves (Continued)
20
25
20
If R = 0
V
= 20V
= 10V
= 7V
t
AV
= (L)(I )/(1.3*RATED BV
- V
)
DD
GS
AS
DSS
If R ≠ 0
V
GS
t
AV
= (L/R)ln[(I *R)/(1.3*RATED BV
- V ) +1]
DD
AS DSS
V
10
GS
V
= 6V
= 5V
15
GS
o
STARTING T = 25 C
J
10
5
V
o
GS
STARTING T = 150 C
J
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
o
T
= 25 C
A
1
0.01
0
0
1
2
3
4
5
0.1
1
10
t
, TIME IN AVALANCHE (ms)
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
AV
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
FIGURE 7. SATURATION CHARACTERISTICS
25
2.5
2.0
1.5
1.0
0.5
PULSE DURATION = 80µs
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
o
-55 C
DUTY CYCLE = 0.5% MAX
= 15V
V
V
= 10V, I = 2.6A
DD
GS
D
20
15
10
5
o
25 C
o
150 C
0
0
1.5
3.0
4.5
6.0
7.5
-80
-40
0
40
80
120
160
o
V
, GATE TO SOURCE VOLTAGE (V)
T , JUNCTION TEMPERATURE ( C)
GS
J
FIGURE 8. TRANSFER CHARACTERISTICS
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
1.2
1.0
0.8
0.6
0.4
1.2
V
= V , I = 250µA
GS
DS
D
I
= 250µA
D
1.1
1.0
0.9
0.8
-80
-40
0
40
80
120
160
-80
-40
0
40
80
120
160
o
o
T , JUNCTION TEMPERATURE ( C)
T , JUNCTION TEMPERATURE ( C)
J
J
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
©2001 Fairchild Semiconductor Corporation
HUFA75307T3ST Rev. B
HUFA75307T3ST
Typical Performance Curves (Continued)
500
10
V
= 0V, f = 1MHz
WAVEFORMS IN
DESCENDING ORDER:
V
= 30V
GS
ISS
DD
C
C
C
= C
+ C
GS GD
= C
RSS
OSS
GD
DS
I
I
I
= 2.6A
= 1.5A
= 0.5A
D
D
D
8
6
4
2
0
400
300
200
100
0
= C
+ C
GD
C
C
C
ISS
OSS
RSS
0
2
4
Q , GATE CHARGE (nC)
6
8
0
10
20
30
40
50
60
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
g
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
Test Circuits and Waveforms
V
DS
BV
DSS
L
t
P
V
DS
I
VARY t TO OBTAIN
P
AS
+
-
V
DD
R
REQUIRED PEAK I
G
AS
V
DD
V
GS
DUT
t
P
I
AS
0V
0
0.01Ω
t
AV
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
V
DS
V
Q
g(TOT)
R
DD
L
V
DS
V
= 20V
GS
V
Q
GS
g(10)
+
-
V
DD
V
= 10V
V
GS
GS
DUT
V
= 2V
GS
I
0
g(REF)
Q
g(TH)
I
g(REF)
0
FIGURE 16. GATE CHARGE TEST CIRCUIT
FIGURE 17. GATE CHARGE WAVEFORM
©2001 Fairchild Semiconductor Corporation
HUFA75307T3ST Rev. B
HUFA75307T3ST
Test Circuits and Waveforms (Continued)
V
t
t
DS
ON
OFF
t
d(OFF)
t
d(ON)
t
t
f
R
L
r
V
DS
90%
90%
+
V
GS
V
DD
10%
10%
0
-
DUT
90%
50%
R
GS
V
GS
50%
PULSE WIDTH
10%
V
GS
0
FIGURE 18. SWITCHING TIME TEST CIRCUIT
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, T
thermal resistance of the heat dissipating path determines
, and the
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse applications
can be evaluated using the Fairchild device Spice thermal
model or manually utilizing the normalized maximum
transient thermal impedance curve.
J(MAX)
the maximum allowable device power dissipation, P
,
D(MAX)
in an application. Therefore the application’s ambient
o
o
temperature, T ( C), and thermal resistance R
( C/W)
A
θJA
is never exceeded.
must be reviewed to ensure that T
J(MAX)
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
200
R
= 75.9 -19.3 ln(AREA)
θJA
(T
– T )
J(MAX)
R
A
(EQ. 1)
P
= --------------------------------------------
D(MAX)
θJA
o
2
147 C/W - 0.026in
150
100
o
2
In using surface mount devices such as the SOT-223
128 C/W - 0.068in
o
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of the
2
110 C/W - 0.171in
P
is complex and influenced by many factors:
D(MAX)
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
50
0.01
0.1
AREA, TOP COPPER AREA (in )
1.0
2
2. The number of copper layers and the thickness of the
board.
FIGURE 20. THERMAL RESISTANCE vs MOUNTING PAD
AREA
3. The use of external heat sinks.
4. The use of thermal vias.
Displayed on the curve are the three R values listed in
the Electrical Specifications table. The three points were
θJA
5. Air flow and board orientation.
chosen to depict the compromise between the copper board
area, the thermal resistance and ultimately the power
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
dissipation, P
. Thermal resistances corresponding to
D(MAX)
other component side copper areas can be obtained from
Figure 20 or by calculation using Equation 2. The area, in
square inches is the top copper area including the gate and
source pads.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 20
defines the R
for the device as a function of the top
θJA
R
= 75.9 – 19.3 × ln(Area)
(EQ. 2)
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
θJA
©2001 Fairchild Semiconductor Corporation
HUFA75307T3ST Rev. B
HUFA75307T3ST
PSPICE Electrical Model
.SUBCKT HUFA75307T3ST 2 1 3 ;
rev 7/25/97
CA 12 8 3.5e-10
CB 15 14 3.7e-10
CIN 6 8 2.26e-10
LDRAIN
DPLCAP
10
DRAIN
2
5
RLDRAIN
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
RSLC1
51
DBREAK
+
RSLC2
5
ESLC
11
51
-
50
EBREAK 11 7 17 18 57.4
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
+
-
17
DBODY
RDRAIN
6
ESG
8
EBREAK 18
-
EVTHRES
+
16
21
+
-
EVTEMP 20 6 18 22 1
19
MWEAK
LGATE
EVTEMP
+
8
RGATE
GATE
1
6
-
18
22
MMED
IT 8 17 1
9
20
MSTRO
8
RLGATE
LDRAIN 2 5 1e-9
LGATE 1 9 1.4e-9
LSOURCE 3 7 3.1e-10
LSOURCE
CIN
SOURCE
3
7
K1 LGATE LSOURCE 0.131
RSOURCE
RLSOURCE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
S1A
S2A
RBREAK
12
15
13
8
14
13
17
18
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 7.0e-3
RGATE 9 20 1.9
RLDRAIN 2 5 10
RLGATE 1 9 14
RLSOURCE 3 7 3
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 5.6e-2
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
RVTEMP
19
-
S1B
S2B
13
CB
CA
IT
14
+
+
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
22
RVTHRES
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*50),3))}
.MODEL DBODYMOD D (IS = 2.6e-13 RS = 2.34e-2 IKF = 5.5 N = 0.995 TRS1 = 2.8e-3 TRS2 = 1.1e-5 CJO = 3.7e-10 TT = 3.5e-8 M = 0.46
+ XTI = 5.5)
.MODEL DBREAKMOD D (RS = 0. 5IKF = 0.1 N = 1 TRS1 = 3e- 3TRS2 = -5e-5)
.MODEL DPLCAPMOD D (CJO = 5.6e-1 0IS = 1e-3 0N = 10 M = 0.92)
.MODEL MMEDMOD NMOS (VTO = 3.25 KP = 1.8 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.9)
.MODEL MSTROMOD NMOS (VTO = 3.68 KP = 13.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 2.83 KP = 0.03 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 19 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1.08e- 3TC2 = 5e-7)
.MODEL RDRAINMOD RES (TC1 = 1.7e-2 TC2 = 1e-4)
.MODEL RSLCMOD RES (TC1 = 1e-9 TC2 = 1e-4)
.MODEL RSOURCEMOD RES (TC1 = 3.3e-3 TC2 = 1e-9)
.MODEL RVTHRESMOD RES (TC1 = -1.9e-3 TC2 = -4e-6)
.MODEL RVTEMPMOD RES (TC1 = -2.9e- 3TC2 = 2.2e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -7.1 VOFF= -4)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4 VOFF= -7.1)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.01 VOFF= 1.9)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 1.9 VOFF= 0.01)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
©2001 Fairchild Semiconductor Corporation
HUFA75307T3ST Rev. B
HUFA75307T3ST
SPICE Thermal Model
JUNCTION
7
REV 15 Nov 97
HUFA75307T3ST
RTHERM1
CTHERM1
CTHERM1 7 6 7.5e-5
CTHERM2 6 5 3.5e-4
CTHERM3 5 4 1.2e-3
CTHERM4 4 3 1.5e-2
CTHERM5 3 2 6.9e-2
CTHERM6 2 1 4.5e-1
6
RTHERM2
RTHERM3
RTHERM4
RTHERM5
RTHERM6
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
RTHERM1 7 6 7.5e-2
RTHERM2 6 5 2.0e-1
RTHERM3 5 4 1.2
RTHERM4 4 3 3.3
RTHERM5 3 2 28
RTHERM6 2 1 90
5
4
3
2
1
CASE
©2001 Fairchild Semiconductor Corporation
HUFA75307T3ST Rev. B
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not intended to be an exhaustive list of all such trademarks.
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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
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Rev. H4
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