ISL9N304AP3 [FAIRCHILD]
N-Channel Logic Level UltraFET Trench MOSFETs 30V, 75A, 4.5mз; N沟道逻辑电平UltraFET沟槽MOSFET的30V ， 75A ， 4.5mз
| 型号： | ISL9N304AP3 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | N-Channel Logic Level UltraFET Trench MOSFETs 30V, 75A, 4.5mз |
| 文件： | 总11页 (文件大小：196K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 2002
PWM Optimized
ISL9N304AP3/ISL9N304AS3ST
®
N-Channel Logic Level UltraFET Trench MOSFETs
30V, 75A, 4.5mΩ
General Description
Features
This device employs a new advanced trench MOSFET
technology and features low gate charge while maintaining
low on-resistance.
•
•
•
•
•
•
Fast switching
r
r
= 0.0036Ω (Typ), V = 10V
GS
DS(ON)
DS(ON)
= 0.0060Ω (Typ), V = 4.5V
Optimized for switching applications, this device improves
the overall efficiency of DC/DC converters and allows
operation to higher switching frequencies.
GS
Q (Typ) = 38nC, V = 5V
g
GS
Q
(Typ) = 13nC
gd
ISS
Applications
•
DC/DC converters
C
(Typ) = 4075pF
SOURCE
DRAIN
(FLANGE)
DRAIN
GATE
D
S
GATE
G
SOURCE
DRAIN
(FLANGE)
TO-263
TO-220
MOSFET Maximum Ratings T = 25°C unless otherwise noted
A
Symbol
Parameter
Ratings
30
Units
V
V
Drain to Source Voltage
Gate to Source Voltage
V
V
DSS
GS
±20
Drain Current
o
75
74
A
A
Continuous (T = 25 C, V = 10V)
C
GS
o
I
Continuous (T = 100 C, V = 4.5V)
C GS
D
o
o
Continuous (T = 25 C, V = 10V, R = 43 C/W)
θJA
20
A
C
GS
Pulsed
Figure 4
A
Power dissipation
Derate above 25 C
145
0.97
W
W/ C
P
o
o
D
o
T , T
Operating and Storage Temperature
-55 to 175
C
J
STG
Thermal Characteristics
o
R
R
R
Thermal Resistance Junction to Case TO-220, TO-263
1.03
62
C/W
θJC
θJA
θJA
o
Thermal Resistance Junction to Ambient TO-220, TO-263
C/W
2
o
Thermal Resistance Junction to Ambient TO-263, 1in copper pad area
43
C/W
Package Marking and Ordering Information
Device Marking
N304AS
Device
Package
TO-263AB
TO-220AB
Reel Size
330mm
Tube
Tape Width
Quantity
ISL9N304AS3ST
ISL9N304AP3
24mm
N/A
800 units
50
N304AP
©2002 Fairchild Semiconductor Corporation
Rev. B, February 2002
Final Draft
Electrical Characteristics T = 25°C unless otherwise noted
A
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
B
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
I
= 250µA, V = 0V
30
-
-
-
-
-
-
V
VDSS
D
GS
V
V
V
= 25V
= 0V
1
DS
GS
GS
I
I
µA
nA
DSS
o
T
= 150
-
250
±100
C
= ±20V
-
GSS
On Characteristics
V
Gate to Source Threshold Voltage
V
= V , I = 250µA
1
-
-
3
V
GS(TH)
GS
DS
D
I
I
= 75A, V = 10V
0.0036 0.0045
0.0060 0.0075
D
D
GS
r
Drain to Source On Resistance
Ω
DS(ON)
= 74A, V = 4.5V
-
GS
Dynamic Characteristics
C
C
C
Input Capacitance
-
-
-
4075
830
380
70
-
-
pF
pF
pF
nC
nC
nC
nC
nC
ISS
V
= 15V, V = 0V,
GS
DS
Output Capacitance
OSS
RSS
f = 1MHz
Reverse Transfer Capacitance
Total Gate Charge at 10V
Total Gate Charge at 5V
Threshold Gate Charge
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
-
Q
Q
Q
Q
Q
V
V
V
= 0V to 10V
= 0V to 5V
= 0V to 1V
105
57
5.8
-
g(TOT)
g(5)
g(TH)
gs
GS
GS
GS
-
-
-
-
38
V
= 15V
DD
= 74A
I
3.9
11
D
I = 1.0mA
g
13
-
gd
Switching Characteristics (V = 4.5V)
GS
t
t
t
t
t
t
Turn-On Time
Turn-On Delay Time
Rise Time
-
-
-
-
-
-
-
137
ns
ns
ns
ns
ns
ns
ON
14
77
33
20
-
-
-
d(ON)
V
V
= 15V, I = 20A
r
DD
GS
D
= 4.5V, R = 2.4Ω
Turn-Off Delay Time
Fall Time
-
GS
d(OFF)
-
f
Turn-Off Time
79
OFF
Switching Characteristics (V = 10V)
GS
t
t
t
t
t
t
Turn-On Time
Turn-On Delay Time
Rise Time
-
-
-
-
-
-
-
113
ns
ns
ns
ns
ns
ns
ON
9
-
d(ON)
67
51
19
-
-
V
V
= 15V, I = 20A
r
DD
GS
D
= 10V, R = 2.4Ω
Turn-Off Delay Time
Fall Time
-
-
GS
d(OFF)
f
Turn-Off Time
104
OFF
Unclamped Inductive Switching
t
Avalanche Time
I
= 3.8A, L = 3.0mH
255
-
-
µs
AV
D
Drain-Source Diode Characteristics
I
I
I
I
= 74A
= 35A
-
-
-
-
-
-
-
-
1.25
1.0
27
V
V
SD
SD
SD
SD
V
Source to Drain Diode Voltage
SD
t
Reverse Recovery Time
= 74A, dI /dt = 100A/µs
ns
nC
rr
SD
Q
Reverse Recovered Charge
= 74A, dI /dt = 100A/µs
16
RR
SD
©2002 Fairchild Semiconductor Corporation
Rev. B, February 2002
Final Draft
Typical Characteristic
1.2
1.0
0.8
0.6
0.4
0.2
0
80
60
40
V
= 10V
GS
V
= 4.5V
GS
20
0
0
25
50
75
100
150
175
125
o
25
50
75
100
125
150
175
o
T
, CASE TEMPERATURE ( C)
T , CASE TEMPERATURE ( C)
C
C
Figure 1. Normalized Power Dissipation vs
Ambient Temperature
Figure 2. Maximum Continuous Drain Current vs
Case Temperature
1
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
P
DM
0.1
t
1
t
2
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t /t
1
2
PEAK T = P
x Z
x R
+ T
J
DM
θJC
θJC C
0.01
-5
-4
-3
-2
-1
-0
-1
10
10
10
10
t, RECTANGULAR PULSE DURATION (s)
10
10
10
Figure 3. Normalized Maximum Transient Thermal Impedance
2000
o
T
= 25 C
C
FOR TEMPERATURES
o
ABOVE 25 C DERATE PEAK
1000
CURRENT AS FOLLOWS:
V
= 10V
GS
175 - T
150
C
I = I
25
V
= 5V
GS
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
100
50
-5
-4
-3
-2
-1
0
1
10
10
10
10
t, PULSE WIDTH (s)
10
10
10
Figure 4. Peak Current Capability
©2002 Fairchild Semiconductor Corporation
Rev. B, February 2002
Final Draft
Typical Characteristic (Continued)
150
150
120
90
60
30
0
PULSE DURATION = 80µs
V
= 4.5V
GS
V
= 10V
GS
DUTY CYCLE = 0.5% MAX
V
= 3.5V
V
= 15V
GS
DD
120
90
60
30
0
V
= 3V
GS
o
T
= 175 C
J
o
T
= 25 C
o
C
T
= 25 C
J
PULSE DURATION = 80µs
o
T
= -55 C
J
DUTY CYCLE = 0.5% MAX
1.5
2
2.5
3
3.5
4
0
0.5
1
1.5
2
V
, GATE TO SOURCE VOLTAGE (V)
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
GS
Figure 5. Transfer Characteristics
Figure 6. Saturation Characteristics
10
9
2
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
8
I
= 75A
1.5
D
7
6
I
= 20A
1
D
5
4
V
= 10V, I = 75A
D
GS
0.5
3
-80
-40
0
40
80
120
160
200
2
4
6
8
10
o
V
, GATE TO SOURCE VOLTAGE (V)
T , JUNCTION TEMPERATURE ( C)
GS
J
Figure 7. Drain to Source On Resistance vs Gate
Voltage and Drain Current
Figure 8. Normalized Drain to Source On
Resistance vs Junction Temperature
1.4
1.2
I = 250µA
D
V
= V , I = 250µA
GS
DS
D
1.2
1.0
0.8
0.6
0.4
0.2
1.1
1.0
0.9
-80
-40
0
40
80
120
160
200
-80
-40
0
40
80
120
160
200
o
o
T , JUNCTION TEMPERATURE ( C)
T , JUNCTION TEMPERATURE ( C)
J
J
Figure 9. Normalized Gate Threshold Voltage vs
Junction Temperature
Figure 10. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
©2002 Fairchild Semiconductor Corporation
Rev. B, February 2002
Final Draft
Typical Characteristic (Continued)
10
8
6000
V
= 15V
DD
C
= C + C
GS GD
ISS
C
C
+ C
OSS
DS GD
6
C
= C
GD
RSS
1000
4
WAVEFORMS IN
DESCENDING ORDER:
2
I
I
= 75A
= 20A
D
D
V
= 0V, f = 1MHz
GS
300
0
0.1
1
10
30
0
15
30
45
60
75
V
, DRAIN TO SOURCE VOLTAGE (V)
Q , GATE CHARGE (nC)
DS
g
Figure 11. Capacitance vs Drain to Source
Voltage
Figure 12. Gate Charge Waveforms for Constant
Gate Currents
250
500
V
= 4.5V, V = 15V, I = 20A
DD D
GS
V
= 10V, V = 15V, I = 20A
GS DD D
200
150
100
50
400
300
200
100
0
t
f
t
t
d(OFF)
r
t
d(ON)
t
f
t
d(OFF)
t
r
t
d(ON)
0
0
10
20
30
40
50
0
10
20
30
40
50
R
, GATE TO SOURCE RESISTANCE (Ω)
R , GATE TO SOURCE RESISTANCE (Ω)
GS
GS
Figure 13. Switching Time vs Gate Resistance
Figure 14. Switching Time vs Gate Resistance
Test Circuits and Waveforms
V
BV
DSS
DS
t
P
V
DS
L
I
AS
V
DD
VARY t TO OBTAIN
P
+
-
R
REQUIRED PEAK I
G
AS
V
DD
V
GS
DUT
t
P
I
0V
AS
0
0.01Ω
t
AV
Figure 15. Unclamped Energy Test Circuit
Figure 16. Unclamped Energy Waveforms
©2002 Fairchild Semiconductor Corporation
Rev. B, February 2002
Final Draft
Test Circuits and Waveforms (Continued)
V
DS
V
Q
g(TOT)
DD
R
L
V
DS
V
= 10V
GS
Q
g(5)
V
GS
+
-
V
V
= 5V
DD
V
GS
GS
V
= 1V
DUT
GS
0
I
g(REF)
Q
g(TH)
Q
Q
gd
gs
I
g(REF)
0
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
V
t
t
DS
ON
OFF
t
d(OFF)
t
d(ON)
t
t
f
R
L
r
V
DS
90%
90%
+
-
V
GS
V
DD
10%
10%
0
DUT
90%
50%
R
GS
V
GS
50%
PULSE WIDTH
10%
V
GS
0
Figure 19. Switching Time Test Circuit
Figure 20. Switching Time Waveforms
©2002 Fairchild Semiconductor Corporation
Rev. B, February 2002
Final Draft
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, T , and the
thermal resistance of the heat dissipating path determines
80
60
40
20
JM
R
= 26.51+ 19.84/(0.262+Area)
θJA
the maximum allowable device power dissipation, P , in an
DM
application.
Therefore the application’s ambient
o
o
temperature, T ( C), and thermal resistance R
( C/W)
A
θJA
must be reviewed to ensure that T
is never exceeded.
JM
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
(T
– T )
JM
Z
A
(EQ. 1)
P
= ------------------------------
DM
θJA
In using surface mount devices such as the TO-263
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
0.1
1
10
2
power dissipation ratings. Precise determination of P
complex and influenced by many factors:
is
AREA, TOP COPPER AREA (in )
DM
Figure 21. Thermal Resistance vs Mounting
Pad Area
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the R
for the device as a function of the top
θJA
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
Displayed on the curve are R
values listed in the
θJA
Electrical Specifications table. The points were chosen to
depict the compromise between the copper board area, the
thermal resistance and ultimately the power dissipation,
P
.
DM
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2. R
is defined as the natural log of the area
θJA
times a coefficient added to a constant. The area, in square
inches is the top copper area including the gate and source
pads.
19.84
(0.262 + A rea)
R
= 26.51 + ------------------------------------
(EQ. 2)
θJA
©2002 Fairchild Semiconductor Corporation
Rev. B, February 2002
Final Draft
PSPICE Electrical Model
.SUBCKT ISL9N304AP3 2
CA 12 8 3.3e-9
1 3 ;rev June 2001
Cb 15 14 2.8e-9
Cin 6 8 3.68e-9
LDRAIN
DPLCAP
DRAIN
2
5
10
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
RLDRAIN
RSLC1
51
DBREAK
+
RSLC2
5
ESLC
11
51
Ebreak 11 7 17 18 32
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
-
+
50
-
17
DBODY
RDRAIN
6
8
EBREAK 18
-
ESG
EVTHRES
+
16
21
+
-
19
8
MWEAK
LGATE
EVTEMP
RGATE
GATE
1
+
6
-
18
22
It 8 17 1
MMED
9
20
MSTRO
8
RLGATE
Lgate 1 9 5.61e-9
Ldrain 2 5 1.0e-9
Lsource 3 7 1.98e-9
LSOURCE
CIN
SOURCE
3
7
RSOURCE
RLSOURCE
RLgate 1 9 56.1
RLdrain 2 5 10
RLsource 3 7 19.8
S1A
S2A
RBREAK
12
15
13
8
14
13
17
18
RVTEMP
19
S1B
S2B
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
13
CB
CA
IT
14
-
+
+
VBAT
6
8
5
8
EGS
EDS
+
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 0.5e-3
Rgate 9 20 2.31
-
-
8
22
RVTHRES
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 2.6e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*500),3))}
.MODEL DbodyMOD D (IS=4e-11 N=1.04 RS=2.3e-3 TRS1=2e-3 TRS2=1e-6
+ CJO=1.85e-9 M=0.51 TT=5e-11 XTI=1)
.MODEL DbreakMOD D (RS=0.38 TRS1=2e-3 TRS2=-8.9e-6)
.MODEL DplcapMOD D (CJO=1.45e-9 IS=1e-30 N=10 M=0.47)
.MODEL MstroMOD NMOS (VTO=2.02 KP=200 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MmedMOD NMOS (VTO=1.55 KP=5 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2.31)
.MODEL MweakMOD NMOS (VTO=1.31 KP=0.1 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=23.1 RS=0.1)
.MODEL RbreakMOD RES (TC1=1e-3 TC2=-7e-7)
.MODEL RdrainMOD RES (TC1=1.7e-2 TC2=4.7e-5)
.MODEL RSLCMOD RES (TC1=4.6e-3 TC2=5e-6)
.MODEL RsourceMOD RES (TC1=1e-3 TC2=1e-6)
.MODEL RvthresMOD RES (TC1=-2.9e-3 TC2=-8e-6)
.MODEL RvtempMOD RES (TC1=-1.4e-3 TC2=1e-6)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-6 VOFF=-3)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3 VOFF=-6)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.4 VOFF=0.1)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.1 VOFF=-0.4)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
©2002 Fairchild Semiconductor Corporation
Rev. B, February 2002
Final Draft
SABER Electrical Model
REV June 2001
template ISL9N304AP3 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=4e-11,nl=1.04,rs=2.3e-3,trs1=2e-3,trs2=1e-6,cjo=1.85e-9,m=0.51,tt=5e-11,xti=1)
dp..model dbreakmod = (rs=0.38,trs1=2e-3,trs2=-8.9e-6)
dp..model dplcapmod = (cjo=1.45e-9,isl=10e-30,nl=10,m=0.47)
m..model mstrongmod = (type=_n,vto=2.02,kp=200,is=1e-30, tox=1)
m..model mmedmod = (type=_n,vto=1.55,kp=5,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=1.31,kp=0.1,is=1e-30, tox=1,rs=0.1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-6,voff=-3)
LDRAIN
DPLCAP
DRAIN
2
5
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-3,voff=-6)
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-0.4,voff=0.1)
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.1,voff=-0.4)
c.ca n12 n8 = 3.3e-9
10
RLDRAIN
RSLC1
51
c.cb n15 n14 = 2.8e-9
RSLC2
c.cin n6 n8 = 3.68e-9
ISCL
DBREAK
11
50
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
-
RDRAIN
6
8
ESG
DBODY
EVTHRES
+
16
21
+
-
19
8
MWEAK
spe.ebreak n11 n7 n17 n18 = 32
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
LGATE
EVTEMP
RGATE
GATE
1
+
6
-
18
22
EBREAK
+
MMED
9
20
MSTRO
8
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
17
18
-
RLGATE
LSOURCE
CIN
SOURCE
3
7
RSOURCE
i.it n8 n17 = 1
RLSOURCE
S1A
S2A
RBREAK
12
l.lgate n1 n9 = 5.61e-9
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 1.98e-9
15
13
8
14
13
17
18
RVTEMP
19
S1B
S2B
13
CB
CA
res.rlgate n1 n9 = 56.1
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 19.8
IT
14
-
+
+
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
22
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
RVTHRES
res.rbreak n17 n18 = 1, tc1=1e-3,tc2=-7e-7
res.rdrain n50 n16 = 0.5e-3, tc1=1.7e-2,tc2=4.7e-5
res.rgate n9 n20 = 2.31
res.rslc1 n5 n51 = 1e-6, tc1=4.6e-3,tc2=5e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 2.6e-3, tc1=1e-3,tc2=1e-6
res.rvthres n22 n8 = 1, tc1=-2.9e-3,tc2=-8e-6
res.rvtemp n18 n19 = 1, tc1=-1.4e-3,tc2=1e-6
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/500))** 3))
©2002 Fairchild Semiconductor Corporation
Rev. B, February 2002
Final Draft
SPICE Thermal Model
JUNCTION
th
REV June 2001
ISL9N304AP3
CTHERM1 TH 6 3e-4
CTHERM2 6 5 3.5e-3
CTHERM3 5 4 6.5e-3
CTHERM4 4 3 7.5e-3
CTHERM5 3 2 7.6e-3
CTHERM6 2 TL 3e-2
RTHERM1
RTHERM2
RTHERM3
RTHERM4
RTHERM5
RTHERM6
CTHERM1
6
RTHERM1 TH 6 1e-4
RTHERM2 6 5 6e-3
RTHERM3 5 4 3e-2
RTHERM4 4 3 9.5e-2
RTHERM5 3 2 2.9e-1
RTHERM6 2 TL 4.5e-1
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
5
SABER Thermal Model
SABER thermal model ISL9N304AP3
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 =3e-4
ctherm.ctherm2 6 5 =3.5e-3
ctherm.ctherm3 5 4 =6.5e-3
ctherm.ctherm4 4 3 =7.5e-3
ctherm.ctherm5 3 2 =7.6e-3
ctherm.ctherm6 2 tl =3e-2
4
3
2
rtherm.rtherm1 th 6 =1e-4
rtherm.rtherm2 6 5 =6e-3
rtherm.rtherm3 5 4 =3e-2
rtherm.rtherm4 4 3 =9.5e-2
rtherm.rtherm5 3 2 =2.9e-1
rtherm.rtherm6 2 tl =4.5e-1
}
tl
CASE
©2002 Fairchild Semiconductor Corporation
Rev. B, February 2002
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FASTr™
FRFET™
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SuperSOT™-6
SuperSOT™-8
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Advance Information
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Rev. H4
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