MM74C02N [FAIRCHILD]
Quad 2-Input NAND Gate . Quad 2-Input NOR Gate . Hex Inverter; 四2输入与非门。四2输入或非门。六反相器
| 型号： | MM74C02N |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Quad 2-Input NAND Gate . Quad 2-Input NOR Gate . Hex Inverter |
| 文件： | 总6页 (文件大小：81K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 1987
Revised January 1999
MM74C00 • MM74C02 • MM74C04
Quad 2-Input NAND Gate •
Quad 2-Input NOR Gate •
Hex Inverter
All inputs are protected from damage due to static dis-
charge by diode clamps to VCC and GND.
General Description
The MM74C00, MM74C02, and MM74C04 logic gates
employ complementary MOS (CMOS) to achieve wide
power supply operating range, low power consumption,
high noise immunity and symmetric controlled rise and fall
times. With features such as this the 74C logic family is
close to ideal for use in digital systems. Function and pin
out compatibility with series 74 devices minimizes design
time for those designers already familiar with the standard
74 logic family.
Features
■ Wide supply voltage range: 3V to 15V
■ Guaranteed noise margin: 1V
■ High noise immunity: 0.45 VCC (typ.)
■ Low power consumption: 10 nW/package (typ.)
■ Low power: TTL compatibility:
Fan out of 2 driving 74L
Ordering Code:
Order Number Package Number
Package Description
MM74C00M
MM74C00N
MM74C02N
MM74C04M
MM74C04N
M14A
N14A
M14A
M14A
N14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagrams
Pin Assignments for DIP and SOIC
MM74C00
MM74C02
Top View
Top View
MM74C04
Top View
© 1999 Fairchild Semiconductor Corporation
DS005877.prf
www.fairchildsemi.com
Lead Temperature
Absolute Maximum Ratings(Note 1)
(Soldering, 10 seconds)
300°C
Voltage at Any Pin
−0.3V to VCC + 0.3V
Operating Temperature Range
Storage Temperature Range
Operating VCC Range
Maximum VCC Voltage
Power Dissipation (PD)
Dual-In-Line
−40°C to +85°C
−65°C to +150°C
3.0V to 15V
18V
Note 1: “Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. Except for “Operating Tempera-
ture Range” they are not meant to imply that the devices should be oper-
ated at these limits. The table of “Electrical Characteristics” provides
conditions for actual device operation.
700 mW
500 mW
Small Outline
DC Electrical Characteristics
Min/Max limits apply across the guaranteed temperature range unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS TO CMOS
V
V
V
V
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Output Voltage
Logical “0” Output Voltage
V
V
V
V
V
V
V
V
V
V
V
= 5.0V
= 10V
= 5.0V
= 10V
3.5
8.0
V
V
IN(1)
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
1.5
2.0
V
IN(0)
V
= 5.0V, I = −10 µA
4.5
9.0
V
OUT(1)
OUT(0)
O
= 10V, I = −10 µA
V
O
= 5.0V, I = 10 µA
0.5
1.0
1.0
V
O
= 10V, I = 10 µA
V
O
I
I
I
Logical “1” Input Current
Logical “0” Input Current
Supply Current
= 15V, V = 15V
0.005
−0.005
0.01
µA
µA
µA
IN(1)
IN(0)
CC
IN
= 15V, V = 0V
−1.0
IN
= 15V
15
LOW POWER TO CMOS
V
V
V
V
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Output Voltage
Logical “0” Output Voltage
74C, V = 4.75V
V − 1.5
CC
V
V
V
V
IN(1)
CC
74C, V = 4.75V
0.8
0.4
IN(0)
CC
74C, V = 4.75V, I = −10 µA
4.4
OUT(1)
OUT(0)
CC
O
74C, V = 4.75V, I = 10 µA
CC
O
CMOS TO LOW POWER
V
V
V
V
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Output Voltage
Logical “0” Output Voltage
74C, V = 4.75V
4.0
2.4
V
V
V
V
IN(1)
CC
74C, V = 4.75V
1.0
0.4
IN(0)
CC
74C, V = 4.75V, I = −360 µA
OUT(1)
OUT(0)
CC
O
74C, V = 4.75V, I = 360 µA
CC
O
OUTPUT DRIVE (see Family Characteristics Data Sheet) T = 25°C (short circuit current)
A
I
I
I
I
Output Source Current
Output Source Current
Output Sink Current
Output Sink Current
V
V
V
V
= 5.0V, V
= 0V, V
= 0V
= 0V
−1.75
−8.0
1.75
8.0
mA
mA
mA
mA
SOURCE
SOURCE
SINK
CC
CC
CC
CC
IN(0)
OUT
= 10V, V
= 0V, V
IN(0)
OUT
= 5.0V, V
= 5.0V, V
= V
IN(1)
IN(1)
OUT CC
= 10V, V
= 10V, V
= V
OUT CC
SINK
AC Electrical Characteristics (Note 2)
T
A = 25°C, C = 50 pF, unless otherwise specified
L
Symbol
Parameter
Conditions
Min
Typ
Max
Units
MM74C00, MM74C02, MM74C04
t
, t
Propagation Delay Time to
Logical “1” or “0”
V
V
= 5.0V
= 10V
50
30
6.0
12
90
60
ns
ns
pF
pF
pd0 pd1
CC
CC
C
C
Input Capacitance
(Note 3)
Per Gate or Inverter (Note 4)
IN
Power Dissipation Capacitance
PD
Note 2: AC Parameters are guaranteed by DC correlated testing.
Note 3: Capacitance is guaranteed by periodic testing.
Note 4: C determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics Application Note—
PD
AN-90.
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2
Typical Performance Characteristics
Gate Transfer Characteristics
Propagation Delay vs
Ambient Temperature
MM74C00, MM74C02, MM74C04
Guaranteed Noise Margin
Over Temperature vs VCC
Propagation Delay vs
Ambient Temperature
MM74C00, MM74C02, MM74C04
Propagation Delay Time vs
Load Capacitance
MM74C00, MM74C02, MM74C04
Power Dissipation vs Frequency
MM74C00, MM74C02, MM74C04
3
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Switching Time Waveforms and AC Test Circuit
CMOS to CMOS
Delays measured with input t , t ≤ 20 ns.
r
f
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4
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
Package Number M14A
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N14A
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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