MM74C373WMX [FAIRCHILD]
Bus Driver, CMOS Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, PLASTIC, SO-20;
| 型号： | MM74C373WMX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Bus Driver, CMOS Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, PLASTIC, SO-20 触发器 锁存器 |
| 文件： | 总11页 (文件大小：127K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 1987
Revised January 2004
MM74C373 • MM74C374
3-STATE Octal D-Type Latch •
3-STATE Octal D-Type Flip-Flop
General Description
Features
■ Wide supply voltage range: 3V to 15V
The MM74C373 and MM74C374 are integrated, comple-
mentary MOS (CMOS), 8-bit storage elements with 3-
STATE outputs. These outputs have been specially
designed to drive high capacitive loads, such as one might
find when driving a bus, and to have a fan out of 1 when
driving standard TTL. When a high logic level is applied to
the OUTPUT DISABLE input, all outputs go to a high
impedance state, regardless of what signals are present at
the other inputs and the state of the storage elements.
■ High noise immunity: 0.45 VCC (typ.)
■ Low power consumption
■ TTL compatibility:
Fan out of 1driving standard TTL
■ Bus driving capability
■ 3-STATE outputs
■ Eight storage elements in one package
The MM74C373 is an 8-bit latch. When LATCH ENABLE is
high, the Q outputs will follow the D inputs. When LATCH
ENABLE goes low, data at the D inputs, which meets the
set-up and hold time requirements, will be retained at the
outputs until LATCH ENABLE returns high again.
■ Single CLOCK/LATCH ENABLE and OUTPUT DIS-
ABLE control inputs
■ 20-pin dual-in-line package with 0.300” centers takes
half the board space of a 24-pin package
The MM74C374 is an 8-bit, D-type, positive-edge triggered
flip-flop. Data at the D inputs, meeting the set-up and hold
time requirements, is transferred to the Q outputs on posi-
tive-going transitions of the CLOCK input.
Both the MM74C373 and the MM74C374 are being assem-
bled in 20-pin dual-in-line packages with 0.300” pin cen-
ters.
Ordering Code:
Order Number Package Number
Package Description
MM74C373M
(Note 1)
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
MM74C373N
MM74C374N
N20A
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Note 1: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2004 Fairchild Semiconductor Corporation
DS005906
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Connection Diagrams
MM74C373
MM74C374
Top View
Top View
Truth Tables
MM74C373
MM74C374
Output
Clock
D
Q
Output
LATCH
D
Q
Disable
Disable
ENABLE
L
L
L
L
H
H
L
H
L
L
L
H
H
L
H
L
H
L
L
H
X
X
X
X
Q
L
X
X
Q
Q
H
X
Hi-Z
Hi-Z
L = LOW logic level
H = HIGH logic level
X = Irrelevant
= LOW-to-HIGH logic level transition
Q = Preexisting output level
Hi-Z = High impedance output state
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2
Block Diagrams
MM74C373 (1 of 8 Latches)
MM74C374 (1 of 8 Flip-Flops)
3
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Absolute Maximum Ratings(Note 2)
Voltage at Any Pin
−0.3V to VCC + 0.3V
Operating Temperature Range (TA)
MM74C373
−55°C to +125°C
−65°C to +150°C
Storage Temperature Range (TS)
Power Dissipation
Dual-In-Line
700 mW
500 mW
3V to 15V
18V
Small Outline
Note 2: “Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. Except for “Operating Tempera-
ture Range” they are not meant to imply that the devices should be oper-
ated at these limits. The table of “Electrical Characteristics” provides
conditions for actual device operation.
Operating VCC Range
Absolute Maximum VCC
Lead Temperature (TL)
(Soldering, 10 seconds)
260°C
DC Electrical Characteristics
Min/Max limits apply across temperature range unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS TO CMOS
VIN(1)
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Output Voltage
Logical “0” Output Voltage
V
V
V
V
V
V
V
V
V
V
V
V
V
CC = 5V
CC = 10V
CC = 5V
CC = 10V
3.5
8.0
V
V
V
V
VIN(0)
1.5
2.0
VOUT(1)
CC = 5V, IO = −10 µA
CC = 10V, IO = −10 µA
CC = 5V, IO = 10 µA
CC = 10V, IO = 10 µA
CC = 15V, VIN = 15V
CC = 15V, VIN = 0V
CC = 15V, VO = 15V
CC = 15V, VO = 0V
CC = 15V
4.5
9.0
VOUT(0)
0.5
1.0
1.0
IIN(1)
IIN(0)
IOZ
Logical “1” Input Current
Logical “0” Input Current
3-STATE Leakage Current
0.005
−0.005
0.005
−0.005
0.05
µA
µA
−1.0
−1.0
1.0
µA
µA
ICC
Supply Current
300
CMOS/LPTTL INTERFACE
VIN(1)
Logical “1” Input Voltage
V
V
V
V
V
CC = 4.75V
V
V
CC − 1.5
V
V
VIN(0)
Logical “0” Input Voltage
Logical “1” Output Voltage
CC = 4.75V
0.8
0.4
VOUT(1)
CC = 4.75V, IO = −360 µA
CC = 4.75V, IO = −1.6 mA
CC = 4.75V, IO = 1.6 mA
CC − 0.4
V
V
2.4
VOUT(0)
Logical “0” Output Voltage
OUTPUT DRIVE (Short Circuit Current)
ISOURCE
ISOURCE
ISINK
Output Source Current
Output Source Current
V
CC = 5V, VOUT = 0V
−12
−24
6
−24
−48
12
mA
mA
mA
mA
T
A = 25°C (Note 3)
CC = 10V, VOUT = 0V
A = 25°C (Note 3)
CC = 5V, VOUT = VCC
A = 25°C (Note 3)
CC = 10V, VOUT = VCC
A = 25°C (Note 3)
V
T
Output Sink Current
(N-Channel)
V
T
ISINK
Output Sink Current
(N-Channel)
V
24
48
T
Note 3: These are peak output current capabilities. Continuous output current is rated at 12 mA max.
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4
AC Electrical Characteristics (Note 4)
MM74C373, TA = 25°C, CL = 50 pF, tr = tf = 20 ns, unless otherwise noted
Symbol
Parameter
Propagation Delay,
Conditions
CC = 5V, CL = 50 pF
Min
Typ
165
70
Max
330
140
390
170
Units
tpd0, tpd1
V
V
V
V
LATCH ENABLE to Output
CC = 10V, CL = 50 pF
CC = 5V, CL = 150 pF
CC = 10V, CL = 150 pF
ns
195
85
tpd0, tpd1
Propagation Delay Data
In to Output
LATCH ENABLE = VCC
VCC = 5V, CL = 50 pF
VCC = 10V, CL = 50 pF
VCC = 5V, CL = 150 pF
VCC = 10V, CL = 150 pF
155
70
310
140
370
170
ns
185
85
tSET-UP
Minimum Set-Up Time Data In
to CLOCK/LATCH ENABLE
tHOLD = 0 ns
VCC = 5V
70
35
140
70
ns
MHz
ns
V
CC = 10V
fMAX
Maximum LATCH ENABLE
Frequency
VCC = 5V
3.5
4.5
6.7
9.0
VCC = 10V
tPWH
Minimum LATCH ENABLE
Pulse Width
VCC 5V
75
55
150
110
VCC = 10V
tr, tf
Maximum LATCH ENABLE
Rise and Fall Time
V
CC = 5V
NA
NA
µs
VCC = 10V
t1H, t0H
Propagation Delay OUTPUT
DISABLE to High Impedance
State (from a Logic Level)
Propagation Delay OUTPUT
DISABLE to Logic Level
(from High Impedance State)
Transition Time
RL = 10k, CL = 5 pF
VCC = 5V
105
60
210
120
ns
ns
ns
VCC = 10V
tH1, tH0
RL = 10k, CL = 50 pF
V
V
V
V
V
V
CC = 5V
105
45
210
90
CC = 10V
tTHL, tTLH
CC = 5V, CL = 50 pF
CC = 10V, CL = 50 pF
CC = 5V, CL = 150 pF
CC = 10V, CL = 150 pF
65
130
70
35
110
70
220
140
CLE
Input Capacitance
Input Capacitance
LE Input (Note 5)
OUTPUT DISABLE
Input (Note 5)
7.5
7.5
10
10
pF
pF
COD
CIN
Input Capacitance
Output Capacitance
Any Other Input (Note 5)
High Impedance
5
7.5
15
pF
pF
COUT
10
State (Note 5)
CPD
Power Dissipation Capacitance
Per Package (Note 6)
200
pF
Note 4: AC Parameters are guaranteed by DC correlated testing.
Note 5: Capacitance is guaranteed by periodic testing.
Note 6: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics Application Note
AN-90.
5
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AC Electrical Characteristics (Note 7)
MM74C374, TA = 25°C, CL = 50 pF, tr = tf = 20 ns, unless otherwise noted
Symbol
Parameter
Propagation Delay,
Conditions
CC = 5V, CL = 50 pF
Min
Typ
150
65
Max
300
130
360
160
Units
tpd0, tpd1
V
V
V
V
CLOCK to Output
CC = 10V, CL = 50 pF
CC = 5V, CL = 150 pF
CC = 10V, CL = 150 pF
ns
180
80
tSET-UP
Minimum Set-Up Time Data In
to CLOCK/LATCH ENABLE
tHOLD = 0 ns
VCC = 5V
VCC = 10V
VCC = 5V
VCC = 10V
VCC = 5V
VCC = 10V
70
35
70
50
7.0
10
140
70
ns
ns
tPWH, tPWL Minimum CLOCK Pulse Width
140
100
fMAX
Maximum CLOCK Frequency
3.5
5
MHz
t
1H, t0H
Propagation Delay OUTPUT
DISABLE to High Impedance
State (from a Logic Level)
Propagation Delay OUTPUT
DISABLE to Logic Level
(from High Impedance State)
Transition Time
RL = 10k, CL = 50 pF
VCC = 5V
105
60
210
120
ns
ns
ns
µs
VCC = 10V
tH1, tH0
RL = 10k, CL = 50 pF
V
V
V
V
V
V
V
V
CC = 5V
105
45
210
90
CC = 10V
tTHL, tTLH
CC = 5V, CL = 50 pF
CC = 10V, CL = 50 pF
CC = 5V, CL = 150 pF
CC = 10V, CL = 150 pF
CC = 5V
65
130
70
35
110
70
220
140
tr, tf
Maximum CLOCK Rise
and Fall Time
15
5
>2000
>2000
7.5
CC = 10V
CCLK
COD
Input Capacitance
Input Capacitance
CLOCK Input (Note 8)
OUTPUT DISABLE
Input (Note 8)
10
10
pF
pF
7.5
CIN
Input Capacitance
Output Capacitance
Any Other Input (Note 8)
High Impedance
5
7.5
15
pF
pF
COUT
10
State (Note 8)
CPD
Power Dissipation Capacitance
Per Package (Note 9)
250
pF
Note 7: AC Parameters are guaranteed by DC correlated testing.
Note 8: Capacitance is guaranteed by periodic testing.
Note 9: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics Application Note
AN-90.
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6
Typical Performance Characteristics
MM74C373
MM74C373, MM74C374
Change in Propagation Delay
per pF of Load Capacitance
(∆tPD/pF) vs Power Supply Voltage
Propagation Delay, LATCH ENABLE to Output
vs Load Capacitance
MM74C373
MM74C373, MM74C374
Propagation Delay, Data In to Output
vs Load Capacitance
Output Sink Current vs VOUT
MM74C373
MM74C373, MM74C374
Propagation Delay, CLOCK to Output
vs Load Capacitance
Source Current vs VCC − VOUT
7
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Typical Applications
Data Bus Interfacing Element
Simple, Latching, Octal, LED Indicator
Driver with Blanking for Use as Data Display,
Bus Monitor, µP Front Panel Display, Etc.
3-STATE Test Circuits and Switching Time Waveforms
t1H, tH1
t0H, tH0
t1H, CL = 5 pF
t0H, CL = 5 pF
tH1, CL = 50 pF
tH0, CL = 50 pF
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8
Switching Time Waveforms
MM74C373
Output Disable = GND
MM74C374
Output Disable = GND
9
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Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
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10
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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11
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