MM74C905N [FAIRCHILD]
12-Bit Successive Approximation Register; 12位逐次逼近寄存器
| 型号： | MM74C905N |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 12-Bit Successive Approximation Register |
| 文件： | 总8页 (文件大小：75K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 1987
Revised January 1999
MM74C905
12-Bit Successive Approximation Register
General Description
Features
The MM74C905 CMOS 12-bit successive approximation
register contains all the digit control and storage necessary
for successive approximation analog-to-digital conversion.
Because of the unique capability of CMOS to switch to
each supply rail without any offset voltage, it can also be
used in digital systems as the control and storage element
in repetitive routines.
■ Wide supply voltage range: 3.0V to 15V
■ Guaranteed noise margin: 1.0V
■ High noise immunity: 0.45 VCC (typ)
■ Low power TTL compatibility: Fan out of 2 driving 74L
■ Provision for register extension or truncation
■ Operates in START/STOP or continuous conversion
mode
■ Drive ladder switches directly. For 10 bits or less with
50k/100k R/2R ladder network
Ordering Code:
Order Number Package Number
Package Description
MM74C905N
N24A
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600” Wide
Connection Diagram
Pin Assignments for DIP
© 1999 Fairchild Semiconductor Corporation
DS005910.prf
www.fairchildsemi.com
Truth Table
Time
tn
Inputs
Outputs
D
X
S
L
E
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
D0
X
Q11
X
Q10
X
Q9
X
Q8
X
Q7
X
Q6
X
Q5
Q4
X
Q3
X
Q2
X
Q1
X
Q0
X
CC
X
0
1
X
H
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
H
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
2
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
D11
D11
D11
D11
D11
D11
D11
D11
D11
D11
D11
D11
D11
H
L
H
H
H
H
H
H
H
H
H
H
3
D10
D10
D10
D10
D10
D10
D10
D10
D10
D10
D10
D10
NC
L
H
H
H
H
H
H
H
H
H
4
D9
D9
D9
D9
D9
D9
D9
D9
D9
D9
D9
NC
L
H
H
H
H
H
H
H
H
5
D8
D8
D8
D8
D8
D8
D8
D8
D8
D8
NC
L
H
H
H
H
H
H
H
6
D7
D7
D7
D7
D7
D7
D7
D7
D7
NC
L
H
H
H
H
H
H
7
D6
D6
D6
D6
D6
D6
D6
D6
NC
L
H
H
H
H
H
8
D5
D5
D5
D5
D5
D5
D5
NC
L
H
H
H
H
9
D4
D4
D4
D4
D4
D4
NC
L
H
H
H
10
11
12
13
14
D3
D3
D3
D3
D3
NC
L
H
H
D2
D2
D2
D2
NC
L
H
D1
D1
D1
NC
L
D0
D0
NC
X
L
X
X
NC
H = HIGH Level
L = LOW Level
X = Don’t Care
NC = No Change
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2
Absolute Maximum VCC
Lead Temperature (TL)
(Soldering, 10 seconds)
16V
Absolute Maximum Ratings(Note 1)
Voltage at Any Pin
−0.3V to VCC+0.3V
260°C
Operating Temperature Range (TA)
Storage Temperature Range (TS)
Power Dissipation (PD)
Dual-In-Line
−40°C to +85°C
−65°C to +150°C
Note 1: “Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. Except for “Operating Tempera-
ture Range” they are not meant to imply that the devices should be oper-
ated at these limits. The table of “Electrical Characteristics” provides
conditions for actual device operation.
700 mW
500 mW
Small Outline
Operating VCC Range
3.0V to 15V
DC Electrical Characteristics
Min/Max limits apply across temperature range unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS TO CMOS
V
V
V
V
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Output Voltage
Logical “0” Output Voltage
V
V
V
V
V
V
V
V
V
V
V
= 5.0V
= 10V
= 5.0V
= 10V
3.5
8.0
V
V
IN(1)
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
1.5
2.0
V
IN(0)
V
= 5.0V, I = −10 µA
4.5
9.0
V
OUT(1)
OUT(0)
O
= 10V, I = −10 µA
V
O
= 5.0V, I = 10 µA
0.5
1.0
1.0
V
O
= 10V, I = 10 µA
V
O
I
I
I
Logical “1” Input Current
Logical “0” Input Current
Supply Current
= 15V, V = 15V
0.005
−0.005
0.05
µA
µA
µA
IN(1)
IN(0)
CC
IN
= 15V, V = 0V
−1.0
IN
= 15V
300
CMOS/LPTTL INTERFACE
V
V
V
V
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Output Voltage
Logical “0” Output Voltage
V
V
V
V
= 4.75V
= 4.75V
V − 1.5
CC
V
V
V
V
IN(1)
CC
CC
CC
CC
0.8
0.4
IN(0)
= 4.75V, I = −360 µA
2.4
OUT(1)
OUT(0)
O
= 4.75V, I = 360 µA
O
OUTPUT DRIVE (See Family Characteristics Data Sheet)
I
I
I
I
Output Source Current
(P-Channel)
V
= 5.0V, V
= 0V
= 0V
−1.75
−8.0
−3.3
−15
3.6
mA
mA
mA
SOURCE
SOURCE
SINK
CC
OUT
OUT
T
= 25°C
A
Output Source Current
(P-Channel)
V
= 10V, V
CC
T
= 25°C
A
Output Sink Current
(N-Channel)
V
= 5.0V, V
= V
1.75
CC
OUT
CC
T
= 25°C
A
Output Sink Current
(N-Channel)
V
= 10V, V
= V
SINK
CC
OUT
CC
T
= 25°C
8.0
16
mA
A
V
V
= 10V ±5%
CC
R
R
Q11–Q0 Outputs
Q11–Q0 Outputs
= V − 0.3V
150
350
230
Ω
SOURCE
OUT
CC
T
= 25°C
A
V
V
= 10V ±5%
SINK
CC
= 0.3V
80
Ω
OUT
T
= 25°C
A
3
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AC Electrical Characteristics (Note 2)
T
A = 25°C, C = 50 pF, unless otherwise specified
L
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
Propagation Delay Time from
Clock Input to Outputs
V
V
= 5.0V
= 10V
200
80
350
150
ns
ns
pd
CC
CC
(Q0–Q11) (t
)
pd(Q)
t
t
Propagation Delay Time from
Clock Input to D0 (t
V
V
V
V
= 5.0V
= 10V
= 5.0V
= 10V
180
70
325
125
350
150
ns
ns
ns
ns
pd
pd
CC
CC
CC
CC
)
pd(D0)
Propagation Delay Time from
Register Enable (E) to Output
190
75
(Q11) (t
)
pd(E)
t
t
t
t
Propagation Delay Time from
Clock to CC (t
V
V
V
V
V
V
V
V
V
V
V
V
= 5.0V
= 10V
= 5.0V
= 10V
= 5.0V
= 10V
= 5.0V
= 10V
= 5.0V
= 10V
= 5.0V
= 10V
190
75
350
ns
ns
pd
S
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
)
0.50
pd(CC)
Data Input Set-Up Time
80
30
ns
ns
Start Input Set-Up Time
80
ns
S
30
ns
Minimum Clock Pulse Width
Maximum Clock Rise and Fall Time
Maximum Clock Frequency
250
100
125
50
ns
W
ns
t , t
15
µs
r
f
5.0
µs
f
2.0
5.0
4.0
10
10
5
MHz
MHz
pF
pF
pF
MAX
C
C
C
Clock Input Capacitance
Input Capacitance
Clock Input (Note 3)
Any other Input (Note 3)
(Note 4)
CK
IN
Power Dissipation Capacitance
100
PD
Note 2: AC Parameters are guaranteed by DC correlated testing.
Note 3: Capacitance is guaranteed by periodic testing.
Note 4: C determines the no load AC power consumption of any CMOS device. For complete explanation, see Family Characteristics Application Note—
PD
AN-90.
Typical Performance Characteristics
RSINK vs Temperature
RSOURCE vs Temperature
•These points are guaranteed by automatic testing.
•These points are guaranteed by automatic testing.
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4
Timing Diagram
5
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Switching Time Waveforms
USER NOTES FOR A/D CONVERSION
LSB and using the complement of the MSB Q11 as the sign
bit.
The register can be used with either current switches that
require a low voltage level to turn the switch ON or current
switches that require a high voltage level to turn the switch
ON. If current switches are used which turn ON with a low
logic level, the resulting digit output from the register is
active low. That is, a logic “1” is represented as a low volt-
age level. If current switches are used which turn ON with a
high logic level, the resulting digit output is active high. A
logic “1” is represented as a high voltage level.
If the register is truncated and operated in the continuous
conversion mode, a lock-up condition may occur on power-
ON. This situation can be overcome by making the START
input the “OR” function of CC and the appropriate register
output.
The register, by suitable selection of register ladder net-
work, can be used to perform either binary or BCD conver-
sion.
For a maximum error of ±½ LSB, the comparator must be
biased. If current switches that require a high voltage level
to turn ON are used, the comparator should be biased +½
LSB and if the current switches require a low logic level to
turn ON, then the comparator must be biased −½ LSB.
The register outputs can drive the 10 bits or less with 50k/
100k R/2R ladder network directly for VCC = 10V or higher.
In order to drive the 12-bit 50k/100k ladder network and
have the ±½ LSB resolution, the MM74C902 or
MM74C904 is used as buffers, three buffers for MSB
(Q11), two buffers for Q10, and one buffer for Q9.
The register can be used to perform 2's complement con-
version by offsetting the comparator one half full range +½
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6
Typical Applications
12-Bit Successive Approximation A-to-D Converter,
Operating in Continuous 8–Bit Truncated Mode
12-Bit Successive Approximation A-to-D Converter, Operating in
Continuous Mode, Drives the 50k/100k Ladder Network Directly
Definition of Terms
CP: Register clock input.
Q11: True register MSB output.
CC: Conversion complete—this output remains at VOUT(1)
during a conversion and goes to VOUT(0) when conversion
is complete.
Q11: Complement of register MSB output.
Qi (i = 0 to 11): Register outputs.
S: Start input—holding start input at VIN(0) for at least one
D: Serial data input—connected to comparator output in A-
to-D applications.
clock period will initiate a conversion by setting MSB (Q11)
at VOUT(0) and all other output (Q10–Q0) at VOUT(1). If set-
E: Register enable —this input is used to expand the
length of the register. When E is at VIN(1) Q11 is forced to
up time requirements are met, a conversion may be initi-
ated by holding start input at VIN(0) for less than one clock
VOUT(1) and inhibits conversion. When not used for expan-
sion E must be connected to VIN(0) (GND).
period.
DO: Serial data output—D input delayed by one clock
period.
7
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Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600” Wide
Package Number N24A
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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