MM74HC126N [FAIRCHILD]
3-STATE Quad Buffers; 3 -STATE QUAD BUFFERS型号: | MM74HC126N |
厂家: | FAIRCHILD SEMICONDUCTOR |
描述: | 3-STATE Quad Buffers |
文件: | 总6页 (文件大小:84K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
September 1983
Revised February 1999
MM74HC125/MM74HC126
3-STATE Quad Buffers
condition, whereas the MM74HC126 require the control
input to be low to put the output into high impedance.
General Description
The MM74HC125 and MM74HC126 are general purpose
3-STATE high speed non-inverting buffers utilizing
advanced silicon-gate CMOS technology. They have high
drive current outputs which enable high speed operation
even when driving large bus capacitances. These circuits
possess the low power dissipation of CMOS circuitry, yet
have speeds comparable to low power Schottky TTL cir-
cuits. Both circuits are capable of driving up to 15 low
power Schottky inputs.
All inputs are protected from damage due to static dis-
charge by diodes to VCC and ground.
Features
■ Typical propagation delay: 13 ns
■ Wide operating voltage range: 2–6V
■ Low input current: 1 µA maximum
■ Low quiescent current: 80 µA maximum (74HC)
■ Fanout of 15 LS-TTL loads
The MM74HC125 require the 3-STATE control input C to
be taken high to put the output into the high impedance
Ordering Code:
Order Number Package Number
Package Description
MM74HC125M
MM74HC125SJ
MM74HC125MTC
MM74HC125N
MM74HC126M
MM74HC126SJ
MM74HC126MTC
MM74HC126N
M14A
M14D
MTC14
N14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
M14A
M14D
MTC14
N14A
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. (Tape and Reel not available in N14A.)
Connection Diagrams
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View (MM74HC126)
Top View (MM74HC125)
Truth Tables
Inputs
Output
Inputs
Output
A
H
L
C
L
Y
H
L
A
H
L
C
H
H
L
Y
H
L
L
X
H
Z
X
Z
© 1999 Fairchild Semiconductor Corporation
DS005308.prf
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Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating
Conditions
Supply Voltage (VCC
DC Input Voltage (VIN
DC Output Voltage (VOUT
Clamp Diode Current (IIK, IOK
)
−0.5 to +7.0V
−1.5 to VCC +1.5V
−0.5 to VCC +0.5V
±20 mA
Min Max Units
)
Supply Voltage (VCC
DC Input or Output Voltage
(VIN, VOUT
)
2
0
6
V
V
)
VCC
)
)
DC Output Current, per pin (IOUT
)
±35 mA
Operating Temperature Range (TA)
Input Rise or Fall Times (tr, tf)
−40 +85
°C
DC VCC or GND Current, per pin
(ICC
)
±70 mA
V
V
V
CC = 2.0V
CC = 4.5V
CC = 6.0V
1000 ns
Storage Temperature Range (TSTG
Power Dissipation (PD)
(Note 3)
)
−65°C to +150°C
500
400
ns
ns
600 mW
500 mW
Note 1: Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
S.O. Package only
Note 2: Unless otherwise specified all voltages are referenced to ground.
Lead Temperature (TL)
(Soldering 10 seconds)
Note 3: Power Dissipation temperature derating — plastic “N” package: −
12 mW/°C from 65°C to 85°C.
260°C
DC Electrical Characteristics (Note 4)
T
= 25°C
T
= −40 to 85°C
T = −40 to 125°C
A
A
A
V
Symbol
Parameter
Conditions
Units
CC
Typ
Guaranteed Limits
V
Minimum HIGH Level
Input Voltage
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
1.5
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
V
V
V
V
V
V
IH
3.15
4.2
V
V
Maximum LOW Level
Input Voltage
0.5
0.5
0.5
IL
1.35
1.8
1.35
1.8
1.35
1.8
Minimum HIGH Level
Output Voltage
V
= V or V
IL
2.0
4.5
6.0
1.9
1.9
1.9
OH
IN
IH
|I
| ≤ 20 µA
4.4
4.4
4.4
OUT
5.9
5.9
5.9
V
= V or V
IH IL
IN
|I
|I
| ≤ 6.0 mA
| ≤ 7.8 mA
4.5V
6.0V
2.0V
4.5V
6.0V
4.2
5.7
0
3.98
5.48
0.1
3.84
5.34
0.1
3.7
5.2
0.1
0.1
0.1
V
V
V
V
V
OUT
OUT
V
Maximum LOW Level
Output Voltage
V
= V or V
IH IL
OL
IN
|I
| ≤ 20 µA
0
0.1
0.1
OUT
0
0.1
0.1
V
= V or V
IH IL
IN
|I
|I
| ≤ 6.0 mA
| ≤ 7.8 mA
4.5V
6.0V
6.0V
0.2
0.2
0.26
0.26
±0.5
0.33
0.33
±5
0.4
0.4
±10
V
V
OUT
OUT
I
Maximum 3-STATE Output
Leakage Current
V
V
= V or V
IL
µA
OZ
IN
IH
= V or GND
OUT
CC
C
= Disabled
n
I
I
Maximum Input Current
Maximum Quiescent
Supply Current
V
V
= V or GND
6.0V
6.0V
±0.1
±1.0
±1.0
µA
µA
IN
IN
CC
= V or GND
8.0
80
160
CC
IN
CC
I
= 0 µA
OUT
Note 4: For a power supply of 5V ±10% the worst case output voltages (V , and V ) occur for HC at 4.5V. Thus the 4.5V values should be used when
OH
OL
designing with this supply. Worst case V and V occur at V =5.5V and 4.5V respectively. (The V value at 5.5V is 3.85V.) The worst case leakage current
IH
IL
CC
IH
(I , I , and I ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
IN CC
OZ
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2
AC Electrical Characteristics
V
CC = 5V, TA = 25°C, C = 45 pF, t = t = 6 ns
L
r
f
Guaranteed
Limit
Symbol
Parameter
Conditions
Typ
Units
t
t
t
t
t
, t
Maximum
13
18
25
25
25
25
ns
PHL PLH
Propagation Delay Time
Maximum
R
= 1 kΩ
13
17
18
13
ns
ns
ns
ns
PZH
L
Output Enable Time to HIGH Level
Maximum
R
C
R
= 1 kΩ
= 5 pF
= 1 kΩ
PHZ
L
L
L
Output Disable Time from HIGH Level
Maximum
PZL
Output Enable Time to LOW Level
Maximum
R
C
= 1 kΩ
= 5 pF
PLZ
L
Output Disable Time from LOW Level
L
AC Electrical Characteristics
V
CC = 2.0V to 6.0V, CL = 50 pF, t = t = 6 ns (unless otherwise specified)
r f
T
= 25°C
T
= −40 to 85°C T = −40 to 125°C
A
A
A
V
Symbol
Parameter
Conditions
Units
CC
Typ
40
14
12
35
14
12
25
14
12
25
14
12
35
15
13
30
7
Guaranteed Limits
t
t
t
t
t
t
, t
Maximum Propagation
Delay Time
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
100
125
25
150
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
PHL PLH
20
17
21
25
, t
Maximum Propagation
Delay Time
C
R
R
= 150 pF
= 1 kΩ
130
26
163
33
195
39
PLH PHL
L
L
L
22
28
39
, t
Maximum Output
Enable Time
125
25
156
31
188
38
PZH PZL
21
26
31
, t
Maximum Output
Disable Time
= 1 kΩ
125
25
156
31
188
38
PHZ PLZ
21
26
31
, t
Maximum Output
Enable Time
C
R
= 150 pF
= 1 kΩ
140
28
175
35
210
42
PZL PZH
L
L
24
30
36
, t
Maximum Output
Rise and Fall Time
C
= 50 pF
60
75
90
TLH THL
L
12
15
18
6
10
13
15
C
C
C
Input Capacitance
5
10
10
10
IN
Output Capacitance Outputs
Power Dissipation
15
20
20
20
OUT
PD
(per gate)
Enabled
Disabled
Capacitance (Note 5)
45
6
pF
pF
2
Note 5: C determines the no load dynamic power consumption, P = C
V
f + I
V
, and the no load dynamic current consumption,
PD
D
PD CC
CC CC
I
= C
V
f + I
.
CC
S
PD CC
3
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Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
Package Number M14A
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
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4
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N14A
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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