MM74HC244WMX_NL [FAIRCHILD]
Bus Driver, HC/UH Series, 2-Func, 4-Bit, True Output, CMOS, PDSO20, 0.300 INCH, MS-013, SOIC-20;
| 型号： | MM74HC244WMX_NL |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Bus Driver, HC/UH Series, 2-Func, 4-Bit, True Output, CMOS, PDSO20, 0.300 INCH, MS-013, SOIC-20 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总8页 (文件大小：102K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 1983
Revised May 2005
MM74HC244
Octal 3-STATE Buffer
General Description
The MM74HC244 is a non-inverting buffer and has two
Features
■ Typical propagation delay: 14 ns
active low enables (1G and 2G); each enable indepen-
■ 3-STATE outputs for connection to system buses
■ Wide power supply range: 2–6V
dently controls
4 buffers. This device does not have
Schmitt trigger inputs.
■ Low quiescent supply current: 80
■ Output current: 6 mA
A
These 3-STATE buffers utilize advanced silicon-gate
CMOS technology and are general purpose high speed
non-inverting buffers. They possess high drive current out-
puts which enable high speed operation even when driving
large bus capacitances. These circuits achieve speeds
comparable to low power Schottky devices, while retaining
the advantage of CMOS circuitry, i.e., high noise immunity,
and low power consumption. All three devices have a
fanout of 15 LS-TTL equivalent inputs.
All inputs are protected from damage due to static dis-
charge by diodes to VCC and ground.
Ordering Code:
Order Number Package Number
Package Description
MM74HC244WM
MM74HC244SJ
MM74HC244MTC
MM74HC244N
M20B
M20D
MTC20
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Truth Table
1G
L
1A
1Y
L
2G
L
2A
L
2Y
L
L
H
L
L
H
Z
L
H
L
H
Z
H
H
H
H
H
Z
H
Z
H
L
HIGH Level
LOW Level
Z
High Impedance
Top View
© 2005 Fairchild Semiconductor Corporation
DS005327
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Logic Diagram
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2
Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating
Conditions
Supply Voltage (VCC
DC Input Voltage (VIN
DC Output Voltage (VOUT
Clamp Diode Current (IIK, IOK
DC Output Current, per pin (IOUT
DC VCC or GND Current, per pin (ICC
)
0.5 to 7.0V
1.5 to VCC 1.5V
0.5 to VCC 0.5V
20 mA
Min
Max
Units
)
Supply Voltage (VCC
DC Input or Output Voltage
(VIN, VOUT
)
2
6
V
)
)
)
0
VCC
85
V
C
)
35 mA
Operating Temperature Range (TA)
Input Rise or Fall Times
(tr, tf) VCC 2.0V
40
)
70 mA
Storage Temperature Range (TSTG
Power Dissipation (PD)
(Note 3)
)
65 C to 150 C
1000
500
ns
ns
ns
VCC 4.5V
600 mW
500 mW
VCC 6.0V
400
S.O. Package only
Note 1: Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Lead Temperature (TL)
(Soldering 10 seconds)
Note 2: Unless otherwise specified all voltages are referenced to ground.
260 C
Note 3: Power Dissipation temperature derating — plastic “N” package:
12 mW/ C from 65 C to 85 C.
DC Electrical Characteristics (Note 4)
T
25 C
T
40 to 85 C
T
A
55 to 125 C
A
A
V
Symbol
Parameter
Conditions
Units
CC
Typ
Guaranteed Limits
V
Minimum HIGH Level
Input Voltage
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
1.5
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
V
V
V
IH
3.15
4.2
V
V
Maximum LOW Level
Input Voltage
0.5
0.5
0.5
IL
1.35
1.8
1.35
1.8
1.35
1.8
Minimum HIGH Level
Output Voltage
V
V
or V
IL
OH
IN
IH
IH
|I
|
20
A
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
V
V
V
OUT
V
V
V
or V
IL
IN
|I
|I
|
|
6.0 mA
7.8 mA
4.5V
6.0V
4.2
5.7
3.98
5.4
3.84
5.34
3.7
5.2
OUT
OUT
V
Maximum LOW Level
Output Voltage
V
or V
IL
OL
IN
IH
|I
|
20
A
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
OUT
V
V
or V
IL
IN
IH
|I
|I
|
|
6.0 mA
7.8 mA
4.5V
6.0V
6.0V
0.2
0.2
0.26
0.26
0.1
0.33
0.33
1.0
0.4
0.4
1.0
V
V
A
OUT
OUT
I
I
Maximum Input
Current
V
V
V
or GND
CC
IN
IN
Maximum 3-STATE
Output Leakage
Current
V
V
, or V
6.0V
6.0V
0.5
8.0
5
10
A
A
OZ
CC
IN
IH
IL
V
or GND
OUT
CC
G
V
IH
I
Maximum Quiescent
Supply Current
V
V
or GND
CC
80
160
IN
I
0 A
OUT
Note 4: For a power supply of 5V 10% the worst case output voltages (V , and V ) occur for HC at 4.5V. Thus the 4.5V values should be used when
OH
OL
designing with this supply. Worst case V and V occur at V
5.5V and 4.5V respectively. (The V value at 5.5V is 3.85V.) The worst case leakage cur-
IH
IH
IL
CC
rent (I , I , and I ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
IN CC
OZ
3
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AC Electrical Characteristics
V
5V, TA 25 C, tr tf 6 ns
Symbol Parameter
, t
CC
Guaranteed
Limit
Conditions
Typ
Units
t
t
t
Maximum Propagation
Delay
C
45 pF
14
20
ns
PHL PLH
L
, t
Maximum Enable Delay
to Active Output
R
C
R
C
1 k
17
15
28
25
ns
ns
PZH PZL
L
L
L
L
45 pF
1 k
, t
Maximum Disable Delay
from Active Output
PHZ PLZ
5 pF
AC Electrical Characteristics
V
2.0V-6.0V, CL 50 pF, tr tf 6 ns (unless otherwise specified)
CC
Symbol
, t
T
25 C
T
40 to 85 C
T
A
55 to 125 C
A
A
V
Parameter
Conditions
Units
CC
Typ
58
83
14
17
10
14
Guaranteed Limits
t
Maximum Propagation
Delay
C
C
C
C
C
C
R
C
C
C
C
C
C
R
C
50 pF
150 pF
50 pF
150 pF
50 pF
150 pF
1 k
2.0V
2.0V
4.5V
4.5V
6.0V
6.0V
115
145
208
29
171
246
34
ns
ns
ns
ns
ns
ns
PHL PLH
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
165
23
33
42
49
20
25
29
28
35
42
t
, t
Maximum Output Enable
Time
PZH PZL
50 pF
150 pF
50 pF
150 pF
50 pF
150 pF
1 k
2.0V
2.0V
4.5V
4.5V
6.0V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
75
100
15
30
13
17
75
15
13
150
200
30
189
252
38
224
298
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
40
50
60
26
32
38
34
43
51
t
t
, t
Maximum Output Disable
Time
150
30
189
38
224
45
PHZ PLZ
50 pF
26
32
38
, t
Maximum Output
Rise and Fall Time
60
75
90
TLH THL
12
15
18
10
13
15
C
Power Dissipation
(per buffer)
PD
Capacitance (Note 5)
G
G
V
V
12
50
5
pF
pF
pF
IH
IL
C
C
Maximum Input
Capacitance
10
20
10
20
10
20
IN
Maximum Output
Capacitance
10
pF
OUT
2
Note 5: C determines the no load dynamic power consumption, P
C
V
f
I
V
, and the no load dynamic current consumption,
PD
D
PD CC
CC CC
I
C
V
f
I
.
CC
S
PD CC
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4
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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8
相关型号：
MM74HC244WM_NL
Bus Driver, HC/UH Series, 2-Func, 4-Bit, True Output, CMOS, PDSO20, 0.300 INCH, LEAD FREE, MS-013, SOIC-20
FAIRCHILD
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