MM74HC4040MX [FAIRCHILD]
Binary Counter, HC/UH Series, Asynchronous, Negative Edge Triggered, 12-Bit, Up Direction, CMOS, PDSO16, 0.150 INCH, MS-012, SOIC-16;
| 型号： | MM74HC4040MX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Binary Counter, HC/UH Series, Asynchronous, Negative Edge Triggered, 12-Bit, Up Direction, CMOS, PDSO16, 0.150 INCH, MS-012, SOIC-16 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总9页 (文件大小：109K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 1984
Revised September 2001
MM74HC4020 • MM74HC4040
14-Stage Binary Counter • 12-Stage Binary Counter
These devices are pin equivalent to the CD4020 and
CD4040 respectively. All inputs are protected from damage
due to static discharge by protection diodes to VCC and
General Description
The MM74HC4020, MM74HC4040, are high speed binary
ripple carry counters. These counters are implemented uti-
ground.
lizing advanced silicon-gate CMOS technology to achieve
speed performance similar to LS-TTL logic while retaining
the low power and high noise immunity of CMOS.
Features
■ Typical propagation delay: 16 ns
The MM74HC4020 is
a 14 stage counter and the
MM74HC4040 is a 12-stage counter. Both devices are
incremented on the falling edge (negative transition) of the
input clock, and all their outputs are reset to a low level by
applying a logical high on their reset input.
■ Wide operating voltage range: 2–6V
■ Low input current: 1 µA maximum
■ Low quiescent current: 80 µA maximum (74HC Series)
■ Output drive capability: 10 LS-TTL loads
Ordering Code:
Order Number
MM74HC4020M
MM74HC4020SJ
MM74HC4020N
MM74HC4040M
MM74HC4040SJ
MM74HC4040MTC
MM74HC4040N
Package Number
M16A
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
M16D
N16E
M16A
M16D
MTC16
N16E
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
MM74HC4040
MM74HC4020
© 2001 Fairchild Semiconductor Corporation
DS005216
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Logic Diagrams
MM74HC4020
MM74HC4040
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2
Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating
Conditions
Supply Voltage (VCC
DC Input Voltage (VIN
DC Output Voltage (VOUT
Clamp Diode Current (ICD
DC Output Current, per pin (IOUT
DC VCC or GND Current, per pin (ICC
)
−0.5 to +7.0V
−1.5 to VCC +1.5V
−0.5 to VCC +0.5V
±20 mA
Min
Max
6
Units
)
Supply Voltage (VCC
DC Input or Output Voltage
(VIN, VOUT
)
2
0
V
V
)
VCC
)
)
)
±25 mA
Operating Temperature Range (TA) −40
Input Rise or Fall Times
+85
°C
)
±50 mA
Storage Temperature Range (TSTG
Power Dissipation (PD)
(Note 3)
)
−65°C to +150°C
(tr, tf) VCC = 2.0V
1000
500
ns
ns
ns
V
V
CC = 4.5V
CC = 6.0V
600 mW
500 mW
400
S.O. Package only
Note 1: Maximum Ratings are those values beyond which damage to the
device may occur.
Lead Temperature (TL)
(Soldering 10 seconds)
Note 2: Unless otherwise specified all voltages are referenced to ground.
260°C
Note 3: Power Dissipation temperature derating — plastic “N” package: −
12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics (Note 4)
T
A = 25°C
TA = −40 to 85°C TA = −55 to 125°C
VCC
Symbol
Parameter
Conditions
Units
Typ
Guaranteed Limits
VIH
Minimum HIGH Level Input
Voltage
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
1.5
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
V
V
V
3.15
4.2
VIL
Maximum LOW Level Input
Voltage
0.5
0.5
0.5
1.35
1.8
1.35
1.8
1.35
1.8
VOH
Minimum HIGH Level Output
Voltage
V
IN = VIH or VIL
|IOUT| ≤ 20 µA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
VIN = VIH or VIL
|IOUT| ≤ 4.0 mA
|IOUT| ≤ 5.2 mA
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
VOL
Maximum LOW Level Output
Voltage
V
IN = VIH or VIL
|IOUT| ≤ 20 µA
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN = VIH or VIL
|IOUT| ≤ 4.0 mA
|IOUT| ≤ 5.2 mA
4.5V
6.0V
6.0V
6.0V
0.2
0.2
.26
.26
0.33
0.33
±1.0
80
0.4
0.4
V
V
IIN
Maximum Input Current
Maximum Quiescent Supply
Current
V
IN = VCC or GND
IN = VCC or GND
±0.1
8.0
±1.0
160
µA
µA
ICC
V
I
OUT = 0 µA
Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage cur-
rent (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
3
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AC Electrical Characteristics
V
CC = 5V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns
Guaranteed
Symbol
Parameter
Conditions
Typ
Units
Limit
30
fMAX
Maximum Operating Frequency
Maximum Propagation
Delay Clock to Q
50
17
MHz
ns
tPHL, tPLH
(Note 5)
35
tPHL
tREM
tW
Maximum Propagation
Delay Reset to any Q
Minimum Reset
16
10
10
40
20
16
ns
ns
ns
Removal Time
Minimum Pulse Width
Note 5: Typical Propagation delay time to any output can be calculated using: tP = 17 + 12(N–1) ns; where N is the number of the output, QW, at VCC = 5V.
AC Electrical Characteristics
V
CC = 2.0V to 6.0V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified)
T
A = 25°C
TA = −40 to 85°C TA = −55 to 125°C
VCC
Symbol
fMAX
Parameter
Conditions
Units
Typ
10
40
50
80
21
18
80
18
15
72
24
20
Guaranteed Limits
Maximum Operating
Frequency
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
6
5
24
4
20
MHz
MHz
MHz
ns
30
35
28
24
t
PHL, tPLH
Maximum Propagation
Delay Clock to Q1
210
42
265
53
313
63
ns
36
45
53
ns
TPHL, tPLH Maximum Propagation
Delay Between Stages
from Qn to Qn+1
125
25
156
31
188
38
ns
ns
21
26
31
ns
tPHL
tREM
tW
Maximum Propagation
Delay Reset to any Q
(4020 and 4040)
Minimum Reset
240
48
302
60
358
72
ns
ns
41
51
61
ns
100
20
126
25
149
50
ns
Removal Time
ns
16
21
25
ns
Minimum Pulse Width
90
100
20
120
24
ns
16
ns
14
18
20
ns
t
TLH, tTHL
Maximum
30
10
9
75
95
110
22
ns
Output Rise
15
19
ns
and Fall Time
Maximum Input Rise and
Fall Time
13
16
19
ns
tr, tf
1000
500
400
1000
500
400
1000
500
400
ns
ns
ns
CPD
Power Dissipation
Capacitance (Note 6)
Maximum Input
Capacitance
(per package)
55
5
pF
CIN
10
10
10
pF
Note 6: CPD determines the no load dynamic power consumption, PD = CPD VCC2 f + ICC VCC, and the no load dynamic current consumption,
S = CPD VCC f + ICC
I
.
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4
Timing Diagram
5
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Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M16A
www.fairchildsemi.com
6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
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8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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9
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