MM74HC4316M [FAIRCHILD]

Quad Analog Switch with Level Translator; 四路模拟开关与电平转换器
MM74HC4316M
型号: MM74HC4316M
厂家: FAIRCHILD SEMICONDUCTOR    FAIRCHILD SEMICONDUCTOR
描述:

Quad Analog Switch with Level Translator
四路模拟开关与电平转换器

转换器 电平转换器 开关
文件: 总9页 (文件大小:109K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
February 1984  
Revised February 1999  
MM74HC4316  
Quad Analog Switch with Level Translator  
and outputs and digital inputs are protected from electro-  
static damage by diodes to VCC and ground.  
General Description  
The MM74HC4316 devices are digitally controlled analog  
switches implemented in advanced silicon-gate CMOS  
technology. These switches have low “ON” resistance and  
low “OFF” leakages. They are bidirectional switches, thus  
any analog input may be used as an output and vice-versa.  
Three supply pins are provided on the MM74HC4316 to  
implement a level translator which enables this circuit to  
operate with 0–6V logic levels and up to ±6V analog switch  
levels. The MM74HC4316 also has a common enable input  
in addition to each switch's control which when LOW will  
disable all switches to their OFF state. All analog inputs  
Features  
Typical switch enable time: 20 ns  
Wide analog input voltage range: ±6V  
Low “ON” resistance:  
50 typ. (VCCVEE = 4.5V) 30 typ. (VCCVEE = 9V)  
Low quiescent current: 80 µA maximum (74HC)  
Matched switch characteristics  
Individual switch controls plus a common enable  
Ordering Code:  
Order Number  
MM74HC4316M  
MM74HC4316SJ  
MM74HC4316MTC  
MM74HC4316N  
Package Number  
M16A  
Package Description  
16-Lead Small Outline Integrated Package (SOIC), JEDEC MS-012, 0.150” Narrow  
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-1536, 4.4mm Wide  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
M16D  
MTC16  
N16E  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Diagram  
Connection Diagram  
Pin Assignments for DIP, SOIC, SOP and TSSOP  
Top View  
Truth Table  
Inputs  
Switch  
I/O–O/I  
“OFF”  
“OFF”  
“ON”  
En  
H
L
CTL  
X
L
L
H
© 1999 Fairchild Semiconductor Corporation  
DS005369.prf  
www.fairchildsemi.com  
Absolute Maximum Ratings(Note 1)  
(Note 2)  
Recommended Operating  
Conditions  
Supply Voltage (VCC  
Supply Voltage (VEE  
DC Control Input Voltage (VIN  
DC Switch I/O Voltage (VIO  
Clamp Diode Current (IIK, IOK  
DC Output Current, per pin (IOUT  
DC VCC or GND Current, per pin (ICC  
)
0.5 to +7.5V  
+0.5 to 7.5V  
1.5 to VCC +1.5V  
EE0.5 to VCC +0.5V  
±20 mA  
Min  
Max  
6
Units  
)
Supply Voltage (VCC  
Supply Voltage (VEE  
DC Input or Output Voltage  
(VIN, VOUT  
)
2
0
V
V
)
)
6  
)
V
)
)
0
VCC  
V
)
±25 mA  
Operating Temperature Range (TA) 40  
Input Rise or Fall Times  
+85  
°C  
)
±50 mA  
Storage Temperature Range (TSTG  
Power Dissipation (PD)  
(Note 3)  
)
65°C to +150°C  
(tr, tf) VCC = 2.0V  
1000  
500  
400  
250  
ns  
ns  
ns  
ns  
VCC = 4.5V  
VCC = 6.0V  
VCC = 12.0V  
600 mW  
500 mW  
S.O. Package only  
Lead Temperature (TL)  
(Soldering 10 seconds)  
Note 1: Absolute Maximum Ratings are those values beyond which dam-  
age to the device may occur.  
260°C  
Note 2: Unless otherwise specified all voltages are referenced to ground.  
Note 3: Power Dissipation temperature derating — plastic “N” package: −  
12 mW/°C from 65°C to 85°C.  
DC Electrical Characteristics (Note 4)  
T
= 25°C  
T = −40 to 85°C T = −55 to 125°C  
A A  
A
V
V
CC  
Symbol  
Parameter  
Conditions  
Units  
EE  
Typ  
Guaranteed Limits  
V
Minimum HIGH Level  
Input Voltage  
2.0V  
4.5V  
6.0V  
2.0V  
4.5V  
6.0V  
4.5V  
1.5  
1.5  
3.15  
4.2  
0.5  
1.35  
1.8  
200  
105  
85  
1.5  
3.15  
4.2  
0.5  
1.35  
1.8  
220  
110  
90  
V
V
IH  
3.15  
4.2  
0.5  
1.35  
1.8  
170  
85  
V
V
Maximum LOW Level  
Input Voltage  
V
IL  
V
V
R
Minimum “ON” Resistance  
(Note 5)  
V
V
= V , I = 2.0 mA  
GND  
100  
40  
30  
100  
40  
50  
20  
10  
5
µA  
ON  
CTL  
IH  
S
= V to V  
EE  
4.5V 4.5V  
6.0V 6.0V  
IS  
CC  
(Figure 1)  
70  
GND  
GND  
2.0V  
4.5V  
180  
80  
215  
100  
75  
240  
120  
80  
V
V
= V , I = 2.0 mA  
IH S  
CTL  
= V or V  
4.5V 4.5V  
6.0V 6.0V  
60  
IS  
CC  
EE  
(Figure 1)  
40  
60  
70  
R
Maximum “ON” Resistance  
Matching  
V
V
= V  
IH  
GND  
4.5V  
15  
20  
20  
ON  
CTL  
= V to V  
4.5V 4.5V  
6.0V 6.0V  
10  
15  
15  
IS  
CC  
EE  
5
10  
15  
15  
I
I
Maximum Control  
Input Current  
V
= V or GND  
GND  
6.0V  
±0.1  
±1.0  
±1.0  
IN  
IN  
CC  
Maximum Switch “OFF”  
Leakage Current  
V
V
V
V
V
= V or V  
EE  
GND  
6.0V  
±60  
±600  
±600  
nA  
nA  
IZ  
OS  
CC  
= V or V  
CC  
6.0V 6.0V  
±100  
±1000  
±1000  
IS  
EE  
= V (Figure 2)  
CTL  
IL  
I
I
Maximum Switch “ON”  
Leakage Current  
= V to V  
GND  
6.0V  
±40  
±60  
±150  
±300  
±150  
±300  
nA  
nA  
IZ  
IS  
CC  
IH  
EE  
OS  
= V , V = OPEN 6.0V 6.0V  
CTL  
(Figure 3)  
Maximum Quiescent  
Supply Current  
V
= V or GND  
GND  
6.0V  
2.0  
8.0  
20  
80  
40  
µA  
µA  
CC  
IN  
CC  
I
= 0 µA  
6.0V 6.0V  
160  
OUT  
Note 4: For a power supply of 5V ±10% the worst case on resistances (R ) occurs for HC at 4.5V. Thus the 4.5V values should be used when designing  
ON  
with this supply. Worst case V and V occur at V =5.5V and 4.5V respectively. (The V value at 5.5V is 3.85V.) The worst case leakage current occurs  
IH  
IL  
CC  
IH  
for CMOS at the higher voltage and so the 5.5V values should be used.  
Note 5: At supply voltages (V –V ) approaching 2V the analog switch on resistance becomes extremely non-linear. Therefore it is recommended that  
CC  
EE  
these devices be used to transmit digital only when using these supply voltages.  
www.fairchildsemi.com  
2
AC Electrical Characteristics  
V
CC = 2.0V6.0V, VEE = 0V6V, C = 50 pF (unless otherwise specified)  
L
T
= +25°C  
T = −40°C to +85°C T = −55°C to +125°C  
A A  
A
V
V
CC  
Symbol  
Parameter  
Conditions  
Units  
EE  
Typ  
25  
5
Guaranteed Limits  
t
t
,
Maximum Propagation  
Delay Switch  
GND 2.0V  
GND 4.5V  
4.5V 4.5V  
6.0V 6.0V  
GND 2.0V  
GND 4.5V  
4.5V 4.5V  
6.0V 6.0V  
GND 2.0V  
GND 4.5V  
4.5V 4.5V  
6.0V 6.0V  
GND 2.0V  
GND 4.5V  
4.5V 4.5V  
6.0V 6.0V  
GND 2.0V  
GND 4.5V  
4.5V 4.5V  
6.0V 6.0V  
50  
10  
8
63  
13  
75  
15  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
PHL  
PLH  
In to Out  
4
12  
14  
3
7
11  
13  
t
t
,
Maximum Switch  
Turn “ON” Delay  
(Control)  
R
= 1 kΩ  
30  
20  
15  
14  
45  
25  
20  
20  
35  
20  
19  
18  
58  
28  
23  
21  
40  
100  
165  
35  
32  
30  
250  
50  
44  
44  
205  
41  
38  
36  
265  
53  
47  
47  
206  
43  
250  
53  
PZL  
L
PZH  
39  
48  
37  
45  
t
t
,
Maximum Switch  
Turn “OFF” Delay  
(Control)  
R
= 1 kΩ  
312  
63  
375  
75  
PHZ  
L
PLZ  
55  
66  
55  
66  
t
t
,
Maximum Switch  
Turn “ON” Delay  
(Enable)  
256  
52  
308  
62  
ns  
ns  
PZL  
PZH  
48  
57  
ns  
45  
54  
ns  
t
t
,
Maximum Switch  
Turn “OFF” Delay  
(Enable)  
330  
67  
400  
79  
ns  
PLZ  
ns  
PHZ  
59  
70  
ns  
59  
70  
ns  
f
Minimum Frequency  
Response (Figure 7)  
R
= 600, V = 2V  
PP  
0V  
4.5  
MHz  
MHz  
MAX  
L
IS  
at (V V /2)  
4.5V 4.5V  
CC  
EE  
20 log (V /V )= −3 dB (Note 6) (Note 7)  
OS IS  
Control to Switch  
Feedthrough Noise  
(Figure 8)  
R
C
= 600, F = 1 MHz  
= 50 pF  
0V 4.5V  
100  
250  
mV  
mV  
L
L
4.5V 4.5V  
(Note 7) (Note 8)  
Crosstalk Between  
any Two Switches  
(Figure 9)  
R
= 600, F = 1 MHz  
L
0V 4.5V  
52  
50  
dB  
dB  
4.5V 4.5V  
Switch OFF Signal  
Feedthrough Isolation  
(Figure 10)  
R
= 600, F = 1 MHz  
L
V
= V  
,
0V 4.5V  
42  
44  
dB  
dB  
CTL  
IL  
(Note 7) (Note 8)  
= 10 K, C = 50 pF,  
4.5V 4.5V  
THD  
Sinewave Harmonic  
Distortion  
R
L
L
F = 1 KHz  
(Figure 11)  
V
V
= 4V  
= 8V  
0V 4.5V 0.013  
4.5V 4.5V 0.008  
5
%
%
IS  
PP  
IS  
PP  
C
C
C
C
Maximum Control  
Input Capacitance  
Maximum Switch  
Input Capacitance  
Maximum Feedthrough  
Capacitance  
pF  
IN  
35  
0.5  
15  
pF  
pF  
pF  
IN  
V
= GND  
IN  
CTL  
Power Dissipation  
Capacitance  
PD  
Note 6: Adjust 0 dBm for F = 1 KHz (Null R /Ron Attenuation).  
L
Note 7: V is centered at V –V /2.  
IS  
CC  
EE  
Note 8: Adjust for 0 dBm.  
3
www.fairchildsemi.com  
AC Test Circuits and Switching Time Waveforms  
FIGURE 1. “ON” Resistance  
FIGURE 2. “OFF” Channel Leakage Current  
FIGURE 3. “ON” Channel Leakage Current  
FIGURE 4. tPHL, tPLH Propagation Delay Time Signal Input to Signal Output  
FIGURE 5. tPZL, tPLZ Propagation Delay Time Control to Signal Output  
FIGURE 6. tPZH, tPHZ Propagation Delay Time Control to Signal Output  
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4
AC Test Circuits and Switching Time Waveforms (Continued)  
FIGURE 7. Frequency Response  
FIGURE 8. Crosstalk: Control Input to Signal Output  
FIGURE 9. : Crosstalk Between Any Two Switches  
FIGURE 10. Switch OFF Signal Feedthrough Isolation  
FIGURE 11. Sinewave Distortion  
5
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Typical Performance Characteristics  
Typical “ON” Resistance  
Typical Crosstalk Between  
Any Two Switches  
Typical Frequency Response  
Special Considerations  
In certain applications the external load-resistor current  
the analog switch input pins, the voltage drop across the  
switch must not exceed 0.6V (calculated from the ON resis-  
tance).  
may include both VCC and signal line components. To  
avoid drawing VCC current when switch current flows into  
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6
Physical Dimensions inches (millimeters) unless otherwise noted  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow  
Package Number M16A  
16-Lead small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
Package Number M16D  
7
www.fairchildsemi.com  
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)  
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
Package Number MTC16  
www.fairchildsemi.com  
8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
Package Number N16E  
LIFE SUPPORT POLICY  
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT  
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD  
SEMICONDUCTOR CORPORATION. As used herein:  
1. Life support devices or systems are devices or systems  
which, (a) are intended for surgical implant into the  
body, or (b) support or sustain life, and (c) whose failure  
to perform when properly used in accordance with  
instructions for use provided in the labeling, can be rea-  
sonably expected to result in a significant injury to the  
user.  
2. A critical component in any component of a life support  
device or system whose failure to perform can be rea-  
sonably expected to cause the failure of the life support  
device or system, or to affect its safety or effectiveness.  
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.  

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