MM74HC573SJ [FAIRCHILD]
3-STATE Octal D-Type Latch; 三态八路D类锁存器
| 型号： | MM74HC573SJ |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 3-STATE Octal D-Type Latch |
| 文件： | 总8页 (文件大小：91K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 1983
Revised May 2000
MM74HC573
3-STATE Octal D-Type Latch
of what signals are present at the other inputs and the state
of the storage elements.
General Description
The MM74HC573 high speed octal D-type latches utilize
advanced silicon-gate P-well CMOS technology. They pos-
sess the high noise immunity and low power consumption
of standard CMOS integrated circuits, as well as the ability
to drive 15 LS-TTL loads. Due to the large output drive
capability and the 3-STATE feature, these devices are ide-
ally suited for interfacing with bus lines in a bus organized
system.
The 74HC logic family is speed, function and pinout com-
patible with the standard 74LS logic family. All inputs are
protected from damage due to static discharge by internal
diode clamps to VCC and ground.
Features
■ Typical propagation delay: 18 ns
When the LATCH ENABLE(LE) input is HIGH, the Q out-
puts will follow the D inputs. When the LATCH ENABLE
goes LOW, data at the D inputs will be retained at the out-
puts until LATCH ENABLE returns HIGH again. When a
HIGH logic level is applied to the OUTPUT CONTROL OC
input, all outputs go to a HIGH impedance state, regardless
■ Wide operating voltage range: 2 to 6 volts
■ Low input current: 1 µA maximum
■ Low quiescent current: 80 µA maximum (74HC Series)
■ Compatible with bus-oriented systems
■ Output drive capability: 15 LS-TTL loads
Ordering Code:
Order Number Package Number
Package Description
MM74HC573WM
MM74HC573SJ
MM74HC573MTC
MM74HC573N
M20B
M20D
MTC20
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Truth Table
Output
Latch
Data
Output
Control
Enable
L
L
H
H
L
H
L
H
L
L
X
X
Q0
Z
H
X
H = HIGH Level
L = LOW Level
Q
0 = Level of output before steady-state input conditions were established.
Z = High Impedance
X = Don't Care
Top View
© 2000 Fairchild Semiconductor Corporation
DS005212
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Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating
Conditions
Supply Voltage (VCC
DC Input Voltage (VIN
DC Output Voltage (VOUT
Clamp Diode Current (IIK, IOK
DC Output Current, per pin (IOUT
DC VCC or GND Current, per pin (ICC
)
−0.5 to +7.0V
−1.5 to VCC +1.5V
−0.5 to VCC +0.5V
±20 mA
Min Max Units
)
Supply Voltage (VCC
DC Input or Output Voltage
(VIN, VOUT
)
2
0
6
V
V
)
VCC
)
)
)
±35 mA
Operating Temperature Range (TA) −40 +85
°C
)
±70 mA
Input Rise or Fall Times
Storage Temperature Range (TSTG
Power Dissipation (PD)
(Note 3)
)
−65°C to +150°C
(tr, tf)
V
CC = 2.0V
1000
500
ns
ns
ns
V
CC = 4.5V
CC = 6.0V
600 mW
500 mW
V
400
S.O. Package only
Note 1: Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Lead Temperature (TL)
(Soldering 10 seconds)
Note 2: Unless otherwise specified all voltages are referenced to ground.
260°C
Note 3: Power Dissipation temperature derating — plastic “N” package: −
12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics (Note 4)
T
A = 25°C
TA = −40 to 85°C TA = −55 to 125°C
VCC
Symbol
Parameter
Conditions
Units
Typ
Guaranteed Limits
VIH
Minimum HIGH Level Input
Voltage
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
1.5
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
V
V
V
3.15
4.2
VIL
Maximum LOW Level Input
Voltage
0.5
0.5
0.5
1.35
1.8
1.35
1.8
1.35
1.8
VOH
Minimum HIGH Level Output
Voltage
V
IN = VIH or VIL
|IOUT| ≤ 20 µA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
VIN = VIH or VIL
|IOUT| ≤ 6.0 mA
|IOUT| ≤ 7.8 mA
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
VOL
Maximum LOW Level Output
Voltage
V
IN = VIH or VIL
|IOUT| ≤ 20 µA
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN = VIH or VIL
|IOUT| ≤ 6.0 mA
|IOUT| ≤ 7.8 mA
4.5V
6.0V
6.0V
0.2
0.2
0.26
0.26
±0.1
0.33
0.33
±1.0
0.4
0.4
V
V
IIN
Maximum Input Current
Maximum 3-STATE Output
Leakage Current
VIN = VCC or GND
±1.0
µA
IOZ
VOUT = VCC or GND
OC = VIH
IN = VCC or GND
OUT = 0 µA
6.0V
±0.5
±5.0
±10
µA
ICC
Maximum Quiescent Supply
Current
V
I
6.0V
OE
8.0
1.5
0.8
0.5
80
1.8
1.0
0.6
160
2.0
1.1
0.7
µA
mA
mA
mA
∆ICC
Quiescent Supply Current
per Input Pin
V
CC = 5.5V
IN = 2.4V
1.0
0.6
0.4
V
LE
or 0.4V (Note 4)
DATA
Note 4: For a power supply of 5V ±10% the worst-case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst-case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst-case leakage cur-
rent (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
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2
AC Electrical Characteristics
VCC = 5V, TA = 25°C, tr = tf = 6 ns
Guaranteed
Symbol Parameter
Conditions
Typ
Units
Limit
20
tPHL, tPLH
tPHL, tPLH
tPZH, tPZL
Maximum Propagation Delay, Data to Q
Maximum Propagation Delay, LE to Q
Maximum Output Enable Time
CL = 45 pF
CL = 45 pF
RL = 1 kΩ
CL = 45 pF
RL = 1 kΩ
CL = 5 pF
16
14
15
ns
ns
ns
22
27
tPHZ, tPLZ
Maximum Output Disable Time
13
23
ns
tS
Minimum Set Up Time, Data to LE
Minimum Hold Time, LE to Data
Minimum Pulse Width, LE or Data
10
2
15
5
ns
ns
ns
tH
tW
10
16
AC Electrical Characteristics
T
A = 25°C
T
A = −40 to 85°C TA = −55 to 125°C
VCC
Symbol
PHL, tPLH
Parameter
Conditions
Units
Typ
45
58
17
21
15
19
46
60
14
21
12
19
Guaranteed Limits
t
Maximum Propagation
Delay Data to Q
C
C
C
C
C
C
C
C
C
C
C
C
R
C
C
C
C
C
C
R
C
L = 50 pF
L = 150 pF
L = 50 pF
L = 150 pF
L = 50 pF
L = 150 pF
L = 50 pF
L = 150 pF
L = 50 pF
L = 150 pF
L = 50 pF
L = 150 pF
L = 1 kΩ
2.0V
2.0V
4.5V
4.5V
6.0V
6.0V
2.0V
2.0V
4.5V
4.5V
6.0V
6.0V
110
150
22
138
188
28
165
225
33
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
30
38
40
19
24
29
26
33
39
tPHL, tPLH
Maximum Propagation
Delay, LE to Q
115
155
23
138
194
29
165
233
35
31
47
47
20
25
30
27
34
41
tPZH, tPZL
Maximum Output Enable
Time
L = 50 pF
L = 150 pF
L = 50 pF
L = 150 pF
L = 50 pF
L = 150 pF
L = 1 kΩ
2.0V
2.0V
4.5V
4.5V
6.0V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
55
67
15
24
14
22
40
13
12
30
10
9
140
180
28
36
24
31
125
25
21
75
15
13
25
5
175
225
35
45
30
39
156
31
27
95
19
16
31
6
210
270
42
54
36
47
188
38
32
110
22
19
38
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
pF
tPHZ, tPLZ
Maximum Output Disable
Time
L = 50 pF
tS
Minimum Set Up Time
Data to LE
tH
Minimum Hold Time
LE to Data
4
5
6
tW
Minimum Pulse Width LE,
or Data
30
9
80
16
14
60
12
10
100
20
18
75
15
13
120
24
20
90
18
15
8
tTLH, tTHL
Maximum Output Rise
and Fall Time, Clock
C
L = 50 pF
25
7
6
CPD
Power Dissipation Capacitance OC = VCC
5
(Note 5) (per latch)
Maximum Input
Capacitance
OC = GND
52
5
CIN
10
10
10
3
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AC Electrical Characteristics (Continued)
T
A = 25°C
TA = −40 to 85°C TA = −55 to 125°C
VCC
Symbol
COUT
Parameter
Conditions
Units
Typ
Guaranteed Limits
Maximum Output
Capacitance
Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC2 f + ICC VCC, and the no load dynamic current consumption,
S = CPD VCC f + ICC
15
20
20
20
pF
I
.
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4
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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8
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