MM74HC595M_NL [FAIRCHILD]
Serial In Parallel Out, HC/UH Series, 8-Bit, Right Direction, True Output, CMOS, PDSO16, 0.150 INCH, LEAD FREE, MS-012AC, SOIC-16;
| 型号： | MM74HC595M_NL |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Serial In Parallel Out, HC/UH Series, 8-Bit, Right Direction, True Output, CMOS, PDSO16, 0.150 INCH, LEAD FREE, MS-012AC, SOIC-16 移位寄存器 锁存器 |
| 文件： | 总10页 (文件大小：95K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 1983
Revised February 1999
MM74HC595
8-Bit Shift Registers with Output Latches
The 74HC logic family is speed, function, and pin-out com-
patible with the standard 74LS logic family. All inputs are
protected from damage due to static discharge by internal
diode clamps to VCC and ground.
General Description
The MM74HC595 high speed shift register utilizes
advanced silicon-gate CMOS technology. This device pos-
sesses the high noise immunity and low power consump-
tion of standard CMOS integrated circuits, as well as the
ability to drive 15 LS-TTL loads.
Features
■ Low quiescent current: 80 µA maximum (74HC Series)
■ Low input current: 1 µA maximum
■ 8-bit serial-in, parallel-out shift register with storage
■ Wide operating voltage range: 2V–6V
■ Cascadable
This device contains an 8-bit serial-in, parallel-out shift reg-
ister that feeds an 8-bit D-type storage register. The stor-
age register has 8 3-STATE outputs. Separate clocks are
provided for both the shift register and the storage register.
The shift register has a direct-overriding clear, serial input,
and serial output (standard) pins for cascading. Both the
shift register and storage register use positive-edge trig-
gered clocks. If both clocks are connected together, the
shift register state will always be one clock pulse ahead of
the storage register.
■ Shift register has direct clear
■ Guaranteed shift frequency: DC to 30 MHz
Ordering Code:
Order Number Package Number
Package Description
MM74HC595M
MM74HC595WM
MM74HC595SJ
MM74HC595MTC
MM74HC595N
M16A
M16B
M16D
MTC16
N16E
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Truth Table
Pin Assignments for DIP, SOIC, SOP and TSSOP
RCK SCK SCLR
G
H
L
Function
X
X
X
X
X
L
QA thru QH = 3-STATE
Shift Register cleared
Q
H = 0
Shift Register clocked
N = Qn-1, Q0 = SER
X
↑
H
H
L
L
Q
↑
X
Contents of Shift
Register transferred
to output latches
Top View
© 1999 Fairchild Semiconductor Corporation
DS005342.prf
www.fairchildsemi.com
Logic Diagram
(positive logic)
www.fairchildsemi.com
2
Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating
Conditions
Supply Voltage (VCC
DC Input Voltage (VIN
DC Output Voltage (VOUT
Clamp Diode Current (IIK, IOK
)
−0.5 to +7.0V
−1.5 to VCC +1.5V
−0.5 to VCC +0.5V
±20 mA
Min
Max
Units
)
Supply Voltage (VCC
DC Input or Output Voltage
(VIN, VOUT
)
2
6
V
)
)
)
0
VCC
V
DC Output Current, per pin (IOUT
DC VCC or GND Current,
)
±35 mA
Operating Temperature Range (TA) −40
Input Rise or Fall Times
+85
°C
per pin (ICC
)
±70 mA
(tr, tf) VCC = 2.0V
1000
500
ns
ns
ns
Storage Temperature Range (TSTG
Power Dissipation (PD)
(Note 3)
)
−65°C to +150°C
V
V
CC = 4.5V
CC = 6.0V
400
600 mW
500 mW
Note 1: Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
S.O. Package only
Note 2: Unless otherwise specified all voltages are referenced to ground.
Lead Temperature (TL)
(Soldering 10 seconds)
Note 3: Power Dissipation temperature derating — plastic “N” package: −
12 mW/°C from 65°C to 85°C.
260°C
DC Electrical Characteristics (Note 4)
T
= 25°C
T = −40 to 85°C T = −55 to 125°C
A A
A
V
Symbol
Parameter
Conditions
Units
CC
Typ
Guaranteed Limits
V
Minimum HIGH Level
Input Voltage
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
1.5
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
V
V
V
IH
3.15
4.2
V
V
Maximum LOW Level
Input Voltage
0.5
0.5
0.5
IL
1.35
1.8
1.35
1.8
1.35
1.8
Minimum HIGH Level
Output Voltage
V
= V or V
IH IL
OH
IN
|I
| ≤ 20 µA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
OUT
Q
Q
V
= V or V
IH IL
H
IN
|I
|I
| ≤ 4.0 mA
| ≤ 5.2 mA
4.5V
6.0V
4.2
5.2
3.98
5.48
3.84
5.34
3.7
5.2
V
V
OUT
OUT
thru Q
V
= V or V
IH IL
A
H
IN
|I
|I
| ≤ 6.0 mA
| ≤ 7.8 mA
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
OUT
OUT
V
Maximum LOW Level
Output Voltage
V
= V or V
IH IL
OL
IN
|I
| ≤ 20 µA
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
OUT
Q
Q
V
= V or V
IH IL
H
IN
|I
|I
| ≤ 4 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
OUT
OUT
| ≤ 5.2 mA
thru Q
V
= V or V
IH IL
A
H
IN
|I
|I
| ≤ 6.0 mA
| ≤ 7.8 mA
4.5V
6.0V
6.0V
0.2
0.2
0.26
0.26
±0.1
0.33
0.33
±1.0
0.4
0.4
V
V
OUT
OUT
I
Maximum Input
Current
V
= V or GND
±1.0
µA
IN
IN
CC
I
Maximum 3-STATE
Output Leakage
V
= V or GND
6.0V
6.0V
±0.5
±5.0
±10
µA
µA
OZ
OUT
CC
G = V
IH
I
Maximum Quiescent
Supply Current
V
= V or GND
8.0
80
160
CC
IN
CC
I
= 0 µA
OUT
Note 4: For a power supply of 5V ±10% the worst case output voltages (V , and V ) occur for HC at 4.5V. Thus the 4.5V values should be used when
OH
OL
designing with this supply. Worst case V and V occur at V = 5.5V and 4.5V respectively. (The V value at 5.5V is 3.85V.) The worst case leakage cur-
IH
IL
CC
IH
rent (I , I , and I ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
IN CC
OZ
3
www.fairchildsemi.com
AC Electrical Characteristics
V
CC = 5V, TA = 25°C, t = t = 6 ns
r f
Guaranteed
Limit
Symbol
Parameter
Conditions
Typ
Units
f
t
t
t
Maximum Operating
Frequency of SCK
50
30
MHz
MAX
, t
Maximum Propagation
C
C
= 45 pF
= 45 pF
12
18
20
30
ns
ns
PHL PLH
L
Delay, SCK to Q
H’
, t
Maximum Propagation
Delay, RCK to Q thru Q
PHL PLH
L
A
H
, t
Maximum Output Enable
R
C
= 1 kΩ
PZH PZL
L
= 45 pF
17
15
28
25
ns
ns
Time from G to Q thru Q
A
L
H
t
, t
Maximum Output Disable
R
C
= kΩ
PHZ PLZ
L
= 5 pF
Time from G to Q thru Q
A
L
H
t
t
Minimum Setup Time
from SER to SCK
20
20
ns
ns
S
S
Minimum Setup Time
from SCLR to SCK
Minimum Setup Time
from SCK to RCK
(Note 5)
t
40
ns
S
t
t
Minimum Hold Time
from SER to SCK
Minimum Pulse Width
of SCK or RCK
0
ns
ns
H
16
W
Note 5: This setup time ensures the register will see stable data from the shift-register outputs. The clocks may be connected together in which case the stor-
age register state will be one clock pulse behind the shift register.
AC Electrical Characteristics
V
CC = 2.0−6.0V, C = 50 pF, t = t = 6 ns (unless otherwise specified)
L
r
f
T
= 25°C
T = −40 to 85°C T = −55 to 125°C
A A
A
V
Symbol
Parameter
Conditions
= 50 pF
Units
CC
Typ
10
45
50
58
83
14
17
10
14
70
105
21
28
18
26
Guaranteed Limits
f
t
Maximum Operating
Frequency
C
2.0V
4.5V
6.0V
2.0V
2.0V
4.5V
4.5V
6.0V
6.0V
2.0V
2.0V
4.5V
4.5V
6.0V
6.0V
2.0V
4.5V
6
4.8
24
4.0
20
MHz
MHz
MHz
ns
MAX
L
30
35
28
24
, t
Maximum Propagation
C
C
C
C
C
C
C
C
C
C
C
C
= 50 pF
= 150 pF
= 50 pF
= 150 pF
= 50 pF
= 150 pF
= 50 pF
= 150 pF
= 50 pF
= 150 pF
= 50 pF
= 150 pF
210
294
42
265
367
53
315
441
63
PHL PLH
L
L
L
L
L
L
L
L
L
L
L
L
Delay from SCK to Q
ns
H
ns
58
74
88
ns
36
45
54
ns
50
63
76
ns
t
t
, t
Maximum Propagation
175
245
35
220
306
44
265
368
53
ns
PHL PLH
Delay from RCK to Q thru Q
A
ns
H
ns
49
61
74
ns
30
37
45
ns
42
53
63
ns
, t
Maximum Propagation
175
35
221
44
261
52
ns
PHL PLH
ns
Delay from SCLR to Q
H
6.0V
30
37
44
ns
www.fairchildsemi.com
4
AC Electrical Characteristics (Continued)
T
= 25°C
T = −40 to 85°C T = −55 to 125°C
A A
A
V
Symbol
, t
Parameter
Conditions
= 1 kΩ
Units
CC
Typ
Guaranteed Limits
t
Maximum Output Enable
from G to Q thru Q
R
C
PZH PZL
L
= 50 pF
2.0V
75
175
220
265
ns
L
A
H
C
C
C
C
C
R
C
= 150 pF
= 50 pF
= 150 pF
= 50 pF
= 150 pF
= 1 kΩ
2.0V
4.5V
4.5V
6.0V
6.0V
2.0V
4.5V
100
15
20
13
17
75
15
245
35
306
44
368
53
ns
ns
ns
ns
ns
ns
ns
L
L
L
L
L
L
L
49
61
74
30
37
45
42
53
63
t
, t
Maximum Output Disable
175
35
220
44
265
53
PHZ PLZ
= 50 pF
Time from G to Q thru Q
A
H
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
13
30
100
20
37
125
25
45
150
30
ns
ns
ns
ns
ns
ns
t
t
Minimum Setup Time
from SER to SCK
S
R
17
21
25
Minimum Removal Time
from SCLR to SCK
50
63
75
10
13
15
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
9
100
20
17
5
11
125
25
21
5
13
150
30
26
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
Minimum Setup Time
from SCK to RCK
S
Minimum Hold Time
SER to SCK
H
W
5
5
5
5
5
5
Minimum Pulse Width
of SCK or SCLR
30
9
80
16
100
20
120
24
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
8
14
1000
500
400
60
18
1000
500
400
75
22
1000
500
400
90
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
t , t
Maximum Input Rise and
Fall Time, Clock
r
f
t
, t
Maximum Output
Rise and Fall Time
25
7
THL TLH
12
15
18
Q –Q
6
10
13
15
A
H
t
, t
Maximum Output
Rise & Fall Time
75
95
110
22
THL TLH
15
19
Q
13
16
19
H
C
Power Dissipation
90
G = V
PD
CC
Capacitance, Outputs
150
pF
G = GND
Enabled (Note 6)
Maximum Input
Capacitance
C
C
5
10
20
10
20
10
20
pF
pF
IN
Maximum Output
Capacitance
15
OUT
2
Note 6: C determines the no load dynamic power consumption, P = C
V
f + I
V
, and the no load dynamic current consumption,
PD
D
PD CC
CC CC
I
= C
V
f + I
.
CC
S
PD CC
5
www.fairchildsemi.com
Timing Diagram
www.fairchildsemi.com
6
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
Package Number M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
Package Number M16B
7
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
www.fairchildsemi.com
8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
9
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual--Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N16E
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
相关型号：
MM74HC595N
HC/UH SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP16, 0.300 INCH, ROHS COMPLIANT, PLASTIC, MS-001BB, DIP-16
ROCHESTER
MM74HC595N_NL
Serial In Parallel Out, HC/UH Series, 8-Bit, Right Direction, True Output, CMOS, PDIP16, 0.300 INCH, LEAD FREE, PLASTIC, MS-001BB, DIP-16
FAIRCHILD
MM74HC595WMX
Serial In Parallel Out, HC/UH Series, 8-Bit, Right Direction, True Output, CMOS, PDSO16, 0.300 INCH, MS-013, SOIC-16
FAIRCHILD
MM74HC597J
HC/UH SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP16, CERDIP-16
TI
©2020 ICPDF网 联系我们和版权申明