NC7SZ18P6X_11 [FAIRCHILD]
TinyLogic® UHS 1-of-2 Non-Inverting De-multiplexer with 3-STATE Deselected Output; TinyLogic® UHS 1 - 2非反相解复用器与3-STATE取消选择输出
| 型号： | NC7SZ18P6X_11 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | TinyLogic® UHS 1-of-2 Non-Inverting De-multiplexer with 3-STATE Deselected Output |
| 文件： | 总10页 (文件大小：547K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 2011
NC7SZ18
TinyLogic® UHS 1-of-2 Non-Inverting De-multiplexer
with 3-STATE Deselected Output
Features
Description
The NC7SZ18 is a 1-of-2 non-inverting demultiplexer.
The device will buffer the data on the A pin and pass to
either output Y0 or Y1 dependent on whether state of the
select pin (S) is LOW or HIGH respectively. The
deselected output will be placed into a high impedance
state. The device is fabricated with advanced CMOS
technology to achieve ultra high speed with high output
drive while maintaining low static power dissipation over
a broad VCC operating range. The device is specified to
operate over the 1.65V to 5.5V VCC operating range.
The inputs and outputs are high impedance when VCC is
0V. Inputs tolerate voltages up to 5.5V independent of
.
Ultra-High Speed: tPD 2.5ns Typical at 5V
VCC
.
.
.
.
High Impedance Output when Deselected
Broad VCC Operating Range: 1.65V to 5.50V
Power Down High Impedance Inputs/Outputs
Over-Voltage Tolerance Inputs Facilitate 5V to 3V
Translation
.
.
Proprietary Noise/EMI Reduction Circuitry
Ultra-Small MicroPak™ Packages
VCC operating range.
Ordering Information
Part Number
NC7SZ18P6X
NC7SZ18L6X
NC7SZ18FHX
Top Mark
Package
Packing Method
Z18
D5
6-Lead SC70, EIAJ SC88 1.25mm Wide
6-Lead MicroPak™, 1.00mm Wide
3000 Units on Tape & Reel
5000 Units on Tape & Reel
D5
6-Lead, MicroPak2™, 1x1mm Body, .35mm Pitch 5000 Units on Tape & Reel
TinyLogic® is a registered trademark of Fairchild Semiconductor Corporation.
MicroPak™ is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
NC7SZ18 • Rev. 1.0.2
www.fairchildsemi.com
Pin Configurations
Figure 1. SC70 (Top View)
Figure 2. MicroPak™ (Top Through View)
Figure 3. Pin 1 Orientation
Notes:
1. AAA represents product code top mark (see Ordering Information).
2. Orientation of top mark determines pin one location.
3. Reading the top mark left to right, pin one is the lower left pin.
Pin Definitions
Pin # SC70
Pin # MicroPak™
Name
S
Description
1
2
3
4
5
6
1
2
3
4
5
6
Data Input
Ground
GND
A
Demultiplexer Data
Output
Y1
VCC
Y0
Supply Voltage
Output
Function Table
Inputs
Output
S
A
Y0
L
Y1
Z
L
L
H
L
L
H
Z
Z
H
H
L
H
Z
H
H = HIGH Logic Level
L = LOW Logic Level
X = 3-STATE
© 1999 Fairchild Semiconductor Corporation
NC7SZ18 • Rev. 1.0.2
www.fairchildsemi.com
2
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
VCC
Parameter
Min.
-0.5
-0.5
-0.5
Max.
7.0
Unit
V
Supply Voltage
VIN
DC Input Voltage
7.0
V
VOUT
IIK
DC Output Voltage
7.0
V
DC Input Diode Current
DC Output Diode Current
DC Output Current
-50
mA
mA
mA
mA
°C
°C
°C
VIN -0.5V
VIN -0.5V
IOK
-50
IOUT
±50
ICC or IGND
TSTG
TJ
DC VCC or Ground Current
Storage Temperature Range
Junction Temperature Under Bias
±100
+150
+150
+260
180
-65
TL
Junction Lead Temperature (Soldering, 10 Seconds)
SC70-6
PD
Power Dissipation at +85°C
MicroPak™-6
MicroPak2™-6
130
mW
V
120
Human Body Model, JEDEC:JESD22-A114
Charge Device Model, JEDEC:JESD22-C101
4000
2000
ESD
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Supply Voltage Operating
Supply Voltage Data Retention
Input Voltage
Conditions
Min.
1.65
1.5
0
Max.
5.50
5.5
Unit
VCC
V
VIN
5.5
V
V
VOUT
Output Voltage
0
VCC
V
CC at 1.8V, ±0.15V,
0
20
2.5V ± 0.2V
tr, tf
Input Rise and Fall Times
ns/V
VCC at 3.3V ± 0.3V
VCC at 5.0V ± 0.5V
0
0
10
5
TA
Operating Temperature
Thermal Resistance
-40
+85
425
500
560
°C
SC70-6
MicroPak™-6
MicroPak2™-6
°C/W
JA
© 1999 Fairchild Semiconductor Corporation
NC7SZ18 • Rev. 1.0.2
www.fairchildsemi.com
3
DC Electrical Characteristics
TA=-40 to
+85°C
TA=+25°C
Symbol
Parameter
VCC
Condition
Unit
Min. Typ. Max.
0.75VCC
Min.
Max.
1.65 to 1.95
2.30 to 5.50
1.65 to 1.95
2.30 to 5.50
1.65
0.75VCC
0.70VCC
HIGH Level Input
Voltage
VIH
VIL
V
V
0.70VCC
0.25VCC
0.25VCC
0.30VCC
LOW Level Input
Voltage
0.30VCC
1.55
2.20
2.90
4.40
1.29
1.90
2.40
2.30
3.80
1.65
2.30
3.00
4.50
1.52
2.15
2.80
3.68
4.20
0.00
0.00
0.00
0.00
0.08
0.10
0.15
0.22
0.22
1.55
2.20
2.90
4.40
1.29
1.90
2.40
2.30
3.80
2.30
VIN=VIH,
OH=-100µA
I
3.00
4.50
HIGH Level
Output Voltage
VOH
1.65
IOH=-4mA
IOH=-8mA
IOH=-16mA
IOH=-24mA
IOH=-32mA
V
2.30
3.00
3.00
4.50
1.65
0.10
0.10
0.10
0.10
0.24
0.30
0.40
0.55
0.55
0.10
0.10
0.10
0.10
0.24
0.30
0.40
0.55
0.55
2.30
VIN=VIL
I
OL=100µA
3.00
4.50
LOW Level
Output Voltage
VOL
1.65
IOL=4mA
IOL=8mA
IOL=16mA
IOL=24mA
IOL=32mA
V
2.30
3.00
3.00
4.50
Input Leakage
Current
IIN
IOZ
IOFF
ICC
0 to 5.5
1.65 to 5.50
0
VIN=5.5V, GND
±0.1
±0.5
1
±1.0
±5.0
10
µA
µA
µA
µA
VIN=VIL or VOH
0<VOUT 5.5V
3-STATE Output
Leakage
Power Off
Leakage Current
VIN or VOUT=5.5V
Quiescent
Supply Current
1.65 to 5.50 VIN=5.5V, GND
1
10
© 1999 Fairchild Semiconductor Corporation
NC7SZ18 • Rev. 1.0.2
www.fairchildsemi.com
4
AC Electrical Characteristics
TA=-40 to
+85°C
TA=+25°C
Symbol
Parameter
VCC
Condition
Unit Figure
Min. Typ. Max. Min.
Max.
10.5
6.0
1.80 ± 0.15
2.50 ± 0.20
3.30 ± 0.30
5.00 ± 0.50
2.0
1.0
0.8
0.5
1.2
0.8
6.3
3.6
2.7
2.0
3.4
10.1
5.7
4.0
3.1
4.9
2.0
1.0
0.8
0.5
1.2
0.8
CL=15pF,
RD=1M
V1=OPEN
4.3
Propagation Delay
A to Y0 or Y1
Figure 4
ns
tPLH, tPHL
3.3
Figure 6
3.30 ± 0.30 CL=50pF,
5.4
RD=500
5.00 ± 0.50
V1=OPEN
2.5
3.9
4.2
1.80 ± 0.15 CL=50pF,
3.0
1.8
1.2
6.9
4.2
3.2
12.0
6.8
3.0
1.8
1.2
12.5
7.3
RD,RU=500
V1=GND for
2.50 ± 0.20
Output Enable
Time
Figure 4
ns
3.30 ± 0.30
5.0
5.5
tPZH
Figure 6
V1=VIN for
tPZL
VIN=2 x VCC
5.00 ± 0.50
0.8
2.5
4.0
0.8
4.3
tPZL, tPHZ
1.80 ± 0.15 CL=50pF,
2.5
1.5
0.8
6.0
4.0
2.9
10.0
6.8
2.5
1.5
0.8
10.5
7.1
RD,RU=500
V1=GND for
tPHZ
2.50 ± 0.20
3.30 ± 0.30
Output Disable
Time
Figure 4
ns
4.9
5.3
Figure 6
V1=VIN for
tPLZ
VIN=2 x VCC
5.00 ± 0.50
0.3
1.8
3.5
0.3
3.7
CIN
Input Capacitance
0
0
2.5
4.0
pF
pF
Output
Capacitance
COUT
3.30
5.00
16.0
19.5
Power Dissipation
Capacitance(4)
CPD
pF Figure 5
Note:
4. CPD is defined as the value of the internal equivalent capacitance which is derived from dynamic operating
current consumption (ICCD) at no output loading and operating at 50% duty cycle. CPD is related to ICCD dynamic
operating current by the expression: ICCD=(CPD)(VCC)(fIN)+(ICCstatic).
© 1999 Fairchild Semiconductor Corporation
NC7SZ18 • Rev. 1.0.2
www.fairchildsemi.com
5
AC Loadings and Waveforms
Notes:
5. CL includes load and stray capacitance.
6. Input PRR = 1.0MHz, tW = 500ns.
Figure 5. ICCD Test Circuit
Figure 4. AC Test Circuit
Figure 6. AC Waveforms
© 1999 Fairchild Semiconductor Corporation
NC7SZ18 • Rev. 1.0.2
www.fairchildsemi.com
6
Physical Dimensions
SYMM
C
L
±0.20
A
2.00
0.65
0.50 MIN
6
4
B
PIN ONE
±0.10
1.25
1.90
1
3
0.30
0.15
(0.25)
0.40 MIN
0.10
A B
1.30
0.65
1.30
LAND PATTERN RECOMMENDATION
SEE DETAIL A
1.00
0.80
1.10
0.80
0.10 C
0.10
0.00
C
2.10±0.30
SEATING
PLANE
NOTES: UNLESS OTHERWISE SPECIFIED
GAGE
PLANE
A) THIS PACKAGE CONFORMS TO EIAJ
SC-88, 1996.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE BURRS
OR MOLD FLASH.
(R0.10)
0.25
0.10
D) DRAWING FILENAME: MKT-MAA06AREV6
0.20
30°
0°
0.46
0.26
DETAIL A
SCALE: 60X
Figure 7. 6-Lead, SC70, EIAJ SC88, 1.25mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
Tape and Reel Specification
Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:
http://www.fairchildsemi.com/products/analog/pdf/sc70-6_tr.pdf.
Package Designator
Tape Section
Leader (Start End)
Carrier
Cavity Number
125 (Typical)
3000
Cavity Status Cover Type Status
Empty
Filled
Sealed
Sealed
Sealed
P6X
Trailer (Hub End)
75 (Typical)
Empty
© 1999 Fairchild Semiconductor Corporation
NC7SZ18 • Rev. 1.0.2
www.fairchildsemi.com
7
Physical Dimensions
2X
0.05 C
1.45
B
(1)
2X
0.05 C
(0.49)
5X
(0.254)
1.00
(0.75)
(0.52)
1X
TOP VIEW
A
PIN 1 IDENTIFIER
5
0.55MAX
(0.30)
6X
PIN 1
0.05 C
0.05
0.00
RECOMMENED
LAND PATTERN
0.05 C
C
0.45
0.35
0.10
6X
0.00
0.25
6X
0.15
1.0
DETAIL A
0.10
C B A
0.40
0.30
0.05
C
0.35
0.25
5X
5X
0.40
0.30
DETAIL A
PIN 1 TERMINAL
0.075 X 45
CHAMFER
0.5
BOTTOM VIEW
(0.05)
6X
(0.13)
4X
Notes:
1. CONFORMS TO JEDEC STANDARD M0-252 VARIATION UAAD
2. DIMENSIONS ARE IN MILLIMETERS
3. DRAWING CONFORMS TO ASME Y14.5M-1994
4. FILENAME AND REVISION: MAC06AREV4
5. PIN ONE IDENTIFIER IS 2X LENGTH OF ANY
OTHER LINE IN THE MARK CODE LAYOUT.
Figure 8. 6-Lead, MicroPak™, 1.0mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
Tape and Reel Specification
Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:
http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf.
Package Designator
Tape Section
Leader (Start End)
Carrier
Cavity Number
125 (Typical)
5000
Cavity Status Cover Type Status
Empty
Filled
Sealed
Sealed
Sealed
L6X
Trailer (Hub End)
75 (Typical)
Empty
© 1999 Fairchild Semiconductor Corporation
NC7SZ18 • Rev. 1.0.2
www.fairchildsemi.com
8
Physical Dimensions
0.89
0.35
0.05 C
2X
1.00
B
A
5X 0.40
1X 0.45
PIN 1
0.66
MIN 250uM
1.00
6X 0.19
0.05 C
TOP VIEW
RECOMMENDED LAND PATTERN
FOR SPACE CONSTRAINED PCB
2X
0.90
0.35
0.05 C
0.55MAX
C
5X 0.52
SIDE VIEW
0.73
0.57
1X
(0.08) 4X
DETAIL A
0.09
0.19
6X
1
2
3
0.20 6X
ALTERNATIVE LAND PATTERN
FOR UNIVERSAL APPLICATION
(0.05) 6X
0.35
5X
0.25
0.60
6
5
4
0.10
.05 C
C B A
0.40
0.30
0.35
(0.08)
4X
BOTTOM VIEW
NOTES:
A. COMPLIES TO JEDEC MO-252 STANDARD
B. DIMENSIONS ARE IN MILLIMETERS.
0.075X45°
CHAMFER
C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994
D. LANDPATTERN RECOMMENDATION IS BASED ON FSC
DESIGN.
DETAIL A
PIN 1 LEAD SCALE: 2X
E. DRAWING FILENAME AND REVISION: MGF06AREV3
Figure 9.
6-Lead, MicroPak2™, 1x1mm Body, .35mm Pitch
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
Tape and Reel Specification
Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:
http://www.fairchildsemi.com/packaging/MicroPAK2_6L_tr.pdf.
Package Designator
Tape Section
Leader (Start End)
Carrier
Cavity Number
125 (Typical)
5000
Cavity Status Cover Type Status
Empty
Filled
Sealed
Sealed
Sealed
FHX
Trailer (Hub End)
75 (Typical)
Empty
© 1999 Fairchild Semiconductor Corporation
NC7SZ18 • Rev. 1.0.2
www.fairchildsemi.com
9
© 1999 Fairchild Semiconductor Corporation
NC7SZ18 • Rev. 1.0.2
www.fairchildsemi.com
10
相关型号：
NC7SZ18P6X_NL
Decoder/Driver, LVC/LCX/Z Series, True Output, CMOS, PDSO6, 1.25 MM, LEAD FREE, EIAJ, SC-88, SC-70, 6 PIN
FAIRCHILD
NC7SZ18_04
TinyLogic UHS 1-of-2 Non-Inverting Demultiplexer with 3-STATE Deselected Output
FAIRCHILD
NC7SZ18_11
TinyLogic® UHS 1-of-2 Non-Inverting De-multiplexer with 3-STATE Deselected Output
FAIRCHILD
©2020 ICPDF网 联系我们和版权申明