NC7SZ374P6_NL [FAIRCHILD]
Bus Driver, LVC/LCX/Z Series, 1-Func, 1-Bit, True Output, CMOS, PDSO6, 1.25 MM, LEAD FREE, EIAJ, SC-88, SC-70, 6 PIN;
| 型号： | NC7SZ374P6_NL |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Bus Driver, LVC/LCX/Z Series, 1-Func, 1-Bit, True Output, CMOS, PDSO6, 1.25 MM, LEAD FREE, EIAJ, SC-88, SC-70, 6 PIN 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总9页 (文件大小：148K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
May 1998
Revised October 2004
NC7SZ374
TinyLogic UHS D-Type Flip-Flop with 3-STATE Output
General Description
Features
The NC7SZ374 is a single positive edge-triggered D-type
CMOS Flip-Flop with 3-STATE output from Fairchild’s Ultra
High Speed Series of TinyLogic in the space saving
SC70 6-lead package. The device is fabricated with
advanced CMOS technology to achieve ultra high speed
with high output drive while maintaining low static power
dissipation over a very broad VCC operating range. The
■ Space saving SC70 6-lead package
■ Ultra small MicroPak leadless package
■ Ultra High Speed; tPD 2.6 ns Typ into 50 pF at 5V VCC
■ High Output Drive; ±24 mA at 3V VCC
■ Broad VCC Operating Range; 1.65V to 5.5V
■ Matches the performance of LCX when operated at
3.3V VCC
device is specified to operate over the 1.65V to 5.5V VCC
range. The inputs and output are high impedance when
VCC is 0V. Inputs tolerate voltages up to 7V independent of
■ Power down high impedance inputs/output
■ Overvoltage tolerant inputs facilitate 5V - 3V translation
■ Patented noise/EMI reduction circuitry implemented
VCC operating voltage. This single flip-flop will store the
state of the D input that meets the setup and hold time
requirements on the LOW-to-HIGH Clock (CP) transition.
The output tolerates voltages above VCC in the 3-STATE
condition.
Ordering Code:
Order
Number
Package
Number
MAA06A
MAC06A
Product Code
Top Mark
Z74
Package Description
Supplied As
NC7SZ374P6X
NC7SZ374L6X
6-Lead SC70, EIAJ SC88, 1.25mm Wide
6-Lead MicroPak, 1.0mm Wide
3k Units on Tape and Reel
5k Units on Tape and Reel
C9
TinyLogic is a registered trademark of Fairchild Semiconductor Corporation.
MicroPak is a trademark of Fairchild Semiconductor Corporation.
© 2004 Fairchild Semiconductor Corporation
DS500156
www.fairchildsemi.com
Logic Symbol
Connection Diagrams
IEEE/IEC
Pin Assignments for SC70
Pin Descriptions
Pin Names
Description
Data Input
D
(Top View)
CP
Clock Pulse Input
Pin One Orientation Diagram
OE
Q
Output Enable Input
Flip-Flop Output
Function Table
AAA represents Product Code Top Mark - see ordering code
Inputs
Output
Note: Orientation of Top Mark determines Pin One location. Read the top
product code mark left to right, Pin One is the lower left pin (see diagram).
CP
D
L
OE
L
Q
L
Pad Assignment for MicroPak
H
X
X
L
H
L
Qn
X
H
Z
H = HIGH Logic Level
L = LOW Logic Level
Z = High Impedance
n = No change in data
X = Immaterial
Q
(Top Thru View)
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions (Note 2)
Supply Voltage (VCC
DC Input Voltage (VIN
DC Output Voltage (VOUT
DC Input Diode Current (IIK
IN < 0V
DC Output Diode Current (IOK
OUT < 0V
DC Output (IOUT) Source/Sink Current
DC VCC/GND Current (ICC/IGND
Storage Temperature Range (TSTG
)
−0.5V to +7.0V
−0.5V to +7.0V
−0.5V to +7.0V
)
Power Supply
)
Operating (VCC
Data Retention
)
1.65V to 5.5V
1.5V to 5.5V
0V to 5.5V
)
V
−50 mA
Input Voltage (VIN)
)
Output Voltage (VOUT
)
V
−50 mA
± 50 mA
Active State
0V to VCC
0V to 5.5V
3-STATE
)
± 50 mA
Input Rise and Fall Time (tr, tf)
)
−65°C to +150°C
150°C
V
V
V
CC = 1.8V, 2.5V ± 0.2V
CC = 3.3V ± 0.3V
0 to 20 ns/V
0 to 10 ns/V
0 to 5 ns/V
Junction Temperature under Bias (TJ)
Junction Lead Temperature (TL)
(Soldering, 10 seconds)
CC = 5.5V ± 0.5V
260°C
Operating Temperature (TA)
Thermal Resistance (θJA
−40°C to +85°C
350° C/W
Power Dissipation (PD) @ +85°C
180 mW
)
Note 1: Absolute Maximum Ratings: are those values beyond which the
safety of the device cannot be guaranteed. The device should not be oper-
ated at these limits. The parametric values defined in the Electrical Charac-
teristics tables are not guaranteed at the absolute maximum ratings. The
“Recommended Operating Conditions” table will define the conditions for
actual device operation.
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
VCC
T
A = +25°C
TA = −40°C to +85°C
Symbol
Parameter
Units
Conditions
(V)
Min Typ
Max
Min
Max
VIH
HIGH Level Control
Input Voltage
1.65 to 1.95 0.75 VCC
2.3 to 5.5 0.75 VCC
1.65 to 1.95
0.75 VCC
0.7 VCC
V
V
VIL
LOW Level Control
Input Voltage
0.25 VCC
0.3 VCC
0.25 VCC
0.3 VCC
2.3 to 5.5
VOH
HIGH Level Control
Output Voltage
1.65
1.8
1.55
1.7
2.2
2.9
4.4
1.24
1.9
2.4
2.3
3.8
1.65
1.55
1.7
2.2
2.9
4.4
1.29
1.9
2.4
2.3
3.8
1.8
2.3
2.3
I
OH = −100 µA
3.0
3.0
4.5
4.5
V
VIN = VIH
1.65
2.3
1.52
2.15
2.8
IOH
IOH
=
=
−4 mA
−8 mA
3.0
I
I
I
OH = −16 mA
3.0
2.68
4.2
OH = −24 mA
OH = −32 mA
4.5
VOL
LOW Level Control
Output Voltage
1.65
1.8
0.0
0.1
0.1
0.1
0.1
0.0
2.3
0.0
0.1
0.1
I
OL = 100 µA
3.0
0.0
0.1
0.1
4.5
0.0
0.1
0.1
V
VIN = VIH
1.65
2.3
0.08
0.10
0.15
0.22
0.22
0.24
0.3
0.24
0.3
IOL
IOL
=
=
4 mA
8 mA
3.0
0.4
0.4
I
I
I
OL = 16 mA
3.0
0.55
0.55
±0.1
±0.5
0.55
0.55
±1.0
±5.0
OL = 24 mA
OL = 32 mA
4.5
IIN
Input Leakage Current
0 to 5.5
1.65 to 5.5
µA 0 ≤ VIN ≤ 5.5V
µA IN = VIL or VIH
0 ≤ VOUT ≤ 5.5V
µA VIN or VOUT = 5.5V
IOZ
3-STATE Output Leakage
V
IOFF
ICC
Power Off Leakage Current
Quiescent Supply Current
0.0
1.0
1.0
10
1.65 to 5.5
10.0
µA
VIN = 5.5V, GND
3
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AC Electrical Characteristics
T
A = +25°C
T
A = −40°C to +85°C
Figure
VCC
(V)
Symbol
Parameter
Units
Conditions
Min
Typ
Max
Min
100
100
125
150
175
2.5
2.5
2.0
1.4
1.0
1.6
1.4
2.0
2.0
1.8
1.4
1.0
2.0
2.0
1.8
1.4
1.0
2.5
2.0
1.5
1.5
1.5
1.5
3.0
2.8
2.5
Max
Number
fMAX
Maximum Clock
Frequency
1.65
1.8
Figures
1, 3
2.5 ± 0.2
3.3 ± 0.3
5.0 ± 0.5
1.65
MHz
C
L = 50 pF
RD = 500Ω, S1 = Open
2.5
2.5
2.0
1.5
1.0
2.0
1.5
2.0
2.0
2.0
1.5
1.0
2.0
2.0
2.0
1.5
1.0
9.7
6.5
3.8
2.8
2.2
3.4
2.6
9.0
6.0
3.7
2.8
2.2
7.7
5.1
3.5
2.8
2.3
1.50
10.0
6.5
4.5
3.5
5.5
4.0
13.5
9.0
6.0
5.0
3.7
12.0
8.0
6.0
4.5
3.7
16.5
11.0
7.0
5.0
3.8
6.2
4.7
14.3
9.5
6.6
5.3
3.9
13.0
8.5
6.3
4.7
3.9
tPLH
tPHL
Propagation Delay
CP to Q
1.8
Figures
1, 3
2.5 ± 0.2
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
1.65
C
R
L = 15 pF
D = 1 MΩ
ns
S1 = Open
C
R
L = 50 pF
Figures
1, 3
D = 500 Ω, S1 = Open
tPZL
tPZH
Output Enable Time
1.8
C
L = 50 pF, VI = 2x VCC
Figures
1, 4
2.5 ± 0.2
3.3 ± 0.3
5.0 ± 0.5
1.65
ns
ns
RU, RD = 500 Ω
S1 = GND for tPZH
S1 = VI for tPZL
tPLZ
tPHZ
Output Disable Time
1.8
CL = 50 pF, VI = 2x VCC
Figures
1, 4
2.5 ± 0.2
3.3 ± 0.3
5.0 ± 0.5
2.5 ± 0.2
3.3 ± 0.3
5.0 ± 0.5
2.5 ± 0.2
3.3 ± 0.3
5.0 ± 0.5
2.5 ± 0.2
3.3 ± 0.3
5.0 ± 0.5
RU, RD = 500 Ω
S1 = GND for tPHZ
S1 = VI for tPLZ
tS
Setup Time,
CP to D
CL = 50 pF
Figures
1, 5
ns
ns
ns
R
D = 500 Ω, S1 = Open
tH
Hold Time,
CP to D
CL = 50 pF
Figures
1, 5
D = 500 Ω, S1 = Open
tW
Pulse Width, CP
CL = 50 pF
Figures
1, 5
R
D = 500 Ω, S1 = Open
Capacitance (Note 3)
Symbol
Parameter
Typ
3
Max
Units
Conditions
CIN
Input Capacitance
Output Capacitance
Power Dissipation Capacitance (Note 4)
pF
pF
V
V
V
V
CC = Open, VIN 0V or VCC
CC = 3.3V, VIN = 0V or VCC
CC = 3.3V
COUT
CPD
4
10
12
pF
CC = 5.0V
Note 3: TA = +25C, f = 1MHz.
Note 4: CPD is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current consumption (ICCD) at no output
loading and operating at 50% duty cycle. (See Figure 2) CPD is related to ICCD dynamic operating current by the expression:
I
CCD = (CPD) (VCC) (fIN) + (ICCstatic).
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4
AC Loading and Waveforms
CP Input = AC Waveform; tr = tf = 1.8 ns;
CL includes load and stray capacitance
CP Input PRR = 10 MHz; Duty Cycle = 50%
D Input PRR = 5MHz; Duty Cycle = 50%
Input PRR = 1.0 MHz; tw = 500 ns
FIGURE 1. AC Test Circuit
FIGURE 2. ICCD Test Circuit
FIGURE 3. AC Waveforms
FIGURE 4. AC Waveforms
FIGURE 5. AC Waveforms
5
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Tape and Reel Specification
TAPE FORMAT for SC70
Package
Tape
Section
Number
Cavities
125 (typ)
3000
Cavity
Status
Empty
Filled
Cover Tape
Status
Designator
Leader (Start End)
Carrier
Sealed
P6X
Sealed
Trailer (Hub End)
75 (typ)
Empty
Sealed
TAPE DIMENSIONS inches (millimeters)
Tape Size
DIM A
DIM B
DIM F
DIM Ko
DIM P1
DIM W
Package
0.093
(2.35)
0.096
(2.45)
0.138 ± 0.004 0.053 ± 0.004
(3.5 ± 0.10) (1.35 ± 0.10)
0.157
(4)
0.315 ± 0.004
(8 ± 0.1)
SC70-6
8 mm
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6
Tape and Reel Specification (Continued)
TAPE FORMAT for MicroPak
Package
Tape
Section
Number
Cavities
125 (typ)
5000
Cavity
Status
Empty
Filled
Cover Tape
Status
Designator
Leader (Start End)
Carrier
Sealed
L6X
Sealed
Trailer (Hub End)
75 (typ)
Empty
Sealed
REEL DIMENSIONS inches (millimeters)
Tape
Size
A
B
C
D
N
W1
W2
W3
7.0
0.059
0.512
0.795
2.165 0.331 + 0.059/−0.000
0.567
W1 + 0.078/−0.039
(W1 + 2.00/−1.00)
8 mm
(177.8) (1.50) (13.00) (20.20) (55.00) (8.40 + 1.50/−0.00)
(14.40)
7
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Physical Dimensions inches (millimeters) unless otherwise noted
6-Lead SC70, EIAJ SC88, 1.25mm Wide
Package Number MAA06A
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8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
6-Lead MicroPak, 1.0mm Wide
Package Number MAC06A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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9
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