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NC7SZ58FHX_11 [FAIRCHILD]

TinyLogic® UHS Universal Configurable Two-Input Logic Gates;
NC7SZ58FHX_11
型号： NC7SZ58FHX_11
厂家： FAIRCHILD SEMICONDUCTOR    FAIRCHILD SEMICONDUCTOR
描述：

TinyLogic® UHS Universal Configurable Two-Input Logic Gates

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September 2011  
NC7SZ57 / NC7SZ58  
TinyLogic® UHS Universal Configurable Two-Input  
Logic Gates  
Features  
Description  
The NC7SZ57 and NC7SZ58 are universal configurable  
two-input logic gates. Each device is capable of being  
configured for 1 of 5 unique two-input logic functions.  
Any possible two-input combinatorial logic function can  
be implemented, as shown in the Function Selection  
Table. Device functionality is selected by how the device  
is wired at the board level. Figures 4 through 13  
illustrate how to connect the NC7SZ57 and NC7SZ58,  
respectively, for the desired logic function. All inputs  
have been implemented with hysteresis.  
.
.
Ultra High Speed  
Capable of Implementing any Two-Input Logic  
Functions  
Typical Usage Replaces Two (2) TinyLogic® Gate  
Devices  
.
.
.
.
.
Reduces Part Counts in Inventory  
Broad VCC Operating Range: 1.65V to 5.5V  
Power Down High Impedance Input/Output  
The device is fabricated with advanced CMOS  
technology to achieve ultra high speed with high output  
drive while maintaining low static power dissipation over  
a broad VCC operating range. The device is specified to  
operate over the 1.65V to 5.5V VCC operating range.  
The input and output are high impedance when VCC is  
0V. Inputs tolerate voltages up to 5.5V independent of  
Over-Voltage Tolerant Inputs Facilitate 5V to 3V  
Translation  
.
Proprietary Noise/EMI Reduction Circuitry  
Implemented  
VCC operating range.  
Ordering Information  
Part Number Top Mark  
Package  
Packing Method  
NC7SZ57P6X  
NC7SZ57L6X  
NC7SZ57FHX  
NC7SZ58P6X  
NC7SZ58L6X  
NC7SZ58FHX  
Z57  
KK  
KK  
Z58  
LL  
6-Lead SC70, EIAJ SC-88a, 1.25mm Wide  
6-Lead Micropak™, 1.0mm Wide  
3000 Units on Tape & Reel  
5000 Units on Tape & Reel  
3000 Units on Tape & Reel  
5000 Units on Tape & Reel  
6-Lead, MicroPak2™, 1x1mm Body, .35mm Pitch  
6-Lead SC70, EIAJ SC-88a, 1.25mm Wide  
6-Lead Micropak™, 1.0mm Wide  
LL  
6-Lead, MicroPak2™ , 1x1mm Body, .35mm Pitch  
© 2000 Fairchild Semiconductor Corporation  
NC7SZ57 • NC7SZ58 • Rev. 1.0.4  
www.fairchildsemi.com  
Pin Configurations  
Figure 1. SC70 (Top View)  
Figure 2. MicroPak™ (Top Through View)  
Figure 3. Pin 1 Orientation  
Notes:  
1. AAA represents product code top mark (see Ordering Information).  
2. Orientation of top mark determines pin one location.  
3. Reading the top mark left to right, pin one is the lower left pin.  
Pin Definitions  
Pin # SC70  
Pin # MicroPak™  
Name  
Description  
1
2
3
4
5
6
1
2
3
4
5
6
I1  
GND  
I0  
Data Input  
Ground  
Data Input  
Output  
Y
VCC  
I2  
Supply Voltage  
Data Input  
© 2000 Fairchild Semiconductor Corporation  
NC7SZ57 • NC7SZ58 • Rev. 1.0.4  
www.fairchildsemi.com  
2
Function Table  
Inputs  
NC7SZ57  
NC7SZ58  
I2  
L
I1  
L
I0  
L
Y = (I0) • (I2) + (I1) • (I2)  
Y = (I0) • (I2) + (I1) • (I2)  
H
L
L
H
L
L
L
H
L
L
H
H
L
H
L
L
H
L
H
H
H
L
H
H
H
H
L
L
H
L
L
H
H
H
H
H
L
H = HIGH Logic Level  
L = LOW Logic Level  
Function Selection Table  
2-Input Logic Function  
2-Input AND  
Device Selection  
Connection Configuration  
Figure 4  
NC7SZ57  
NC7SZ58  
NC7SZ57  
NC7SZ58  
NC7SZ57  
NC7SZ58  
NC7SZ58  
NC7SZ57  
NC7SZ58  
NC7SZ57  
NC7SZ58  
NC7SZ57  
NC7SZ58  
NC7SZ57  
2-Input AND with Inverted Input  
2-Input AND with Both Inputs Inverted  
2-Input NAND  
Figure 10, Figure 11  
Figure 7  
Figure 9  
2-Input NAND with Inverted Input  
2-Input NAND with Both Inputs Inverted  
2-Input OR  
Figure 5, Figure 6  
Figure 12  
Figure 12  
2-Input OR with Inverted Input  
2-Input OR with Both Inputs Inverted  
2-Input NOR  
Figure 5, Figure 6  
Figure 9  
Figure 7  
2-Input NOR with Inverted Input  
2-Input NOR with Both Inputs Inverted  
2-Input XOR  
Figure 9, Figure 10  
Figure 4  
Figure 13  
2-Input XNOR  
Figure 8  
© 2000 Fairchild Semiconductor Corporation  
NC7SZ57 • NC7SZ58 • Rev. 1.0.4  
www.fairchildsemi.com  
3
NC7SZ57 Logic Configurations  
Figure 4 through Figure 8 show the logical functions that  
can be implemented using the NC7SZ57. The diagrams  
show the DeMorgan’s equivalent logic duals for a given  
two-input function. The logical implementation is next to  
the board-level physical implementation of how the pins  
of the function should be connected.  
Figure 4. 2-Input AND Gate  
Figure 5. 2-Input NAND with Inverted A Input  
Figure 6. 2-Input NAND with Inverted B Input  
Figure 7. 2-Input NOR Gate  
Figure 8.  
2-Input XNOR Gate  
© 2000 Fairchild Semiconductor Corporation  
NC7SZ57 • NC7SZ58 • Rev. 1.0.4  
www.fairchildsemi.com  
4
NC7SZ58 Logic Configurations  
Figure 9 through Figure 13 show the logical functions  
that can be implemented using the NC7SZ58. The  
diagrams show the DeMorgan’s equivalent logic duals  
implementation is next to the board-level physical  
implementation of how the pins of the function should be  
connected.  
for  
a
given two-input function. The logical  
Figure 9.  
2-Input NAND Gate  
Figure 10. 2-Input AND with Inverted A Input  
Figure 11. 2-Input AND with Inverted B Input  
Figure 12. 2-Input OR Gate  
Figure 13. 2-Input XOR Gate  
© 2000 Fairchild Semiconductor Corporation  
NC7SZ57 • NC7SZ58 • Rev. 1.0.4  
www.fairchildsemi.com  
5
Absolute Maximum Ratings  
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be  
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.  
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.  
The absolute maximum ratings are stress ratings only.  
Symbol  
VCC  
Parameter  
Min.  
-0.5  
-0.5  
-0.5  
Max.  
7.0  
Units  
V
Supply Voltage  
VIN  
DC Input Voltage  
7.0  
V
VOUT  
IIK  
DC Output Voltage  
7.0  
V
DC Input Diode Current  
DC Output Diode Current  
DC Output Source / Sink Current  
DC VCC or Ground Current  
Storage Temperature Range  
VIN < 0.5V  
VOUT < -0.5V  
-50  
mA  
mA  
mA  
mA  
°C  
IOK  
-50  
IOUT  
±50  
±50  
+150  
+150  
+260  
130  
180  
120  
4000  
2000  
ICC or IGND  
TSTG  
TJ  
-65  
Maximum Junction Temperature under Bias  
Lead Temperature, Soldering 10 Seconds  
MicroPak™-6  
°C  
TL  
°C  
PD  
Power Dissipation at +85°C  
SC70-6  
mW  
V
MicroPak2™-6  
Human Body Model, JEDEC:JESD22-A114  
Charged Device Model, JEDEC:JESD22-C101  
ESD  
Recommended Operating Conditions  
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended  
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not  
recommend exceeding them or designing to Absolute Maximum Ratings.  
Symbol  
Parameter  
Supply Voltage Operating  
Supply Voltage Data Retention  
Input Voltage  
Conditions  
Min.  
1.65  
1.5  
0
Max.  
5.5  
Units  
V
VCC  
5.5  
VIN  
5.5  
V
V
VOUT  
Output Voltage  
0
VCC  
TA  
Operating Temperature  
Thermal Resistance  
-40  
+85  
°C  
SC70-6  
350  
500  
560  
MicroPak™-6  
MicroPak2™-6  
°C/W  
JA  
© 2000 Fairchild Semiconductor Corporation  
NC7SZ57 • NC7SZ58 • Rev. 1.0.4  
www.fairchildsemi.com  
6
DC Electrical Characteristics  
TA=+25°C  
TA=-40 to +85°C  
Symbo  
Parameter  
VCC  
Conditions  
Units  
l
Min.  
0.60  
1.00  
1.30  
1.90  
2.20  
0.20  
0.40  
0.60  
1.00  
1.20  
0.15  
0.25  
0.40  
0.60  
0.70  
1.55  
2.20  
2.90  
4.40  
1.29  
1.90  
2.40  
2.30  
3.80  
Typ.  
0.99  
1.39  
1.77  
2.49  
2.95  
0.50  
0.75  
0.99  
1.43  
1.70  
0.48  
0.64  
0.78  
1.06  
1.25  
1.65  
2.30  
3.00  
4.50  
1.52  
2.15  
2.80  
2.68  
4.20  
Max.  
1.40  
1.80  
2.20  
3.10  
3.60  
0.90  
1.15  
1.50  
2.00  
2.30  
0.90  
1.10  
1.20  
1.50  
1.70  
Min.  
0.60  
1.00  
1.30  
1.90  
2.20  
0.20  
0.40  
0.60  
1.00  
1.20  
0.15  
0.25  
0.40  
0.60  
0.70  
1.55  
2.20  
2.90  
4.40  
1.29  
1.90  
2.40  
2.30  
3.80  
Max.  
1.40  
1.80  
2.20  
3.10  
3.60  
0.90  
1.15  
1.50  
2.00  
2.30  
0.90  
1.10  
1.20  
1.50  
1.70  
1.65  
2.30  
3.00  
4.50  
5.50  
1.65  
2.30  
3.00  
4.50  
5.50  
1.65  
2.30  
3.00  
4.50  
5.50  
1.65  
2.30  
3.00  
4.50  
1.65  
2.30  
3.00  
3.00  
4.50  
Positive  
Threshold  
Voltage  
VP  
V
Negative  
Threshold  
Voltage  
VN  
V
V
Hysteresis  
Voltage  
VH  
VIN=VIH or VIL  
IOH= -100µA  
HIGH Level  
Output Voltage  
VOH  
I
OH= -4mA  
V
IOH= -8mA  
IOH= -16mA  
IOH= -24mA  
IOH= -32mA  
VIN=VIH  
or VIL  
Continued on the following page…  
© 2000 Fairchild Semiconductor Corporation  
NC7SZ57 • NC7SZ58 • Rev. 1.0.4  
www.fairchildsemi.com  
7
DC Electrical Characteristics (Continued)  
TA=+25°C  
Typ.  
TA=-40 to +85°C  
Symbol  
Parameter  
VCC  
Conditions  
Units  
Min.  
Max.  
Min.  
Max.  
1.65  
2.30  
3.00  
4.50  
1.65  
2.30  
3.00  
3.00  
4.50  
0.10  
0.10  
0.10  
0.10  
0.24  
0.30  
0.40  
0.55  
0.55  
0.10  
0.10  
0.10  
0.10  
0.24  
0.30  
0.40  
0.55  
0.55  
VIN=VIH or VIL  
IOL=100µA  
V
LOW Level  
Output Voltage  
VOL  
I
OL=4mA  
0.08  
0.10  
0.15  
0.22  
0.22  
IOL=8mA  
VIN=VIH or  
VIL  
IOL=16mA  
IOL=24mA  
IOL=32mA  
Input Leakage  
Current  
0 to  
5.50  
IIN  
IOFF  
ICC  
±0.1  
1
±1.0  
10  
µA  
µA  
µA  
VIN 5.5V, GND  
VIN or VOUT5.5V  
VIN 5.5V, GND  
Power Off  
Leakage  
Current  
0
Quiescent  
Supply Current  
1.65 to  
5.5  
1
10  
AC Electrical Characteristics  
TA=25°C  
TA=-40 to 85°C  
Symbol Parameter  
VCC  
Conditions  
Units Figure  
Min. Typ. Max. Min.  
Max.  
14.5  
8.5  
1.8 ± 0.15  
2.5 ± 0.2  
3.3 ± 0.3  
5.0 ± 0.5  
3.3 ± 0.3  
5.0 ± 0.5  
3.0  
1.5  
1.2  
0.8  
1.5  
1.0  
8.0  
4.9  
3.7  
2.8  
4.2  
3.4  
14.0  
8.0  
5.3  
4.3  
6.0  
4.9  
3.0  
1.5  
1.2  
0.8  
1.5  
1.0  
CL=15pF, RL=1M  
5.7  
Propagation  
tPHL, tPLH  
Figure 14  
ns  
Delay In to Y  
Figure 16  
4.6  
6.5  
CL=50pF,  
RL=500  
5.3  
Input  
CIN  
0
2
pF  
Capacitance  
Power  
Dissipation  
Capacitance  
3.3  
5.0  
14  
17  
CPD  
Note 4  
pF  
Figure 15  
Note:  
4. CPD is defined as the value of the internal equivalent capacitance which is derived from dynamic operating  
current consumption (ICCD) at no output loading and operating at 50% duty cycle. (See Figure 12) CPD is related  
to ICCD dynamic operatic current by the expression: ICCD = (CPD)(VCC)(fin) + (ICCstatic).  
© 2000 Fairchild Semiconductor Corporation  
NC7SZ57 • NC7SZ58 • Rev. 1.0.4  
www.fairchildsemi.com  
8
AC Loadings and Waveforms  
Note:  
5. CL includes load and stray capacitance.  
6. Input PRR = 1.0MHz, tW = 500ns.  
Figure 14. AC Test Circuit  
Note:  
7. Input = AC waveforms.  
8. PRR = Variable; Duty Cycle = 50%.  
Figure 15.  
ICCD Test Circuit  
Figure 16. AC Waveforms  
© 2000 Fairchild Semiconductor Corporation  
NC7SZ57 • NC7SZ58 • Rev. 1.0.4  
www.fairchildsemi.com  
9
Physical Dimensions  
SYMM  
C
L
±0.20  
2.00  
A
0.65  
0.50 MIN  
6
4
B
PIN ONE  
±0.10  
1.25  
1.90  
1
3
0.30  
0.15  
(0.25)  
0.40 MIN  
0.10  
A B  
1.30  
0.65  
1.30  
LAND PATTERN RECOMMENDATION  
SEE DETAIL A  
1.00  
0.80  
1.10  
0.80  
0.10 C  
0.10  
0.00  
C
2.10±0.30  
SEATING  
PLANE  
NOTES: UNLESS OTHERWISE SPECIFIED  
GAGE  
PLANE  
A) THIS PACKAGE CONFORMS TO EIAJ  
SC-88, 1996.  
B) ALL DIMENSIONS ARE IN MILLIMETERS.  
C) DIMENSIONS DO NOT INCLUDE BURRS  
OR MOLD FLASH.  
(R0.10)  
0.25  
0.10  
D) DRAWING FILENAME: MKT-MAA06AREV6  
0.20  
30°  
0°  
0.46  
0.26  
DETAIL A  
SCALE: 60X  
Figure 17. 6-Lead, SC70, EIAJ SC-88a, 1.25mm Wide  
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner  
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or  
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the  
warranty therein, which covers Fairchild products.  
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:  
http://www.fairchildsemi.com/packaging/.  
Tape and Reel Specifications  
Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:  
http://www.fairchildsemi.com/products/analog/pdf/sc70-6_tr.pdf  
Package Designator  
Tape Section  
Leader (Start End)  
Carrier  
Cavity Number  
125 (Typical)  
3000  
Cavity Status Cover Type Status  
Empty  
Filled  
Sealed  
Sealed  
Sealed  
P6X  
Trailer (Hub End)  
75 (Typical)  
Empty  
© 2000 Fairchild Semiconductor Corporation  
NC7SZ57 • NC7SZ58 • Rev. 1.0.4  
www.fairchildsemi.com  
10  
Physical Dimensions  
2X  
0.05 C  
1.45  
B
(1)  
2X  
0.05 C  
(0.49)  
5X  
(0.254)  
1.00  
(0.75)  
(0.52)  
1X  
A
TOP VIEW  
PIN 1 IDENTIFIER  
5
0.55MAX  
(0.30)  
6X  
PIN 1  
0.05 C  
0.05  
0.00  
RECOMMENED  
LAND PATTERN  
0.05 C  
C
0.45  
0.35  
0.10  
6X  
0.00  
0.25  
6X  
0.15  
1.0  
DETAIL A  
0.10  
C B A  
0.40  
0.30  
0.05  
C
0.35  
0.25  
5X  
5X  
0.40  
0.30  
DETAIL A  
PIN 1 TERMINAL  
0.075 X 45  
CHAMFER  
0.5  
BOTTOM VIEW  
(0.05)  
6X  
(0.13)  
4X  
Notes:  
1. CONFORMS TO JEDEC STANDARD M0-252 VARIATION UAAD  
2. DIMENSIONS ARE IN MILLIMETERS  
3. DRAWING CONFORMS TO ASME Y14.5M-1994  
4. FILENAME AND REVISION: MAC06AREV4  
5. PIN ONE IDENTIFIER IS 2X LENGTH OF ANY  
OTHER LINE IN THE MARK CODE LAYOUT.  
Figure 18. 6-Lead, MicroPak™, 1.0mm Wide  
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner  
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or  
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the  
warranty therein, which covers Fairchild products.  
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:  
http://www.fairchildsemi.com/packaging/.  
Tape and Reel Specifications  
Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:  
http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf.  
Package Designator  
Tape Section  
Leader (Start End)  
Carrier  
Cavity Number  
125 (Typical)  
5000  
Cavity Status Cover Type Status  
Empty  
Filled  
Sealed  
Sealed  
Sealed  
L6X  
Trailer (Hub End)  
75 (Typical)  
Empty  
© 2000 Fairchild Semiconductor Corporation  
NC7SZ57 • NC7SZ58 • Rev. 1.0.4  
www.fairchildsemi.com  
11  
Physical Dimensions  
0.89  
0.35  
0.05 C  
2X  
1.00  
B
A
5X 0.40  
1X 0.45  
PIN 1  
0.66  
MIN 250uM  
1.00  
6X 0.19  
0.05 C  
TOP VIEW  
RECOMMENDED LAND PATTERN  
FOR SPACE CONSTRAINED PCB  
2X  
0.90  
0.35  
0.05 C  
0.55MAX  
C
5X 0.52  
SIDE VIEW  
0.73  
0.57  
1X  
(0.08) 4X  
DETAIL A  
0.09  
0.19  
6X  
1
2
3
0.20 6X  
ALTERNATIVE LAND PATTERN  
FOR UNIVERSAL APPLICATION  
(0.05) 6X  
0.35  
0.25  
5X  
0.60  
6
5
4
0.10  
.05 C  
C B A  
0.40  
0.30  
0.35  
(0.08)  
4X  
BOTTOM VIEW  
NOTES:  
A. COMPLIES TO JEDEC MO-252 STANDARD  
B. DIMENSIONS ARE IN MILLIMETERS.  
0.075X45°  
CHAMFER  
C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994  
D. LANDPATTERN RECOMMENDATION IS BASED ON FSC  
DESIGN.  
DETAIL A  
PIN 1 LEAD SCALE: 2X  
E. DRAWING FILENAME AND REVISION: MGF06AREV3  
Figure 19. 6-Lead, MicroPak2™, 1x1mm Body, .35mm Pitch  
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner  
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or  
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the  
warranty therein, which covers Fairchild products.  
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:  
http://www.fairchildsemi.com/packaging/.  
Tape and Reel Specifications  
Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:  
http://www.fairchildsemi.com/packaging/MicroPAK2_6L_tr.pdf.  
Package Designator  
Tape Section  
Leader (Start End)  
Carrier  
Cavity Number  
125 (Typical)  
5000  
Cavity Status Cover Type Status  
Empty  
Filled  
Sealed  
Sealed  
Sealed  
FHX  
Trailer (Hub End)  
75 (Typical)  
Empty  
© 2000 Fairchild Semiconductor Corporation  
NC7SZ57 • NC7SZ58 • Rev. 1.0.4  
www.fairchildsemi.com  
12  
© 2000 Fairchild Semiconductor Corporation  
NC7SZ57 • NC7SZ58 • Rev. 1.0.4  
www.fairchildsemi.com  
13  

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SI9135_11

 SMBus Multi-Output Power-Supply Controller

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SI9136_11

 Multi-Output Power-Supply Controller

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SI9130CG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

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SI9130LG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

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SI9130_11

 Pin-Programmable Dual Controller - Portable PCs

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SI9137

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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SI9137DB

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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SI9137LG

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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SI9122E

 500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification Drivers

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