NM24C32FN [FAIRCHILD]

I2C Serial EEPROM ; I2C串行EEPROM\n


型号：	NM24C32FN
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	I2C Serial EEPROM I2C串行EEPROM\n 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件：	总12页 (文件大小：91K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PRELIMINARY

March 1999

NM24C32

32K-Bit Extended 2-Wire Bus Interface

Serial EEPROM with Write Protect

General Description:

Features:

The NM24C32 devices are 32,768 bits of CMOS nonvolatile

electrically erasable memory. These devices offer the designer

different low voltage and low power options, and they conform to

allspecificationsintheExtendedIIC2-wireprotocol.Furthermore,

they are designed to minimize device pin count and simplify PC

board layout requirements.

■ Extended operating voltage 2.7V – 5.5V

■ 400 KHz clock frequency (F) at 2.7V - 5.5V

■ 200µA active current typical

10µA standby current typical

1µA standby typical (L)

0.1µA standby typical (LZ)

The upper half of the memory can be disabled (Write Protection)

by connecting the WP pin to V_CC. This section of memory then

becomes ROM.

■ IIC compatible interface

– Provides bidirectional data transfer protocol

■ 32 byte page write mode

This communication protocol uses CLOCK (SCL) and DATA I/O

(SDA) lines to synchronously clock data between the master (for

example a microprocessor) and the slave EEPROM device(s).

– Minimizes total write time per byte

■ Self timed write cycle

Typical write cycle time of 6ms

Fairchild EEPROMs are designed and tested for applications

requiring high endurance, high reliability, and low power con-

sumption.

■ Hardware write protect for upper block

■ Endurance: 1,000,000 data changes

■ Data retention greater than 40 years

■ Packages available: 8-pin SO, 8-pin DIP

■ Low V_CCprogramming lockout (3.8V - on Standard V_CC

devices only).

Block Diagram

WRITE

LOCKOUT

H.V. GENERATION

TIMING &CONTROL

START CYCLE

START

STOP

SDA

LOGIC

CONTROL

LOGIC

SLAVE ADDRESS

COMPARATOR

E PROM

ARRAY

XDEC

SCL

LOAD

INC

WORD

ADDRESS

COUNTER

R/W

YDEC

OUT

DATA REGISTER

DS500073-1

NM24C32 Rev. C.2

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Connection Diagram

Dual-In-Line Package (N)

and 8-Pin SO Package (M8)

Pin Names

Device Address Input

Ground

A0, A1, A2

V_SS

SDA

Data I/O

SCL

Clock Input

NM24C32

Top View

Write Protect

Power Supply

SCL

SDA

V_CC

DS500073-2

See Package Number N08E and M08A

Ordering Information

NM 24

Letter Description

Package

8-Pin DIP

8-Pin SOIC

Temp. Range

None

0 to 70°C

-40 to +125°C

-40 to +85°C

Voltage Operating Range

Blank

4.5V to 5.5V

2.7V to 4.5V

2.7V to 4.5V and

<1µA Standby Current

SCL Clock Frequency

Density

Blank

100KHz

400KHz

32K with Write Protect

CMOS

IIC

Interface

Fairchild Non-Volatile

Memory

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NM24C32 Rev. C.2

Product Specifications

Operating Conditions

Absolute Maximum Ratings

Ambient Operating Temperature

NM24C32

Ambient Storage Temperature

–65°C to +150°C

0°C to +70°C

-40°C to +85°C

-40°C to +125°C

All Input or Output Voltages

with Respect to Ground

NM24C32E

NM24C32V

6.5V to –0.3V

Lead Temperature

Positive Power Supply

NM24C32

(Soldering, 10 seconds)

+300°C

4.5V to 5.5V

2.7V to 4.5V

NM24C32L

NM24C32LZ

ESD Rating

2000V min.

Standard V_CC(4.5V to 5.5V) DC Electrical Characteristics

Symbol

Parameter

Test Conditions

Limits

Units

Min

Typ (Note 1)

Max

I_CCA

I_SB

I_LI

Active Power Supply Current

Standby Current

f_SCL= 100 kHz

0.2

1.0

µA

V_IN= GND or V_CC

V_IN= GND to V_CC

V_OUT= GND to V_CC

Input Leakage Current

Output Leakage Current

Input Low Voltage

0.1

I_LO

V_IL

V_IH

V_OL

–0.3

V_CCx 0.3

V_CC+ 0.5

0.4

Input High Voltage

V_CCx 0.7

Output Low Voltage

I_OL= 3 mA

Low V_CC(2.7V to 4.5V) DC Electrical Characteristics

Symbol

Parameter

Test Conditions

Limits

Units

Min

Typ (Note 1)

Max

I_CCA

Active Power Supply Current

f_SCL= 100 kHz

0.2

1.0

I_SB

(Note 1)

Standby Current for L

Standby Current for LZ

V_IN= GND or V_CC

0.1

µA

I_LI

I_LO

Input Leakage Current

Output Leakage Current

Input Low Voltage

V_IN= GND to V_CC

V_OUT= GND to V_CC

0.1

µA

V_IL

V_IH

V_OL

–0.3

V_CCx 0.3

V_CC+ 0.5

0.4

Input High Voltage

V_CCx 0.7

Output Low Voltage

I_OL= 3 mA

Capacitance T_A= +25°C, f = 100/400 KHz, V_CC= 5V (Note 2)

Symbol

C_I/O

Test

Conditions

V_I/O= 0V

Max Units

Input/Output Capacitance (SDA)

Input Capacitance (A0, A1, A2, SCL)

C_IN

V_IN= 0V

Note 1: Typical values are for T_A= 25°C and nominal supply voltage (5V).

Note 2: This parameter is periodically sampled and not 100% tested.

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NM24C32 Rev. C.2

AC Conditions of Test

Input Pulse Levels

V_CCx 0.1 to V_CCx 0.9

Input Rise and Fall Times

10 ns

Input & Output Timing Levels V_CCx 0.5

Output Load

1 TTL Gate and C_L= 100 pF

Read and Write Cycle Limits (Standard and Low V_CCRange - 2.7V-5.5V)

Symbol

Parameter

100 KHz

400 KHz

Units

kHz

Min

Max

Min

Max

f_SCL

T_I

SCL Clock Frequency

100

3.5

400

Noise Suppression Time Constant at

SCL, SDA Inputs (Minimum V_IN

Pulse width)

t_AA

SCL Low to SDA Data Out Valid

0.3

4.7

0.1

1.3

0.9

µs

t_BUF

Time the Bus Must Be Free before

a New Transmission Can Start

t_HD:STA

t_LOW

Start Condition Hold Time

Clock Low Period

4.0

4.7

4.0

4.7

0.6

1.5

0.6

µs

t_HIGH

Clock High Period

t_SU:STA

Start Condition Setup Time

(for a Repeated Start Condition)

t_HD:DAT

t_SU:DAT

t_R

Data in Hold Time

µs

Data in Setup Time

250

100

SDA and SCL Rise Time

SDA and SCL Fall Time

Stop Condition Setup Time

Data Out Hold Time

0.3

t_F

300

t_SU:STO

t_DH

4.7

0.6

300

t_WR

(Note 3)

Write Cycle Time - NM24C32

- NM24C32L, NM24C32LZ

Note 3: The write cycle time (t_WR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the

NM24C32 bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address

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NM24C32 Rev. C.2

Bus Timing

HIGH

LOW

SCL

SU:STO

SU:STA

HD:DAT

SU:DAT

HD:STA

SDA

BUF

SDA

OUT

DS500073-3

BACKGROUND INFORMATION (IIC Bus)

Definitions

Asmentioned,theIICbusallowssynchronousbidirectionalcommu-

nication between Transmitter/Receiver using the SCL (clock) and

SDA (Data I/O) lines. All communication must be started with a valid

START condition, concluded with a STOP condition and acknowl-

edged by the Receiver with an ACKNOWLEDGE condition.

Word

Page

8 bits (byte) of data

32 sequential addresses (one byte

each) that may be programmed during

a "Page Write" programming cycle.

In addition, since the IIC bus is designed to support other devices

such as RAM, EPROM, etc., the device type identifier string, or

slave address, must follow the START condition. For EEPROMs,

the first 4-bits of the slave address is '1010'. This is then followed

by the device selection bits A2, A1 and A0.The final bit in the slave

address determines the type of operation performed (READ/

WRITE). A"1"signifiesaREADwhilea"0"signifiesaWRITE. The

slave address is then followed by two bytes that define the word

address, which is then followed by the data byte.

Master

Slave

Any IIC device CONTROLLING the

transfer of data (such as a microcon-

troller).

Device being controlled (EEPROMS

are always considered Slaves).

Transmitter

Receiver

Device currently SENDING data on the

bus (may be either a Master or Slave).

The EEPROMs on the IIC bus may be configured in any manner

required, providing the total memory addressed does not exceed

4M bits in the Extended IIC protocol. EEPROM memory address-

ing is controlled by hardware configuring the A2, A1, and A0 pins

(Device Address pins) with pull-up or pull-down resistors. ALL

UNUSED PINS MUST BE GROUNDED (tied to V_SS).

Device currently receiving data on the

bus (Master or Slave).

Pin Description

Addressing an EEPROM memory location involves sending a

command string with the following information:

SERIAL CLOCK (SCL)

The SCL input is used to clock all data into and out of the device.

[DEVICE TYPE]-[DEVICE ADDRESS]-[PAGE BLOCK AD-

DRESS]-[BYTE ADDRESS]

SERIAL DATA (SDA)

SDA is a biderectional pin used to transfer data into and out of the

device. It is an open drain output and may be wire-ORed with any

number of open drain or open collector outputs.

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NM24C32 Rev. C.2

START CONDITION

Device Address Inputs (A0, A1, A2)

All commands are preceded by the start condition, which is a

HIGH to LOW transition of SDA when SCL is HIGH. The

NM24C32xxx continuously monitors the SDA and SCL lines for

the start condition and will not respond to any command until this

condition has been met.

Device address pins A0, A1, and A2 are connected to V_CCor V_SS

to configure the EEPROM address for multiple device configura-

tion. A total of eight different devices can be attached to the same

SDA bus.

Write Protection (WP)

IfWPistiedtoV_CC,programWRITEoperationsontotheupperhalf

of the memory will not be executed. READ operations are always

available.

STOP CONDITION

All communications are terminated by a stop condition, which is a

LOW to HIGH transition of SDA when SCL is HIGH. The stop

condition is also used by the NM24C32xxx to place the device in

the standby power mode.

If WP is tied to V_SS, normal memory operation is enabled, READ/

WRITE over the entire memory array.

Write Cycle Timing

Thisfeatureallowstheusertoassigntheupperhalfofthememory

as ROM which can be protected against accidental programming

writes. WhenWRITEisdisabled, slaveaddressandwordaddress

will be acknowledged but data will not be acknowledged.

ACKNOWLEDGE

Acknowledgeisasoftwareconventionusedtoindicatesuccessful

data transfers. The transmitting device, either master or slave, will

release the bus after transmitting eight bits. During the ninth clock

cycle the receiver will pull the SDA line LOW to acknowledge that

it received the eight bits of data. Refer to Figure 4.

Device Operation

The NM24C32xxx supports a bidirectional bus oriented protocol.

The protocol defines any device that sends data onto the bus as

atransmitterandthereceivingdevicesasthereceiver.Thedevice

controlling the transfer is the master and the device that is

controlled is the slave. The master will always initiate data

transfers and provide the clock for both transmit and receive

operations. Therefore, the NM24C32xxx is considered a slave in

all applications.

The NM24C32xxx device will always respond with an acknowl-

edge after recognition of a start condition and its slave address. If

both the device and a WRITE operation have been selected, the

NM24C32xxx will respond with an acknowledge after the receipt

of each subsequent eight bit word.

In the READ mode the NM24C32xxx slave will transmit eight bits

of data, release the SDA line and monitor the line for an acknowl-

edge. If an acknowledge is detected and no stop condition is

generated by the master, the slave will continue to transmit data.

If an acknowledge is not detected, the slave will terminate further

data transmissions and await the stop condition to return to the

standby power mode.

CLOCK AND DATA CONVENTIONS

Data states on the SDA line can change only during SCL LOW.

SDA state changes during SCL HIGH and reserved for indicating

start and stop conditions. Refer to Figures 2 and 3.

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NM24C32 Rev. C.2

Write Cycle Timing (Figure 1)

SCL

SDA

8th BIT

WORD n

ACK

STOP

START

CONDITION

DS500073-4

Data Validity (Figure 2)

SCL

SDA

DATA

CHANGE

DATA STABLE

DS500073-5

Definition of Start and Stop (Figure 3)

SCL

START

BIT

STOP

BIT

SDA

DS500073-6

Acknowledge Response from Receiver (Figure 4)

SCL FROM

MASTER

Data Output

from Transmitter

Data Output

from Receiver

START

Acknowledge

DS500073-7

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NM24C32 Rev. C.2

transfer by generating a stop condition, at which time the

NM24C32xxx begins the internal write cycle to the nonvolatile

memory. While the internal write cycle is in progress, the device's

inputsaredisabledandthedevicewillnotrespondtoanyrequests

from the master. Refer to Figure 5 for the address, acknowledge

and data transfer sequence.

DEVICE ADDRESSING

Following a start condition the master must output the address of

the slave it is accessing. The most significant four bits of the slave

address are those of the device type identifier. This is fixed as

1010 for all EEPROM devices.

The next three bits identifies the device address. Address from

000 to 111 are acceptable thus allowing up to eight devices to be

connected to the IIC bus.

PAGE WRITE

The NM24C32xxx is capable of thirty-two byte page write opera-

tion. It is initiated in the same manner as the byte write operation;

but instead of termination the write cycle after the first data word

istransfered, themastercantransmituptothirty-onemorewords.

After the receipt of each word, the device responds with an

acknowledge.

The last bit of the slave address defines whether a write or read

condition is requested by the master. A "1" indicates that a READ

operation is to be executed and a "0" initiates the WRITE mode.

A simple review: After the NM24C32xxx recognizes the start

condition, the devices interfaced to the IIC bus waits for a slave

address to be transmitted over the SDA line. If the transitted slave

addressmatchesanaddressofoneofthedevices,thedesignated

slave pulls the line LOW with an acknowledge. signal and awaits

further transmissions.

After the receipt of each word, the internal address counter

increments to the next address and the next SDA data is ac-

cepted. If the master should transmit more than thirty-two words

priortogeneratingthestopcondition,theaddresscounterwill"roll

over" and the previous written data will be overwritten. As with the

byte write operation, all inputs are disabled until completion of the

internal write cycle. Refer to Figure 6 for the address, acknowl-

edge and data transfer sequence.

Write Operations

BYTE WRITE

For a WRITE operation, two additional address bytes, with 12

active bits, are required after the SLAVE acknowledge to address

the full memory array. The first byte indicates the high-order byte

of the word address. Only the four least signicant bits can be

changed, the other bits are pre-assigned the value "0". Following

the acknowledgement from the first word address, the next byte

indicates the low-order byte of the word address. Upon receipt of

the word address, the NM24C32xxx responds with another ac-

knowledge and waits for the next eight bits of data, again,

responding with an acknowledge. The master then terminates the

Acknowledge Polling

Once the stop condition is isssued to indicate the end of the host's

writeoperation, theNM24C32xxxinitiatestheinternalwritecycle.

ACKpollingcanbeinitiatedimmediately.Thisinvolvesissuingthe

start condition followed by the slave address for a write operation.

If the NM24C32xxx is still busy with the write operation, no ACK

will be returned. If the device has completed the write operation,

an ACK will be returned and the host can then proceed with the

next read or write operation.

Byte Write (Figure 5)

SLAVE

ADDRESS

WORD

ADDRESS (1)

WORD

ADDRESS (0)

DATA

Bus Activity:

Master

1 0

0 0 0 0

SDA Line

Bus Activity

DS500073-8

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NM24C32 Rev. C.2

transfer but does generate a stop condition, and therefore discon-

tinues transmission. Refer to Figure 7 for the sequence of ad-

dress, acknowledge and data transfer.

Write Protection

Programming of the upper half of memory will not take place if the

WPpinisconnectedtoV_CC. Thedevicewillacceptslaveandword

addresses; but if the memory accessed is write protected by the

WP pin, the NM24C32xxx will not generate an acknowledge after

the first byte of data has been received, and thus the program

cycle will not be started when the stop condition is asserted.

RANDOM READ

Random read operations allow the master to access any memory

location in a random manner. Prior to issuing the slave address

withtheR/Wbitsetto"1", themastermustfirstperforma"dummy"

writeoperation.Themasterissuesastartcondition,slaveaddress

and then the word address it is to read. After the word address

acknowledge, the master immediately reissues the start condition

and the slave address with the R/W bit set to "1". This will be

followed by an acknowledge from the NM24C32xxx and then by

the eight bit word. The master will not acknowledge the transfer

but does generate the stop condition, and therefore the

NM24C32xxx discontinues transmission. Refer to Figure 8 for the

address, acknowledge and data transfer sequence.

Low V_CCLockout

NM24C32xxx provides data security against inadvertent writes

that could potentially happen during the time the device is being

powered on, powered down and brown out conditions by monitor-

ing the V_CCvoltage during a write cycle. Whenever a write cycle

is started, the built-in circuitry starts to monitor the V_CClevel

throughout the duration of the write command sequence until the

master issues the required STOP condition to start the actual

internal write operation. If the sensed V_CCvoltage is below 3.8V at

any point during this monitoring period, the device prohibits the

write operation and does not generate the ACK pulse. This low

V_CClockout feature is only available for standard 5V device.

SEQUENTIAL READ

Sequential reads can be initiated as either a current address read

or random access read. The first word is transmitted in the same

manner as the other read modes; however, the master now

responds with an acknowledge, indicating it requires additional

data. The NM24C32xxx continues to output data for each ac-

knowledge received. The read operation is terminated by the

master not responding with an acknowledge or by generating a

stop condition.

Read Operation

Read operations are initiated in the same manner as write

operations,withtheexceptionthattheR/Wbitoftheslaveaddress

is set to "1". There are three basic read operations: current

address read, random read and sequential read.

The data output is sequential, with the data from address n

followedbythedatan+1. Theaddresscounterforreadoperations

increments all word address bits, allowing the entire memory

contents to be serially read during one operation. After the entire

memory has been read, the counter "rolls over" and the

NM24C32xxx continues to output data for each acknowledge

received. RefertoFigure9fortheaddress, acknowledgeanddata

transfer sequence.

CURRENT ADDRESS READ

Internally the NM24C32xxx contains an address counter that

maintains the address of the last word accessed, incremented by

one. Therefore, if the last access (either a read or write) was to

address n, the next read operation would access data from

address n+1. Upon receipt of the slave address with R/W set to

one, the NM24C32xxx issues an acknowledge and transmits the

eight bit word. The master will not acknowledge acknowledge the

Page Write (Figure 6)

SLAVE

ADDRESS

WORD

ADDRESS (1)

WORD

ADDRESS (0)

DATA n

DATA n+31

Bus Activity:

Master

1 0

0 0 0 0

SDA Line

Bus Activity

DS500073-9

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NM24C32 Rev. C.2

Current Address Read (Figure 7)

SLAVE

ADDRESS

DATA

1 0 1 0

DS500073-10

Random Read (Figure 8)

WORD

ADDRESS (1)

WORD

ADDRESS (0)

SLAVE

ADDRESS

SLAVE

ADDRESS

Bus Activity:

Master

DATA n

1 0

0 0

1 0 1 0

1 0

SDA Line

Bus Activity

DS500073-11

Sequential Read (Figure 9)

SLAVE

ADDRESS

DATA n

DATA n + 1

DATA n + x

Bus Activity:

Master

0 1 0

SDA Line

Bus Activity

DS500073-12

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NM24C32 Rev. C.2

Physical Dimensions inches (millimeters) unless otherwise noted

0.189 - 0.197

(4.800 - 5.004)

0.228 - 0.244

(5.791 - 6.198)

Lead #1

IDENT

0.150 - 0.157

0.053 - 0.069

(1.346 - 1.753)

(3.810 - 3.988)

0.010 - 0.020

(0.254 - 0.508)

0.004 - 0.010

(0.102 - 0.254)

x 45°

8° Max, Typ.

All leads

Seating

Plane

0.04

0.0075 - 0.0098

(0.190 - 0.249)

Typ. All Leads

(0.102)

All lead tips

0.014

(0.356)

0.016 - 0.050

(0.406 - 1.270)

Typ. All Leads

0.050

(1.270)

Typ

0.014 - 0.020

(0.356 - 0.508)

Typ.

Molded Small Out-Line Package (M8)

Order Number NM24C32xxxM8 or NM24C32xxxEM8

Package Number M08A

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NM24C32 Rev. C.2

Physical Dimensions inches (millimeters) unless otherwise noted

0.373 - 0.400

(9.474 - 10.16)

0.090

(2.286)

0.032 ± 0.005

(0.813 ± 0.127)

0.092

(2.337)

RAD

DIA

0.250 - 0.005

Pin #1

IDENT

Pin #1 IDENT

(6.35 ± 0.127)

Option 1

Option 2

0.280

MIN

0.040

(1.016)

Typ.

(7.112)

0.030

0.145 - 0.200

(3.683 - 5.080)

0.039

(0.991)

MAX

(0.762)

0.300 - 0.320

(7.62 - 8.128)

20° ± 1°

0.130 ± 0.005

(3.302 ± 0.127)

0.125 - 0.140

95° ± 5°

0.009 - 0.015

(3.175 - 3.556)

0.065

(1.651)

0.125

(3.175)

DIA

0.020

90° ± 4°

Typ

(0.508)

Min

(0.229 - 0.381)

0.018 ± 0.003

(0.457 ± 0.076)

NOM

+0.040

-0.015

0.325

0.100 ± 0.010

+1.016

-0.381

8.255

(2.540 ± 0.254)

0.045 ± 0.015

(1.143 ± 0.381)

0.060

(1.524)

0.050

(1.270)

Molded Dual-In-Line Package (N)

Order Number NM24C32xxxN or NM24C32xxxEN

Package Number N08E

Life Support Policy

Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written

approval of the President of Fairchild Semiconductor Corporation. As used herein:

1. Life support devices or systems are devices or systems which,

(a)areintendedforsurgicalimplantintothebody,or(b)support

or sustain life, and whose failure to perform, when properly

used in accordance with instructions for use provided in the

labeling, can be reasonably expected to result in a significant

injury to the user.

2. A critical component is any component of a life support device

or system whose failure to perform can be reasonably ex-

pected to cause the failure of the life support device or system,

or to affect its safety or effectiveness.

Fairchild Semiconductor

Americas

Fairchild Semiconductor

Europe

Fairchild Semiconductor

Hong Kong

Fairchild Semiconductor

Japan Ltd.

Customer Response Center

Tel. 1-888-522-5372

Fax:

Tel:

+44 (0) 1793-856858

8/F, Room 808, Empire Centre

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Tel: 81-3-3818-8840

Fax: 81-3-3818-8841

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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NM24C32 Rev. C.2

NM24C32FN [FAIRCHILD]

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