NM25C040VM8 [FAIRCHILD]
4K-Bit Serial CMOS EEPROM (Serial Peripheral Interface (SPI) Synchronous Bus); 4K位串行CMOS EEPROM （串行外设接口（ SPI ），同步总线）
| 型号： | NM25C040VM8 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 4K-Bit Serial CMOS EEPROM (Serial Peripheral Interface (SPI) Synchronous Bus) |
| 文件： | 总10页 (文件大小：105K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 1999
NM25C040
4K-Bit Serial CMOS EEPROM
(Serial Peripheral Interface (SPI) Synchronous Bus)
General Description
Features
The NM25C040 is a 4096-bit CMOS EEPROM with an SPI
compatible serial interface. The NM25C040 is designed for data
storage in applications requiring both non-volatile memory and in-
systemdataupdates. ThisEEPROMiswellsuitedforapplications
using the 68HC11 series of microcontrollers that support the SPI
interface for high speed communication with peripheral devices
via a serial bus to reduce pin count. The NM25C040 is imple-
mented in Fairchild Semiconductor’s floating gate CMOS process
that provides superior endurance and data retention.
■ 2.1 MHz clock rate @ 2.7V to 5.5V
■ 4096 bits organized as 512 x 8
■ Multiple chips on the same 3-wire bus with separate chip
select lines
■ Self-timed programming cycle
■ Simultaneous programming of 1 to 4 bytes at a time
■ Status register can be polled during programming to monitor
READY/BUSY
The serial data transmission of this device requires four signal
lines to control the device operation: Chip Select (CS), Clock
(SCK), Data In (SI), and Serial Data Out (SO). All programming
cycles are completely self-timed and do not require an erase
before WRITE.
■ Write Protect (WP) pin and write disable instruction for both
hardware and software write protection
■ Block write protect feature to protect against accidental
writes
■ Endurance: 1,000,000 data changes
BLOCK WRITE protection is provided by programming the STA-
TUS REGISTER with one of four levels of write protection.
Additionally, separate WRITE enable and WRITE disable instruc-
tions are provided for data protection.
■ Data retention greater than 40 years
■ Packages available: 8-pin DIP, 8-pin SO, or 8-pin TSSOP
Hardware data protection is provided by the WP pin to protect
against inadvertent programming. The HOLD pin allows the serial
communication to be suspended without resetting the serial
sequence.
Block Diagram
CS
HOLD
SCK
VCC
VSS
Instruction
Decoder
Control Logic
and Clock
WP
Instruction
SI
Generators
Register
Program
Enable
Address
Counter/
Register
High Voltage
Generator
and
Program
Timer
VPP
EEPROM Array
4096 Bits
(512 x 8)
Decoder
1 of 512
Read/Write Amps
Data In/Out Register
8 Bits
Data Out
Buffer
SO
Non-Volatile
Status Register
DS012401-1
1
© 1999 Fairchild Semiconductor Corporation
NM25C040 Rev. D.1
www.fairchildsemi.com
Connection Diagram
Dual-In-Line Package (N), SO Package (M8),
and TSSOP Package (MT8)
CS
SO
WP
VSS
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
NM25C040
DS012401-2
Top View
See Package Number N08E (N), M08A (M8), and MTC08 (MT8)
Pin Names
CS
SO
Chip Select Input
Serial Data Output
Write Protect
WP
VSS
Ground
SI
Serial Data Input
Serial Clock Input
Suspends Serial Data
Power Supply
SCK
HOLD
VCC
Ordering Information
NM 25
C
XX LZ E XX
Letter Description
Package
Temp. Range
N
M8
MT8
8-pin DIP
8-pin SO
8-pin TSSOP
None
0 to 70°C
V
E
-40 to +125°C
-40 to +85°C
Voltage Operating Range
Blank
L
4.5V to 5.5V
2.7V to 4.5V
LZ
2.7V to 4.5V and
<1µA Standby Current
Density/Mode
Interface
040
4K, mode 0
C
W
CMOS technology
Total Array write protect
25
SPI
NM
Fairchild Nonvolatile
Memory Prefix
2
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NM25C040 Rev. D.1
Standard Voltage 4.5 ≤ VCC ≤ 5.5V Specifications
Operating Conditions
Absolute Maximum Ratings (Note 1)
Ambient Operating Temperature
NM25C040
Ambient Storage Temperature
-65°C to +150°C
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
All Input or Output Voltage with
Respect to Ground
NM25C040E
NM25C040V
+6.5V to -0.3V
+300°C
Lead Temp. (Soldering, 10 sec.)
ESD Rating
Power Supply (VCC
)
4.5V to 5.5V
2000V
DC and AC Electrical Characteristics 4.5V ≤ VCC ≤ 5.5V (unless otherwise specified)
Symbol
Parameter
Conditions
Min
Max
Units
ICC
ICCSB
IIL
Operating Current
CS = VIL
3
50
mA
µA
µA
µA
V
Standby Current
Input Leakage
CS = VCC
VIN = 0 to VCC
VOUT = GND to VCC
-1
-1
+1
IOL
Output Leakage
+1
VIL
CMOS Input Low Voltage
CMOS Input High Voltage
Output Low Voltage
Output High Voltage
SCK Frequency
-0.3
VCC * 0.3
VCC + 0.3
0.4
VIH
VOL
VOH
fOP
0.7 * VCC
V
IOL = 1.6 mA
IOH = -0.8 mA
V
VCC - 0.8
V
2.1
2.0
2.0
MHz
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
tRI
Input Rise Time
tFI
Input Fall Time
tCLH
tCLL
tCSH
tCSS
tDIS
tHDS
tCSN
tDIN
tHDN
tPD
Clock High Time
Clock Low Time
(Note 2)
(Note 2)
(Note 3)
190
190
240
240
100
90
Min CS High Time
CS Setup Time
Data Setup Time
HOLD Setup Time
CS Hold Time
240
100
90
Data Hold Time
HOLD Hold Time
Output Delay
CL = 200 pF
240
tDH
Output Hold Time
HOLD to Output Low Z
Output Disable Time
HOLD to Output High Z
Write Cycle Time
0
tLZ
100
240
100
10
tDF
CL = 200 pF
1–4 Bytes
tHZ
tWP
Capacitance TA = 25°C, f = 2.1/1 MHz (Note 4)
AC Test Conditions
Output Load
CL = 200 pF
0.1 * VCC – 0.9 * VCC
0.3 * VCC - .07 * VCC
Symbol
COUT
Test
Typ Max Units
Input Pulse Levels
Output Capacitance
Input Capacitance
3
2
8
6
pF
pF
Timing Measurement Reference Level
CIN
Note 1: Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the
device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Note 2: The fOP frequency specification specifies a minimum clock period of 1/fOP. Therefore, for every fOP clock cycle, tCLH + tCLL must be equal to or greater than 1/fOP. For
example, if the 2.1MHz period = 476ns and tCLH = 190ns, tCLL must be 286ns.
Note 3: CS must be brought high for a minimum of tCSH between consecutive instruction cycles.
Note 4: This parameter is periodically sampled and not 100% tested.
3
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NM25C040 Rev. D.1
Low Voltage 2.7V ≤ VCC ≤ 4.5V Specifications
Operating Conditions
Absolute Maximum Ratings (Note 5)
Ambient Storage Temperature
-65°C to +150°C
Ambient Operating Temperature
NM25C040L/LZ
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
All Input or Output Voltage with
Respect to Ground
NM25C040LE/LZE
NM25C040LV
+6.5V to -0.3V
+300°C
Lead Temp. (Soldering, 10 sec.)
ESD Rating
Power Supply (VCC
)
2.7V–4.5V
2000V
DC and AC Electrical Characteristics 2.7V ≤ VCC ≤ 4.5V (unless otherwise specified)
25C040L/LE
25C040LV
25C040LZ/ZE
Symbol
Parameter
Part
Conditions
Min.
Max.
Min Max
Units
ICC
Operating Current
Standby Current
CS = VIL
3
3
mA
ICCSB
L
LZ
CS = VCC
10
1
10
N/A
µA
µA
IIL
Input Leakage
VIN = 0 to VCC
-1
-1
1
1
-1
-1
1
1
µA
µA
V
IOL
Output Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
SCK Frequency
Input Rise Time
Input Fall Time
VOUT = GND to VCC
VIL
-0.3
VCC * 0.3
-0.3
VCC * 0.3
VIH
VOL
VOH
fOP
tRI
VCC * 0.7 VCC + 0.3
VCC * 0.7 VCC + 0.3
V
IOL = 0.8 mA
0.4
0.4
V
IOH = –0.8 mA
VCC - 0.8
VCC - 0.8
V
1.0
1.0
MHz
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
2.0
2.0
tFI
2.0
2.0
tCLH
tCLL
tCSH
tCSS
tDIS
tHDS
tCSN
tDIN
tHDN
tPD
Clock High Time
Clock Low Time
Min. CS High Time
CS Setup Time
(Note 6)
(Note 6)
(Note 7)
410
410
500
500
100
240
500
100
240
500
0
410
410
500
500
100
240
500
100
240
500
0
Data Setup Time
HOLD Setup Time
CS Hold Time
Data Hold Time
HOLD Hold Time
Output Delay
CL = 200 pF
tDH
tLZ
Output Hold Time
HOLD Output Low Z
Output Disable Time
HOLD to Output Hi Z
Write Cycle Time
240
500
240
15
240
500
240
15
tDF
CL = 200 pF
1-4 Bytes
tHZ
tWP
Capacitance TA = 25°C, f = 2.1/1 MHz (Note 8)
AC Test Conditions
Output Load
CL = 200pF
Symbol
COUT
Test
Typ Max Units
Input Pulse Levels
0.1 * VCC - 0.9 * VCC
0.3 * VCC - 0.7 * VCC
Output Capacitance
Input Capacitance
3
2
8
6
pF
pF
Timing Measurement Reference Level
CIN
Note 5: Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Note 6: The fOP frequency specification specifies a minimum clock period of 1/fOP. Therefore, for every fOP clock cycle, tCLH + tCLL must be equal to or greater than 1/fOP. For example,
if the 2.1MHz period = 476ns and tCLH = 190ns, tCLL must be 286ns.
Note 7: CS must be brought high for a minimum of tCSH between consecutive instruction cycles.
Note 8: This parameter is periodically sampled and not 100% tested.
4
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NM25C040 Rev. D.1
AC Test Conditions (Continued)
FIGURE 1. Synchronous Data Timing Diagram
t
V
CSH
IH
CS
V
IL
t
t
CSS
CSN
V
IH
t
t
SCK
SI
CLL
t
CLH
V
IL
t
DIS
DIN
V
IH
V
IL
t
t
DF
t
PD
DH
V
OH
SO
DS012401-3
V
OL
FIGURE 2. HOLD Timing
SCK
t
t
t
t
HDN
HDS
HDN
HDS
HOLD
SO
t
t
LZ
HZ
DS012401-6
FIGURE 3. SPI Serial Interface
MASTER MCU
NM25C040
SI
DATA OUT (MOSI)
DATA IN (MISO)
SERIAL CLOCK (CLK)
SS0
SO
SCK
CS
SPI
SS1
SS2
SS3
SI
CHIP
SO
SCK
CS
SELECTION
SI
SO
SCK
CS
SI
SO
SCK
CS
DS012401-4
5
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NM25C040 Rev. D.1
Functional Description
TABLE 1. Instruction Set
Instruction Instruction
HOLD: The HOLD pin is used in conjunction with the CS to select
the device. Once the device is selected and a serial sequence is
underway, HOLD may be forced low to suspend further serial
communication with the device without resetting the serial se-
quence. Note that HOLD must be brought low while the SCK pin
is low. The device must remain selected during this sequence. To
resume serial communication HOLD is brought high while the
SCK pin is low. The SO pin is at a high impedance state during
HOLD.
Operation
Name
WREN
WRDI
Opcode
00000110
00000100
00000101
00000001
0000A011
Set Write Enable Latch
Reset Write Enable Latch
Read Status Register
Write Status Register
RDSR
WRSR
READ
INVALID OP-CODE: After an invalid code is received, no data is
shifted into the NM25C040, and the SO data output pin remains
high impedance until a new CS falling edge reinitializes the serial
communication. See Figure 5.
Read Data from Memory
Array
WRITE
Note:
0000A010
Write Data to Memory Array
As the NM25C040 requires 9 address bits (4,096 ÷ 8 = 512 bytes = 29), the
FIGURE 5. Invalid Op-Code
9th bit (for R/W instructions) is inputted in the Instruction Set Byte in bit I3. This
convention only applies to 4K SPI protocol.
CS
MASTER: The device that generates the serial clock is desig-
nated as the master. The NM25C040 can never function as a
master.
SI
INVALID CODE
SLAVE: The NM25C040 always operates as a slave as the serial
clock pin is always an input.
SO
TRANSMITTER/RECEIVER: The NM25C040 has separate pins
for data transmission (SO) and reception (SI).
DS012401-7
MSB: The Most Significant Bit is the first bit transmitted and
received.
CHIPSELECT:ThechipisselectedwhenpinCSislow. Whenthe
chip is not selected, data will not be accepted from pin SI, and the
output pin SO is in high impedance.
SERIAL OP-CODE: The first byte transmitted after the chip is
selected with CS going low contains the op-code that defines the
operation to be performed.
PROTOCOL: When connected to the SPI port of a 68HC11
microcontroller, the NM25C040 accepts a clock phase of 0 and a
clockpolarityof0. TheSPIprotocolforthisdevicedefinesthebyte
transmitted on the SI and SO data lines for proper chip operation.
See Figure 4.
FIGURE 4. SPI Protocol
CS
…
SCK
…
SI
Bit 7 Bit 6
Bit 7
Bit 0
Bit 1
SO
…
Bit 0
DS012401-5
Data is clocked in on the positive SCK edge and out on the
negative SCK edge.
6
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NM25C040 Rev. D.1
TABLE 3. Block Write Protection Levels
Functional Description (Continued)
READ SEQUENCE: Reading the memory via the serial SPI link
requiresthefollowingsequence.TheCSlineispulledlowtoselect
the device. The READ op-code (which includes A8) is transmitted
on the SI line followed by the byte address (A7–A0) to be read.
After this is done, data on the SI line becomes don’t care. The data
(D7–D0)attheaddressspecifiedisthenshiftedoutontheSOline.
If only one byte is to be read, the CS line can be pulled back to the
high level. It is possible to continue the READ sequence as the
byte adress is automatically incremented and data will continue to
be shifted out. When the highest address is reached (1FF), the
address counter rolls over to lowest address (000) allowing the
entire memory to be read in one continuous READ cycle. See
Figure 6.
Level
Status Register Bits
Array
Address
Protected
None
BP1
BP0
0
1
2
3
0
0
0
1
1
1
0
1
180-1FF
100-1FF
000-1FF
WRITE ENABLE (WREN): When VCC is applied to the chip, it
“powers up” in the write disable state. Therefore, all programming
modes must be preceded by a WRITE ENABLE (WREN) instruc-
tion. At the completion of a WRITE or WRSR cycle the device is
automatically returned to the write disable state. Note that a
WRITE DISABLE (WRDI) instruction will also return the device to
the write disable state. See Figure 8.
FIGURE 6. Read Sequence
CS
FIGURE 8. Write Enable
Read
Op-Code
Byte
Addr.
CS
SI
SI
WREN Op-Code
Data
n
Data
n+1
Data
n+2
Data
n+3
SO
DS012401-8
READ STATUS REGISTER (RDSR) : The Read Status Register
(RDSR) instruction provides access to the status register is used
to interrogate the READY/BUSY and WRITE ENABLE status of
the chip. Two non-volatile status register bits are used to select
one of four levels of BLOCK WRITE PROTECTION. The status
register format is shown in Table 2.
SO
DS012401-10
WRITE DISABLE (WRDI): To protect against accidental data
disturbance the WRITE DISABLE (WRDI) instruction disables all
programming modes. See Figure 9.
FIGURE 9. Write Disable
TABLE 2. Status Register Format
CS
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
X
X
X
X
BP1
BP0 WEN RDY
SI
WRDI Op-Code
X = Don't Care.
StatusregisterBit0=0(RDY)indicatesthatthedeviceisREADY;
Bit 0 = 1 indicates that a program cycle is in progress. Bit 1 = 0
(WEN) indicates that the device is not WRITE ENABLED; Bit 1 =
1 indicates that the device is WRITE ENABLED. Non-volatile
status register Bits 2 and 3 (BP0 and BP1) indicate the level of
BLOCK WRITE PROTECTION selected. The block write protec-
tion levels and corresponding status register control bits are
shown in Table 3. Note that if a RDSR instruction is executed
during a programming cycle only the RDY bit is valid. All
other bits are 1s. See Figure 7.
SO
DS012401-11
WRITE SEQUENCE: To program the device, the WRITE PRO-
TECT (WP) pin must be held high and two separate instructions
must be executed. The chip must first be write enabled via the
WRITE ENABLE instruction and then a WRITE instruction must
be executed. Moreover, the address of the memory location(s) to
be programmed must be outside the protected address field
selected by the Block Write Protection Level. See Table 3.
FIGURE 7. Read Status
A WRITE command requires the following sequence. The CS line
is pulled low to select the device, then the WRITE op-code (which
includes A8) is transmitted on the SI line followed by the high order
address byte (A10-A8) and the byte address(A7–A0) and the
corresponding data (D7-D0) to be written. Programming will start
after the CS pin is forced back to a high level. Note that the LOW
toHIGHtransitionoftheCSpinmustoccurduringtheSCKlowtime
immediately after clocking in the D0 data bit. See Figure 10.
CS
RDSR
Op-Code
SI
SR Data
MSB…LSB
SO
DS012401-9
7
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NM25C040 Rev. D.1
Functional Description (Continued)
The WRSR command requires the following sequence. The CS
line is pulled low to select the device and then the WRSR op-code
is transmitted on the SI line followed by the data to be pro-
grammed. See Figure 12.
FIGURE 10. Write Sequence
CS
FIGURE 12. Write Status Register
SCK
CS
D2
D1
D0
SI
WRSR
Op-Code
SR Data
xxxxBP1BP0xx
SI
SO
DS012401-12
SO
The READY/BUSY status of the device can be determined by
executing a READ STATUS REGISTER (RDSR) instruction. Bit 0
= 1 indicates that the WRITE cycle is still in progress and Bit 0 =
0 indicates that the WRITE cycle has ended. During the WRITE
programming cycle (Bit 0 = 1) only the READ STATUS REGIS-
TER instruction is enabled.
DS012401-14
Note that the first four bits are don’t care bits followed by BP1 and
BP0 then two additional don’t care bits. Programming will start
after the CS pin is forced back to a high level. As in the WRITE
instruction the LOW to HIGH transition of the CS pin must occur
duringtheSCKlowtimeimmediatelyafterclockinginthelastdon’t
care bit. See Figure 13.
The NM25C040 is capable of a 4 byte PAGE WRITE operation.
Afterreceiptofeachbyteofdatathetwoloworderaddressbitsare
internally incremented by one. The seven high order bits of the
address will remain constant. If the master should transmit more
than 4 bytes of data, the address counter will “roll over,” and the
previously loaded data will be reloaded. See Figure 11.
FIGURE 13. Start WRSR Condition
CS
FIGURE 11. 4 Byte Page Write
SCK
CS
BP0
SI
Write
Op-Code Addr (n)
Byte
Data
(n)
Data
(n + 1)
Data
(n + 2)
Data
(n + 3)
SI
SO
DS012401-15
The READY/BUSY status of the device can be determined by
executing a READ STATUS REGISTER (RDSR) instruction. Bit 0
= 1 indicates that the WRSR cycle is still in progress and Bit 0 =
0 indicates that the WRSR cycle has ended.
SO
DS012401-13
At the completion of a WRITE cycle the device is automatically
returned to the write disable state.
At the completion of a WRITE cycle the device is automatically
returned to the write disable state.
If the device is not WRITE enabled, the device will ignore the
WRITE instruction and return to the standby state when CS is
forced high. A new CS falling edge is required to re-initialize the
serial communication.
WRITE STATUS REGISTER (WRSR): The WRITE STATUS
REGISTER (WRSR) instruction is used to program the non-
volatile status register Bits 2 and 3 (BP0 and BP1). The WRITE
PROTECT (WP) pin must be held high and two separate instruc-
tions must be executed. The chip must first be write enabled via
the WRITE ENABLE instruction and then a WRSR instruction
must be executed.
8
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NM25C040 Rev. D.1
Physical Dimensions inches (millimeters) unless otherwise noted
0.189 - 0.197
(4.800 - 5.004)
8
7
6
5
0.228 - 0.244
0.010
(0.254)
(5.791 - 6.198)
Max.
1
2
3
4
Lead #1
IDENT
30° Typ.
0.150 - 0.157
0.053 - 0.069
(1.346 - 1.753)
(3.810 - 3.988)
0.010 - 0.020
(0.254 - 0.508)
0.004 - 0.010
(0.102 - 0.254)
x 45°
8° Max, Typ.
All leads
Seating
Plane
0.04
0.008 - 0.010
(0.203 - 0.254)
Typ. all leads
(0.102)
All lead tips
0.014
(0.356)
0.016 - 0.050
(0.406 - 1.270)
Typ. All Leads
0.050
(1.270)
Typ
0.014 - 0.020
(0.356 - 0.508)
Typ.
0.008
(0.203)
Typ
Molded Small Out-Line Package (M8)
Package Number M08A
0.373 - 0.400
(9.474 - 10.16)
0.090
(2.286)
8
1
7
0.032 ± 0.005
(0.813 ± 0.127)
8
7
6
5
4
0.092
RAD
DIA
(2.337)
0.250 - 0.005
Pin #1
IDENT
+
Pin #1 IDENT
(6.35 ± 0.127)
Option 1
1
2
3
Option 2
0.280
MIN
0.040
(1.016)
Typ.
(7.112)
0.030
0.145 - 0.200
(3.683 - 5.080)
0.039
(0.991)
MAX
(0.762)
0.300 - 0.320
(7.62 - 8.128)
20° ± 1°
0.130 ± 0.005
(3.302 ± 0.127)
0.125 - 0.140
95° ± 5°
(3.175 - 3.556)
0.065
(1.651)
0.125
(3.175)
DIA
0.020
90° ± 4°
Typ
0.009 - 0.015
(0.508)
Min
(0.229 - 0.381)
NOM
0.018 ± 0.003
(0.457 ± 0.076)
+0.040
-0.015
0.325
0.100 ± 0.010
+1.016
-0.381
8.255
(2.540 ± 0.254)
0.045 ± 0.015
(1.143 ± 0.381)
0.060
(1.524)
0.050
(1.270)
Molded Dual-In-Line Package (N)
Package Number N08E
9
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NM25C040 Rev. D.1
Physical Dimensions inches (millimeters) unless otherwise noted
0.114 - 0.122
(2.90 - 3.10)
8
5
(7.72) Typ
(4.16) Typ
0.246 - 0.256
(6.25 - 6.50)
0.169 - 0.177
(4.30 - 4.50)
(1.78) Typ
(0.42) Typ
0.123 - 0.128
(0.65) Typ
(3.13 - 3.30)
Land pattern recommendation
1
4
Pin #1 IDENT
0.0433
Max
(1.1)
0.0035 - 0.0079
0.002 - 0.006
(0.05 - 0.15)
See detail A
0.0256 (0.65)
Typ.
0.0075 - 0.0098
(0.19 - 0.30)
Gage
plane
0°-8°
DETAIL A
Note: Metal mask option for 16-byte page size.
Typ. Scale: 40X
0.0075 - 0.0098
[0.19 - 0.25]
0.020 - 0.028
[0.50 - 0.70]
Seating
plane
8-Pin Molded TSSOP, JEDEC (MT8)
Package Number MTC08
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Fairchild Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which,
(a)areintendedforsurgicalimplantintothebody,or(b)support
or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant
injury to the user.
2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably ex-
pected to cause the failure of the life support device or system,
or to affect its safety or effectiveness.
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10
www.fairchildsemi.com
NM25C040 Rev. D.1
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