NM25C041 [FAIRCHILD]
4K-Bit Serial Interface CMOS EEPROM (Serial Peripheral Interface (SPI⑩) Synchronous Bus); 4K位串行接口的CMOS EEPROM （串行外设接口（ SPI⑩ ）同步总线）
| 型号： | NM25C041 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 4K-Bit Serial Interface CMOS EEPROM (Serial Peripheral Interface (SPI⑩) Synchronous Bus) |
| 文件： | 总10页 (文件大小：82K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 1999
NM25C041
4K-Bit Serial Interface CMOS EEPROM (Serial
Peripheral Interface (SPI™) Synchronous Bus)
by the Status Register and is described in greater detail within this
datasheet.Inordertopreventspuriousprogramming,theEEPROM
has both a Write Enable command, which is immediately disabled
after each programming operation, and a Write Protect (WP) pin,
which must be pulled HIGH to program.
General Description
The NM25C041 is a 4096-bit MODE 1 SPI (Serial Peripheral
Interface) CMOS EEPROM which is designed for high-reliability
non-volatile data storage applications. The SPI interface features
a byte-wide format (all data is transferred in 8-bit words) to
interfacewiththeMotorola68HC11microprocessor,orequivalent,
at a 2.1MHz clock transfer rate. (This interface is considered the
fastest serial communication method.) This 4-wire SPI interface
allows the end user full EEPROM functionality while keeping pin
count and space requirements low for maximum PC board space
utilization.
Features
■ 2.1 MHz clock rate @ 2.7V to 5.5V
■ 4096 bits organized as 512 x 8
■ Multiple chips on the same 3 wire bus with separate chip
select lines
The SPI interface requires four I/O pins on each EEPROM device:
Chip Select (CS), Clock (SCK), Serial Data In (SI), and Serial Data
Out (SO), as well as 2 other control pins: Write Protect (WP) and
HOLD (HOLD). The Write Protect pin can be used to disable the
Write operation and the HOLD pin is used to interrupt the SI
datastream and place the device in a Hold state during micropro-
cessor instruction generation. Please refer to the following dia-
grams and description for more details.
■ Self-timed programming cycle
■ Simultaneous programming of 1 to 4 bytes at a time
■ Status register can be polled during programming to monitor
RDY/BUSY
■ Both the Write Protect (WP) pin and 'auto-write disable after
programming' provides hardware and software write
protection
■ Block write protect feature to protect against accidental
writes
All programming cycles are completely self-timed and do not
requireanERASE, orsimilarsetup, beforeprogramminganycells.
Programming can be performed in 3 modes, address (byte) write,
page(4addresses/bytes)writeor partial pagewrite. Furthermore,
the EEPROM is provided with 4 levels of write protection wherein
the data, once programmed, cannot be altered. This is controlled
■ Endurance: 1,000,000 data changes
■ Data retention greater than 40 years
■ Packages available: 8-pin DIP and 8-pin SO
Block Diagram
CS
HOLD
SCK
VCC
VSS
Instruction
Decoder
Control Logic
and Clock
WP
Instruction
SI
Generators
Register
Program
Enable
Address
Counter/
Register
High Voltage
Generator
and
Program
Timer
VPP
EEPROM Array
4096 Bits
(512 x 8)
Decoder
1 of 512
Read/Write Amps
Data In/Out Register
8 Bits
Data Out
Buffer
SO
Non-Volatile
Status Register
SPI™ is a trademark of Motorola Corporation.
DS800002-1
1
© 1999 Fairchild Semiconductor Corporation
NM25C041 Rev. D.1
www.fairchildsemi.com
Connection Diagram
Pin Names
Dual-In-Line Package (N)
and SO Package (M8)
CS
SO
Chip Select Input
Serial Data Output
Write Protect
CS
SO
WP
VSS
1
2
3
4
8
7
6
5
VCC
WP
VSS
Ground
HOLD
SCK
SI
SI
Serial Data Input
Serial Clock Input
Suspends Serial Data
Power Supply
SCK
HOLD
VCC
DS800002-2
Top View
Ordering Information
NM 25
C
XX LZ E XX
Letter Description
Package
N
M8
8-pin DIP
8-pin SO
Temp. Range
None
0 to 70°C
V
E
-40 to +125°C
-40 to +85°C
Voltage Operating Range
Blank
L
4.5V to 5.5V
2.7V to 4.5V
LZ
2.7V to 4.5V and
<1µA Standby Current
Density/Mode
Interface
041
C
4K, mode 1
CMOS
SPI
25
NM
Fairchild Non-Volatile
Memory
2
www.fairchildsemi.com
NM25C041 Rev. D.1
Absolute Maximum Ratings (Note 1)
Operating Conditions
Ambient Storage Temperature
-65°C to +150°C
Ambient Operating Temperature
NM25C041
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
All Input or Output Voltages
with Respect to Ground
+6.5V to -0.3V
NM25C041E
NM25C041V
Lead Temperature (Soldering, 10 sec.)
ESD Rating
+300°C
Power Supply (VCC
NM25C041
)
2000V
4.5V to 5.5V
DC and AC Electrical Characteristics 4.5V ≤ VCC ≤ 5.5V
Symbol
Parameter
Conditions
Min
Max
Units
ICC
ICCSB
IIL
Operating Current
CS = VIL
3
mA
µA
µA
µA
V
Standby Current
Input Leakage
CS = VCC
50
VIN = 0 to VCC
VOUT = GND to VCC
-1
-1
1
1
IOL
Output Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
SCK Frequency
Input Rise Time
Input Fall Time
VIL
-0.3
VCC * 0.3
VCC + 0.3
0.4
VIH
VOL
VOH
fOP
0.7 * VCC
V
IOL = 1.6 mA
IOH = -0.8 mA
V
VCC - 0.8
V
2.1
2.0
2.0
MHz
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
tRI
tFI
tCLH
tCLL
tCSH
tCSS
tDIS
tHDS
tCSN
tDIN
tHDN
tPD
Clock High Time
Clock Low Time
Min CS High Time
CS Setup Time
(Note 2)
(Note 2)
(Note 3)
190
190
240
240
100
90
Data Setup Time
HOLD Setup Time
CS Hold Time
240
100
90
Data Hold Time
HOLD Hold Time
Output Delay
CL = 200 pF
240
tDH
Output Hold Time
HOLD to Output Low Z
Output Disable Time
HOLD to Output High Z
Write Cycle Time
0
tLZ
100
240
100
10
tDF
CL = 200 pF
1–4 Bytes
tHZ
tWP
Capacitance (Note 4) TA = 25°C, f = 2.1/1 MHz
AC Test Conditions
Output Load
CL = 200 pF
Symbol
COUT
Test
Typ
Max Units
Input Pulse Levels
0.1 * VCC - 0.9 * VCC
0.3 * VCC - 0.7 * VCC
Output Capacitance
Input Capacitance
3
2
8
6
pF
pF
Timing Measurement Reference Level
CIN
Note 1: Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Note 2: The fOP frequency specification specifies a minimum clock period of 1/fOP. Therefore, for every fOP clock cycle, tCLH + tCLL must be equal to or greater than 1/fOP. For
example, if the 2.1MHz period = 476ns and tCLH = 190ns, tCLL must be 286ns.
Note 3: CS must be brought high for a minimum of tCSH between consecutive instruction cycles.
Note 4: This parameter is periodically sampled and not 100% tested.
3
www.fairchildsemi.com
NM25C041 Rev. D.1
Low Voltage 2.7V ≤ VCC ≤ 4.5V Specifications
Operating Conditions
Absolute Maximum Ratings (Note 5)
Ambient Operating Temperature
NM25C041L/LZ
Ambient Storage Temperature
-65°C to +150°C
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
All Input or Output Voltage with
Respect to Ground
NM25C041LE/LZE
NM25C041LV
+6.5V to -0.3V
+300°C
Lead Temp. (Soldering, 10 sec.)
ESD Rating
Power Supply (VCC
)
2.7V - 4.5V
2000V
DC and AC Electrical Characteristics 2.7V ≤ VCC ≤ 4.5V
25C041L/LE
25C041LV
25C041LZ/LZE
Symbol
Parameter
Conditions
Min.
Max.
Min
Max
Units
ICC
Operating Current
CS = VIL
3
3
mA
ICCSB
Standby Current
CS = VCC
µA
L
LZ
10
1
10
N/A
IIL
Input Leakage
VIN = 0 to VCC
-1
-1
1
1
-1
-1
1
1
µA
µA
V
IOL
Output Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
SCK Frequency
Input Rise Time
Input Fall Time
VOUT = GND to VCC
VIL
-0.3
VCC * 0.3
-0.3
VCC * 0.3
VIH
VOL
VOH
fOP
tRI
0.7 * VCC VCC + 0.3
0.7 * VCC VCC + 0.3
V
IOL = 0.8 mA
0.4
0.4
V
IOH = –0.8 mA
VCC - 0.8
VCC - 0.8
V
1.0
1.0
MHz
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
2.0
2.0
tFI
2.0
2.0
tCLH
tCLL
tCSH
tCSS
tDIS
tHDS
tCSN
tDIN
tHDN
tPD
Clock High Time
Clock Low Time
Min. CS High Time
CS Setup Time
(Note 6)
(Note 6)
(Note 7)
410
410
500
500
100
240
500
100
240
500
0
410
410
500
500
100
240
500
100
240
500
0
Data Setup Time
HOLD Setup Time
CS Hold Time
Data Hold Time
HOLD Hold Time
Output Delay
tDH
tLZ
Output Hold Time
HOLD Output Low Z
Output Disable Time
HOLD to Output Hi Z
Write Cycle Time
240
500
240
15
240
500
240
15
tDF
tHZ
tWP
1-4 Bytes
Capacitance TA = 25°C, f = 2.1/1 MHz (Note 8)
AC Test Conditions
Output Load
CL = 200 pF
Symbol
COUT
Test
Typ Max Units
Input Pulse Levels
0.1 * VCC - 0.9 * VCC
Output Capacitance
Input Capacitance
3
2
8
6
pF
pF
Timing Measurement Reference Level
0.3 * VCC - 0.7 * VCC
CIN
Note 5: Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the
device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Note 6 : The fOP frequency specification specifies a minimum clock period of 1/fOP. Therefore, for every fOP clock cycle, tCLH + tCLL must be equal to or greater than 1/fOP. For
example, if the 2.1MHz period = 476ns and tCLH = 190ns, tCLL must be 286ns.
Note 7: CS must be brought high for a minimum of tCSH between consecutive instruction cycles.
Note 8: This parameter is periodically sampled and not 100% tested.
4
www.fairchildsemi.com
NM25C041 Rev. D.1
AC Test Conditions (Continued)
FIGURE 1. Synchronous Data Timing
VIH
tCSH
CS
VIL
tCSS
tCSN
VIH
tCLL
tDIN
tCLH
tDIS
SCK
VIL
VIH
SI
VIL
tPD
tPD
tDF
VOH
SO
HI-Z
HI-Z
VOL
DS800002-4
FIGURE 2. HOLD Timing
SCK
HOLD
SO
tHDS
tHDN
tHDS
tHDN
tHZ
tLZ
DS800002-6
5
www.fairchildsemi.com
NM25C041 Rev. D.1
Functional Description
TABLE 1. Op Codes Table
Instruction Instruction
As an additional protection against data corruption, the device is
designed so that, if an invalid opcode is received, the device will
not shift any further data into the SI latches and SO will remain tri-
stated. Inthiscase, CSmustagainbebroughtHIGHtore-initialize
the device and a new opcode re-entered. See Figure 4.
Operation
Name
WREN
WRDI
Opcode
0000 0110
0000 0100
0000 0101
0000 0001
0000 A011
Set Write Enable Latch
Reset Write Enable Latch
Read Status Register
Write Status Register
FIGURE 4. Invalid Op-Code
CS
RDSR
WRSR
READ
SI
INVALID OP-CODE
Read Data from Memory
Array
SO
DS800002-7
WRITE
0000 A010
Write Data to Memory
Array
READ STATUS REGISTER (RDSR): The Read Status Register
(RDSR) instruction provides access to the status register which is
used to interrogate the READY/BUSY and WRITE ENABLE
status of the chip. Two non-volatile status register bits are used to
select one of four levels of BLOCK WRITE PROTECTION. The
status register format is shown in Table 2.
Note:
As the NM25C040 requires 9 address bits (4,096 ÷ 8 = 512 bytes = 29), the
9th bit (for R/W instructions) is inputted in the Instruction Set Byte in bit I3. This
convention only applies to 4K SPI protocol.
The NM25C041 SPI device uses a CS functionality, so the device
is selected when CS is LOW (CS is to be held HIGH during
'standby' periods and between instruction sets). As stated above,
the SPI protocol defines this as a MODE 1 part, with a CLOCK
PHASE 1 and CLOCK POLARITY 0. This means that the part is
active with CS = 0 (VIL), all INPUT data is latched into the device
on the RISING edge of SCK and all OUTPUT data is clocked out
on the FALLING edge of SCK.
READ SEQUENCE: Reading the memory via the SPI link re-
quires the following sequence. The CS line is pulled low to select
the device. The READ op-code (which includes A8) is transmitted
on the SI line followed by the byte address (A7–A0) to be read.
After this is done, data on the SI line becomes don’t care. The data
(D7–D0)attheaddressspecifiedisthenshiftedoutontheSOline.
If only one byte is to be read, the CS line can be pulled back to the
high level. It is possible to continue the READ sequence as the
byte address is automatically incremented and data will continue
to be shifted out. When the highest address is reached (1FF), the
address counter rolls over to lowest address (000) allowing the
entire memory to be read in one continuous READ cycle. See
Figure 5.
FIGURE 3. SPI Protocol
CS
…
SCK
…
SI
Bit 7
Bit 7
Bit 6
Bit 6
Bit 1
Bit 1
Bit 0
Bit 0
FIGURE 5. Read Sequence
…
SO
DS800002-5
CS
The HOLD pin operation is used when the device is selected (CS
LOW) and the application requires that the SI datastream be
stopped and then restarted. The HOLD pin allows a fully 'static'
operation, wherin the device may be put on HOLD by bringing the
HOLD pin LOW (VIL). During the HOLD state, SCK must be HIGH
and CS must remain LOW (device selected). In order to resume
EEPROM serial communication, HOLD must be again brought
HIGH and the SCK/SI signals resumed. During the HOLD state,
SO is tri-stated (high impedance).
READ
OP-CODE
BYTE
ADDR (n)
SI
DATA
(n)
DATA
(n+1)
DATA
(n+2)
DATA
(n+3)
SO
DS800002-8
6
www.fairchildsemi.com
NM25C041 Rev. D.1
Functional Description (Continued)
WRITE DISABLE (WRDI): To protect against accidental data
disturbance the WRITE DISABLE (WRDI) instruction disables all
programming modes. The WRITE DISABLE instruction is inde-
pendent of the status of the WP pin. See Figure 8.
TABLE 2. Status Register Format
Bit
7
Bit Bit
Bit Bit
Bit Bit Bit
2
6
5
4
3
1
0
X
X
X
X
BP1
BP0 WEN RDY
FIGURE 8. Write Disable
X = Don't Care
CS
StatusregisterBit0=0(RDY)indicatesthatthedeviceisREADY;
Bit 0 = 1 indicates that a program cycle is in progress. Bit 1 = 0
(WEN) indicates that the device is not WRITE ENABLED; Bit 1 =
1 indicates that the device is WRITE ENABLED. Non-volatile
status register Bits 2 and 3 (BP0 and BP1) indicate the level of
BLOCK WRITE PROTECTION selected. The block write protec-
tion levels and corresponding status register control bits are
shown in Table 3. Note that if a RDSR instruction is executed
during a programming cycle only the RDY bit is valid. All
other bits are 1s. See Figure 6.
SI
WRDI OP-CODE
SO
DS800002-11
WRITE SEQUENCE: To program the device the WRITE PRO-
TECT (WP) pin must be held high and two separate instructions
must be executed. The chip must first be write enabled via the
WRITE ENABLE instruction and then a WRITE instruction must
be executed. Moreover, the address of the memory location(s) to
be programmed must be outside the protected address field
selected by the Block Write Protection Level. See Table 3.
TABLE 3. Block Write Protection Levels
Level
Status Register Bits
Array
A WRITE command requires the following sequence. The CS line
is pulled low to select the device, then the WRITE op-code (which
includes A8) is transmitted on the SI line followed by the byte
address (A7–A0) and the corresponding pro-data (D7–D0) to be
programmed. Programming will start after the CS pin is forced
back to a high level. Note that the LOW to HIGH transition of the
CS pin must occur during the SCK low time immediately after
clocking in the D0 data bit. The READY/BUSY status of the device
can be determined by executing a READ STATUS REGISTER
(RDSR) instruction. Bit 0 = 1 indicates that the WRITE cycle is still
in progress and Bit 0 = 0 indicates that the WRITE cycle has
ended. During the WRITE programming cycle (Bit 0 = 1) only the
READ STATUS REGISTER instruction is enabled.
Address
Protected
BP1
BP0
0
1
2
3
0
0
1
1
0
1
0
1
None
180–1FF
100–1FF
000–1FF
FIGURE 6. Read Status
CS
RDSR
OP-CODE
SI
FIGURE 9. Start WRITE Condition
CS
SR_DATA
MSB...LSB
SO
SCK
DS800002-9
SI
D2
D1
D0
WRITE ENABLE (WREN): When VCC is applied to the chip, it
“powers up” in the write disable state. Therefore, all modes must
be preceded by a WRITE ENABLE (WREN) instruction. Addition-
ally the WP pin must be held high during a WRITE ENABLE
instruction. At the completion of a WRITE or WRSR cycle the
device is automatically turned to the write disable state. Note that
a WRITE DISABLE (WRDI) instruction or forcing the WP pin low
will also return the device to the write disable state. See Figure 7.
SO
DS800002-12
FIGURE 7. Write Enable
CS
SI
WREN OP-CODE
SO
DS800002-10
7
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NM25C041 Rev. D.1
Functional Description (Continued)
Note that the first four bits are don’t care bits followed by BP1 and
BP0 then two additional don’t care bits. Programming will start
after the CS pin is forced back to a high level. As in the WRITE
instruction the LOW to HIGH transition of the CS pin must occur
duringtheSCKlowtimeimmediatelyafterclockinginthelastdon’t
care bit. See Figure 12.
The NM25C041 is capable of a four byte PAGE WRITE operation.
Afterreceiptofeachbyteofdatathetwoloworderaddressbitsare
internally incremented by one. The seven high order bits of the
address will remain constant. If the master should transmit more
than four bytes of data, the address counter will “roll over”, and the
previously loaded data will be reloaded. See Figure 10.
FIGURE 12. Start WRSR Condition
FIGURE 10. 4 Page Byte Write
CS
CS
tCSN
WRITE
OP-CODE
BYTE
ADDR(n)
DATA
(n)
DATA
(n+1)
DATA
(n+2)
DATA
(n+3)
SI
SCK
tDIS
tDIN
SO
SI
BP0
DS800002-13
SO
At the completion of a WRITE cycle the device is automatically
returned to the write disable state.
DS800002-15
The READY/BUSY status of the device can be determined by
executing a READ STATUS REGISTER (RDSR) instruction. Bit 0
= 1 indicates that the WRSR cycle is still in progress and Bit 0 =
0 indicates that the WRSR cycle has ended.
If the WP pin is forced low or the device is not WRITE enabled, the
device will ignore the WRITE instruction and return to the standby
state when CS is forced high. A new CS falling edge is required to
re-initialize the serial communication.
At the completion of a WRSR cycle the device is automatically
returned to the write disable state.
WRITE STATUS REGISTER (WRSR): The WRITE STATUS
REGISTER (WRSR) instruction is used to program the non-
volatile status register Bits 2 and 3 (BP0 and BP1). As in the
WRITE mode the WRITE PROTECT (WP) pin must be held high
and two separate instructions must be executed. The chip must
first be write enabled via the WRITE ENABLE instruction and then
a WRSR instruction must be executed.
The WRSR command requires the following sequence. The CS
line is pulled low to select the device and then the WRSR op-code
istransmittedontheSIlinefollowedbythedatatobeprogrammed
(see Figure 11).
FIGURE 11. Write Status Register
CS
WRSR
OP-CODE
SR_DATA
XXXXBP1BP0XX
SI
SO
DS800002-14
8
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NM25C041 Rev. D.1
Physical Dimensions inches (millimeters) unless otherwise noted
0.189 - 0.197
(4.800 - 5.004)
8
7
6
3
5
4
0.228 - 0.244
(5.791 - 6.198)
1
2
Lead #1
IDENT
0.150 - 0.157
0.053 - 0.069
(1.346 - 1.753)
(3.810 - 3.988)
0.010 - 0.020
(0.254 - 0.508)
0.004 - 0.010
(0.102 - 0.254)
x 45°
8° Max, Typ.
All leads
Seating
Plane
0.04
0.0075 - 0.0098
(0.190 - 0.249)
Typ. All Leads
(0.102)
All lead tips
0.014
(0.356)
0.016 - 0.050
(0.406 - 1.270)
Typ. All Leads
0.050
(1.270)
Typ
0.014 - 0.020
(0.356 - 0.508)
Typ.
Molded Small Out-Line Package (M8)
Order Number NM25C041M8
Package Number M08A
9
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NM25C041 Rev. D.1
Physical Dimensions inches (millimeters) unless otherwise noted
0.373 - 0.400
(9.474 - 10.16)
0.090
(2.286)
8
7
0.032 ± 0.005
(0.813 ± 0.127)
8
7
6
5
4
0.092
(2.337)
RAD
DIA
0.250 - 0.005
Pin #1
IDENT
+
Pin #1 IDENT
(6.35 ± 0.127)
1
Option 1
1
2
3
Option 2
0.280
MIN
0.040
(1.016)
Typ.
(7.112)
0.030
0.145 - 0.200
(3.683 - 5.080)
0.039
(0.991)
MAX
(0.762)
0.300 - 0.320
(7.62 - 8.128)
20° ± 1°
0.130 ± 0.005
(3.302 ± 0.127)
0.125 - 0.140
95° ± 5°
(3.175 - 3.556)
0.065
(1.651)
0.125
(3.175)
DIA
0.020
90° ± 4°
Typ
0.009 - 0.015
(0.229 - 0.381)
(0.508)
Min
0.018 ± 0.003
(0.457 ± 0.076)
NOM
+0.040
-0.015
0.325
0.100 ± 0.010
+1.016
-0.381
8.255
(2.540 ± 0.254)
0.045 ± 0.015
(1.143 ± 0.381)
0.060
(1.524)
0.050
(1.270)
Molded Dual-In-Line Package (N)
Order Number NM25C041N
Package Number N08E
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approval of the President of Fairchild Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which,
(a)areintendedforsurgicalimplantintothebody,or(b)support
or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant
injury to the user.
2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably ex-
pected to cause the failure of the life support device or system,
or to affect its safety or effectiveness.
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68 Mody Road, Tsimshatsui East
Kowloon. Hong Kong
Tel; +852-2722-8338
Fax: +852-2722-8383
4F, Natsume Bldg.
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+49 (0) 8141-6102-0
+44 (0) 1793-856856
+33 (0) 1-6930-3696
+39 (0) 2-249111-1
2-18-6, Yushima, Bunkyo-ku
Tokyo, 113-0034 Japan
Tel: 81-3-3818-8840
Fax: 81-3-3818-8841
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
10
www.fairchildsemi.com
NM25C041 Rev. D.1
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