NM27LV010TE250 [FAIRCHILD]

1,048,576-Bit (128k x 8) Low Voltage EPROM; 1,048,576位（ 128K ×8 ）低电压EPROM


型号：	NM27LV010TE250
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	1,048,576-Bit (128k x 8) Low Voltage EPROM 1,048,576位（ 128K ×8 ）低电压EPROM 存储内存集成电路光电二极管可编程只读存储器 OTP只读存储器电动程控只读存储器
文件：	总10页 (文件大小：104K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

July 1998

NM27LV010

1,048,576-Bit (128k x 8) Low Voltage EPROM

General Description

Features

The NM27LV010 is a high performance Low Voltage Electrically

Programmable Read Only Memory. It is manufactured using

Fairchild’s AMG™ EPROM technology. This technology allows

the part to operate at speeds as fast as 200 ns.

■ 3.0V to 3.6V operation

■ 200 ns access time

■ Low current operation

—8 mA I_CCactive current @ 5 MHz (typ.)

—20µA I_CCstandby current @ 5 MHz (typ.)

This Low Voltage and Low Power EPROM is designed with power

sensitive hand held and portable battery products in mind. This

allows for code storage of firmware for applications like notebook

computers, palm top computers, cellular phones, and HDD.

■ Ultra low power operation

—66 µW standby power @ 3.3V

—50 mW active power @ 3.3V

Small outline packages are just as critical to portable applications

as Low Voltage and Low Power.

■ Surface mount package options|

—32-pin TSOP

—32-pin PLCC

The NM27LV010 is one member of Fairchild’s growing Low

Voltage product Family.

Block Diagram

Data Outputs O - O

GND

PGM

Output Enable,

Chip Enable &

Program Logic

Output

Buffers

Decoder

1,048,576-Bit

Cell Matrix

- A

Address

Inputs

Decoder

DS011377-1

AMG™ is a trademark of WSI, Incorporated.

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Connection Diagrams

PLCC Pin Configuration

TSOP Pin Configuration

32 OE

30 CE

1 32 31 30

PGM

8 x 20 MM

TSOP

14 15 16 17 18 19 20

DS011377-6

DS011377-2

Top View

Commercial Temperature Range

Industrial Temperature Range

(0°C to +70°C) V_CC= 3.3 ± 0.3

(-40°C to +85°C) V_CC= 3.3 ± 0.3

Parameter/Order Number Access Time (ns)

NM27LV010 V, T 200

NM27LV010 V, T 250

200

250

NM27LV010 VE, TE

200

250

Package Types: NM27LV010 V, T

V = PLCC

Pin Names

A0–A16

Addresses

Chip Enable

Output Enable

Outputs

T = TSOP

•

All packages conform to the JEDEC standard.

All versions are guaranteed to function for slower speeds.

O0–O7

PGM

Consult the Fairchild Sales office on new released products

and packages.

Program

•

Consult the Fairchild representative for custom products for

your specific application.

Don’t Care (During Read)

Programming Voltage

V_PP

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All Output Voltages with

V_CC+ 1.0V

to GND - 0.6V

Absolute Maximum Ratings (Note 1)

Respect to Ground (Note 10)

Storage Temperature

-65°C to +150°C

Operating Range

All Input Voltages except A9 with

Respect to Ground (Note 10)

-0.6V to +7V

-0.6V to +14V

Range

Commercial

Industrial

Temperature

0°C to +70°C

V_CCTolerance

V_PPand A9 with Respect to Ground

3.3V

±0.3V

V_CCSupply Voltage with

-40°C to +85°C

Respect to Ground

-0.6V to +7V

>2000V

ESD Protection

DC Electrical Characteristics Over Operating Range with V_PP= V_CC

Symbol

V_IL

Parameter

Test Conditions

Min

-0.3

2.0

Max

Units

Input Low Level

0.7

V_CC+ 0.3

0.4

V_IH

Input High Level

V_OL1

V_OH1

V_OL2

V_OH2

I_SB1

Output Low Voltage (TTL)

Output High Voltage (TTL)

Output Low Voltage

I_OL= 2.0 mA

I_OH= -2.0 mA

I_OL= 100 µA

2.4

0.2

Output High Voltage (CMOS)

I_OH= -100 µA

CE = V_CC± 0.3V

V_CC- 0.3

V_CCStandby Current

(CMOS)

µA

I_SB2

I_CC

V_CCStandby Current (TTL)

V_CCActive Current

CE = V_IH

100

µA

CE = OE = V_IL,

f = 5 MHz

I/O = 0 µA

I_PP

V_PP

I_LI

V_PPSupply Current

V_PPRead Voltage

V_PP= V_CC

V_CC

µA

V_CC- 0.7

Input Load Current

Output Leakage Current

V_IN= 3.0V or GND

V_OUT= 3.0V or GND

µA

I_LO

-1

AC Electrical Characteristics Over Operating Range with V_PP= V_CC

Symbol

Parameter

200

250

Units

Min

Max

200

Min

Max

250

t_ACC

t_CE

Address to Output Delay

CE to Output Delay

t_OE

OE to Output Delay

t_DF

Output Disable to Output Float

(Note 2)

t_OH

(Note 2)

Output Hold from Addresses,

CE or OE , Whichever

Occurred First

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Capacitance (Note 2) T_A= +25°C, 1 = 1 MHz

Symbol

C_IN

Parameter

Input Capacitance

Output Capacitance

Conditions

V_IN= 0V

Typ

Max Units

C_OUT

V_OUT= 0V

AC Test Conditions

Output Load

1 TTL Gate and C_L= 100 pF (Note 8)

Input Rise and Fall Times

Input Pulse Levels

≤5 ns

0.45V to 2.4V

Timing Measurement Reference Level

Inputs

Outputs

0.8V and 2V

AC Waveforms (Note 6) , (Note 7) , and (Note 9)

2.0V

ADDRESS

Address Valid

0.8V

2.0V

0.8V

(Note 2, 4, 5)

2.0V

0.8V

(Note 3)

(Note 2, 4, 5)

2.0V

0.8V

Hi-Z

Valid Output

OUTPUT

ACC

(Note 3)

DS011377-3

Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of

the device at these or any other conditions above those indicated in the operations sections of this specification is not implied. Exposure to absolute maximum rating conditions

for extended periods may affect device reliability.

Note 2: This parameter is only sampled and is not 100% tested.

Note 3: OE may be delayed up to t_ACC- t_CEafter the falling edge of CE without impacting t_ACC

Note 4: The t_DFand t_CFcompare level is determined as follows:

High to TRI-STATE^®, the measured V_OH1(DC) - 0.10V;

Low to TRI-STATE, the measured V_OL1(DC) + 0.10V.

Note 5: TRI-STATE may be attained using OE or CE .

Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.2 µF ceramic capacitor be used on every device

between V_CCand GND.

Note 7: The outputs must be restricted to V_CC+ 1.0V to avoid latch-up and device damage.

Note 8: 1 TTL Gate: I_OL= 1.6 mA, I_OH= -400 µA.

C_L: 100pF includes fixture capacitance.

Note 9: V_PPmay be connected to V_CCexcept during programming.

Note 10: Inputs and outputs can undershoot to -2.0V for 20 ns Max.

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Programming Characteristics (Note 11), (Note 12), (Note 13) and (Note 14)

Symbol

t_AS

Parameter

Address Setup Time

OE Setup Time

Conditions

Min

Typ

Max

Units

µs

t_OES

t_CES

t_DS

µs

CE Setup Time

µs

Data Setup Time

V_PPSetup Time

µs

t_VPS

t_VCS

t_AH

µs

V_CCSetup Time

Address Hold Time

Data Hold Time

µs

t_DH

µs

t_DF

Output Enable to Output

Float Delay

CE/PGM = V_IL

t_PW

t_OE

I_PP

Program Pulse Width

Data Valid from OE

105

100

µs

CE/PGM = V_IL

V_PPSupply Current

during Programming Pulse

I_CC

T_A

V_CCSupply Current

°C

Temperature Ambient

Power Supply Voltage

Programming Supply Voltage

Input Rise, Fall Time

6.25

12.5

6.5

V_CC

V_PP

t_FR

6.75

13.0

12.75

V_IL

Input Low Voltage

0.0

4.0

0.45

V_IH

t_IN

Input High Voltage

2.4

0.8

Input Timing Reference Voltage

Output Timing Reference Voltage

2.0

t_OUT

Programming Waveform (Note 13)

Program

Program Verify

2.0V

Addresses

0.8V

Address N

2.0V

0.8V

Hi-Z

Data In Stable

Data Out Valid

ADD

Data

ADD

6.25V

VCS

VPS

12.75V

CES

PGM

2.0V

0.8V

OES

2.0V

0.8V

DS011377-4

Note 11: Fairchild’s standard product warranty applies to devices programmed to specifications described herein.

Note 12: V_CCmust be applied simultaneously or before V_PPand removed simultaneously or after V_PP. The EPROM must not be inserted into or removedfrom a board with

voltage applied to V_PPor V_CC

Note 13: The maximum absolute allowable voltage which may be applied to the V_PPpin during programming is 14V. Care must be taken when switching the V_PPsupply to

prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 µF capacitor is required across V_PP, V_CCto GND to suppress spurious voltage transients

which may damage the device.

Note 14: During power up the PGM pin must be brought high (≥ V_IH) either coincident with or before power is applied to V_PP

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LV Turbo Programming Algorithm Flow Chart

V_CC= 6.5V V_PP= 12.75V

n = 0

ADDRESS = FIRST LOCATION

PROGRAM ONE 50µs PULSE

INCREMENT n

YES

FAIL

DEVICE

FAILED

VERIFY

BYTE

n = 10?

PASS

INCREMENT

ADDRESS

n = 0

LAST

ADDRESS

YES

ADDRESS = FIRST LOCATION

FAIL

VERIFY

BYTE

PASS

PROGRAM ONE

50 µs

INCREMENT

ADDRESS

PULSE

LAST

ADDRESS

YES

CHECK ALL BYTES

1ST: V_CC= V_PP= 5.0V

2ND: V_CC= V_PP= 3.0V

DS011377-5

Note:

The standard National Semiconductor algorithm may also be used but it will have longer programming time.

FIGURE 1.

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0.1 µF capacitor be placed across V_PPand V_CCto ground to

suppress spurious voltage transients which may damage the

device. The data to be programmed is applied 8 bits in parallel to

the data output pins. The levels required for the address and data

inputs are TTL.

Functional Description

DEVICE OPERATION

The six modes of operation of the EPROM are listed in Table 1. It

should be noted that all inputs for the six modes are at TTL levels.

The power supplies required are V_CCand V_PP. The V_PPpower

supply must be at 12.75V during the three programming modes,

and must be at 3.3V in the other three modes. The V_CCpower

supply must be at 6.5V during the three programming modes, and

at 3.3V in the other three modes.

Whentheaddressanddataarestable,anactivelow,TTLprogram

pulse is applied to the PGM input. A program pulse must be

applied at each address location to be programmed. The EPROM

is programmed with the LV Turbo Programming Algorithm shown

in Figure 1. Each Address is programmed with a series of 50 µs

pulses until it verifies good, up to a maximum of 10 pulses. Most

memorycellswillprogramwithasingle50µspulse.(Thestandard

National Semiconductor Algorithm may also be used, but it will

have longer programming time.)

Read Mode

The EPROM has two control functions, both of which must be

logically active in order to obtain data at the outputs. Chip Enable

(CE) is the power control and should be used for device selection.

Output Enable (OE) is the output control and should be used to

gate data to the output pins, independent of device selection.

The EPROM must not be programmed with a DC signal applied to

the PGM input.

Assuming that addresses are stable, address access time (t_ACC

is equal to the delay from CE to output (t_CE). Data is available at

the outputs t_OEafter the falling edge of OE, assuming that CE has

)

Programming multiple EPROM in parallel with the same data can

be easily accomplished due to the simplicity of the programming

requirements. Like inputs of the parallel EPROM may be con-

nected together when they are programmed with the same data.

A low level TTL pulse applied to the PGM input programs the

paralleled EPROM.

been low and addresses have been stable for at least t_ACC–t_OE

Standby Mode

The EPROM has a standby mode which reduces the active power

dissipation by over 99%, from 50 mW to 0.17 mW. The EPROM

is placed in the standby mode by applying a CMOS high signal to

the CE input. When in standby mode, the outputs are in a high

impedance state, independent of the OE input.

Program Inhibit

Programming multiple EPROM’s in parallel with different data is

also easily accomplished. Except for CE, all like inputs (including

OE and PGM) of the parallel EPROM may be common. A TTL low

level program pulse applied to an EPROM’s PGM input with CE at

Output Disable

_ILand V_PPat 12.75V will program that EPROM. A TTL high level

CE input inhibits the other EPROM’s from being programmed.

The EPROM is placed in output disable by applying a TTL high

signal to the OE input. When in output disable all circuitry is

enabled, except the outputs are in a high impedance state (TRI-

STATE).

Program Verify

Averifyshouldbeperformedontheprogrammedbitstodetermine

whether they were correctly programmed. The verify may be

performed with V_PPat 6.25V. V_PPmust be at V_CC, except during

programming and program verify.

Output OR-Tying

Because the EPROM is usually used in larger memory arrays,

Fairchild has provided a 2-line control function that accommo-

dates this use of multiple memory connections. The 2-line control

function allows for:

AFTER PROGRAMMING

Opaque labels should be placed over the EPROM window to

prevent unintentional erasure. Covering the window will also

preventtemporaryfunctionalfailureduetothegenerationof photo

currents.

1. the lowest possible memory power dissipation, and

2. complete assurance that output bus contention will not

occur.

MANUFACTURER’S IDENTIFICATION CODE

To most efficiently use these two control lines, it is recommended

that CE be decoded and used as the primary device selecting

function, while OE be made a common connection to all devices

in the array and connected to the READ line from the system

control bus. This assures that all deselected memory devices are

in their low power standby modes and that the output pins are

active only when data is desired from a particular memory device.

The EPROM has a manufacturer’s identification code to aid in

programming. When the device is inserted in an EPROM pro-

grammer socket, the programmer reads the code and then

automatically calls up the specific programming algorithm for the

part. This automatic programming control is only possible with

programmers which have the capability of reading the code.

The Manufacturer’s Identification code, shown in Table 2, specifi-

cally identifies the manufacturer and device type. The code for the

NM27LV010 is “8F86”, where “8F” designates that it is made by

Fairchild Semiconductor, and “86” designates a 1 Megabit (128k

x 8) part.

Programming

CAUTION:Exceeding14Vonpin1(V_PP)willdamagetheEPROM.

Initially, and after each erasure, all bits of the EPROM are in the

“1’s” state. Data is introduced by selectively programming “0’s”

into the desired bit locations. Although only “0’s” will be pro-

grammed, both “1’s” and “0’s” can be presented in the data word.

The only way to change a “0” to a “1” is by ultraviolet light erasure.

The code is accessed by applying 12V ±0.5V to address pin A9.

Addresses A1–A8, A10–A16, and all control pins are held at V_IL.

Address pin A0 is held at V_ILfor the manufacturer’s code, and held

at V_IHfor the device code. The code is read on the lower eight data

pins, O0–07. Proper code access is only guaranteed at 25°C ±

5°C.

The EPROM is in the programming mode when the V_PPpower

supply is at 12.75V and OE is at V_IH. It is required that at least a

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ring. Incomplete erasure will cause symptoms that can be mis-

leading. Programmers, components, and even system designs

have been erroneously suspected when incomplete erasure was

the problem.

Functional Description (Continued)

ERASURE CHARACTERISTICS

The erasure characteristics of the device are such that erasure

begins to occur when exposed to light with wavelengths shorter

than approximately 4000 Angstroms (Å). It should be noted that

sunlight and certain types of fluorescent lamps have wavelengths

in the 3000Å – 4000Å range.

SYSTEM CONSIDERATION

The power switching characteristics of EPROMs require careful

decoupling of the devices. The supply current, I_CC, has three

segments that are of interest to the system designer: the standby

current level, the active current level, and the transient current

peaks that are produced by voltage transitions on input pins. The

magnitude of these transient current peaks is dependent on the

output capacitance loading of the device. The associated V_CC

transient voltage peaks can be suppressed by properly selected

decoupling capacitors. It is recommended that at least a 0.1 µF

ceramic capacitor be used on every device between V_CCand

GND. This should be a high frequency capacitor of low inherent

inductance. In addition, at least a 4.7 µF bulk electrolytic capacitor

shouldbeusedbetweenV_CCandGNDforeacheightdevices.The

bulk capacitor should be located near where the power supply is

connected to the array. The purpose of the bulk capacitor is to

overcome the voltage drop caused by the inductive effects of the

PC board traces.

The recommended erasure procedure for the EPROM is expo-

sure to short wave ultraviolet light which has a wavelength of

2537Å. Theintegrateddose(i.e., UVintensityxexposuretime)for

erasure should be a minimum of 30W-sec/cm².

The EPROM should be placed within 1 inch of the lamp tubes

during erasure. Some lamps have a filter on their tubes which

should be removed before erasure.

Anerasuresystemshouldbecalibratedperiodically. Thedistance

fromlamptodeviceshouldbemaintainedatoneinch.Theerasure

time increases as the square of the distance from the lamp (if

distance is doubled the erasure time increases by factor of 4).

Lamps lose intensity as they age. When a lamp has aged, the

system should be checked to make certain full erasure is occur-

Mode Selection

The modes of operation of the NM27LV010 are listed in Table 1. A single 3.3V power supply is required in the read mode. All inputs are

TTL levels except for V_PPand A9 for device signature.

TABLE 1. Modes Selection

Pins

PGM

V_PP

V_CC

Outputs

Mode

Read

V_IL

X (Note 15)

V_IH

V_IL

V_IH

V_CC

3.3V

D_OUT

High Z

D_IN

Output Disable

Standby

V_CC

3.3V

Programming

Program Verify

Program Inhibit

V_IL

V_IH

V_IL

V_IH

V_IL

V_IH

12.75V

6.25V

12.75V

6.25V

V_IL

D_OUT

V_IH

High Z

Note 15: X can be V_ILor V_IH

TABLE 2. Manufacturer’s Identification Code

Pins

Hex

(12)

(26)

(21)

(20)

(19)

(18)

(17)

(15)

(14)

(13)

Data

Manufacturer Code

Device Code

V_IL

V_IH

12V

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Physical Dimensions inches (millimeters) unless otherwise noted

20.0 ± 0.2

0.96 - 1.06

0.5

0.150±0.08

(Leadframe

Thickness)

0.15-0.25 TYP

18.4 ± 0.1

0.10

See Detail A

1.27 MAX

0°-5°

0-0.25

0.4-0.6

DETAIL A

Typical

32-Lead TSOP Package (T)

Order Number NM27LV010TXXX

Package Number MBH32A

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Physical Dimensions inches (millimeters) unless otherwise noted

0.485-0.495

[12.32-12.57]

D-E

0.007[0.18]

0.449-0.453

[11.40-11.51]

-A-

-H-

Base

Plane

0.106-0.112

[2.69-2.84]

0.045

[1.143]

D-E

0.007[0.18]

0.002[0.05]

0.023-0.029

[0.58-0.74]

0.000-0.010

[0.00-0.25]

Polished Optional

0.015

[0.38]

Min Typ

-D-

60°

0.490-0530

[12.45-13.46]

0.400

[10.16]

0.549-0.553

[13.94-14.05]

(

)

-G-

0.541-0.545

[13.74-13-84]

D-E, F-G

-B-

0.015[0.38]

0.585-0.595

[14.86-15.11]

-F-

0.013-0.021

[0.33-0.53]

TYP

0.050

See detail A

-E-

0.002[0.05]

0.007[0.18]

-J-

D-E, F-G

0.007[0.18]

F-G

0.078-0.095

[1.98-2.41]

0.123-0.140

[3.12-3.56]

F-G

0.007[0.18]

-C-

0.004[0.10]

0.005

[0.13]

Max

0.0100

[0.254]

0.118-0.129

[3.00-3.28]

0.020

[0.51]

A D-E, F-G

0.010[0.25]

0.042-0.048

[1.07-1.22]

0.025

[0.64]

45°X

0.045

[1.14]

Min

0.030-0.040

[0.76-1.02]

0.021-0.027

[0.53-0.69]

Detail A

Typical

Rotated 90°

0.025

[0.64]

Min

0.065-0.071

[1.65-1.80]

0.053-0.059

[1.65-1.80]

0.031-0.037

[0.79-0.94]

0.006-0.012

[0.15-0.30]

0.026-0.032

[0.66-0.81]

Typ

0.027-0.033

[0.69-0.84]

Section B-B

Typical

0.019-0.025

[0.48-0.64]

D-E, F-G

0.007[0.18]

32-Lead PLCC Package

Order Number NM27LV010VXXX

Package Number VA32A

Life Support Policy

Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written

approval of the President of Fairchild Semiconductor Corporation. As used herein:

1. Life support devices or systems are devices or systems which,

(a)areintendedforsurgicalimplantintothebody,or(b)support

or sustain life, and whose failure to perform, when properly

used in accordance with instructions for use provided in the

labeling, can be reasonably expected to result in a significant

injury to the user.

2. A critical component is any component of a life support device

or system whose failure to perform can be reasonably ex-

pected to cause the failure of the life support device or system,

or to affect its safety or effectiveness.

Fairchild Semiconductor

Americas

Fairchild Semiconductor

Europe

Fairchild Semiconductor

Hong Kong

Fairchild Semiconductor

Japan Ltd.

Customer Response Center

Tel. 1-888-522-5372

Fax:

Tel:

+44 (0) 1793-856858

8/F, Room 808, Empire Centre

68 Mody Road, Tsimshatsui East

Kowloon. Hong Kong

Tel; +852-2722-8338

Fax: +852-2722-8383

4F, Natsume Bldg.

Deutsch

English

Français

Italiano

+49 (0) 8141-6102-0

+44 (0) 1793-856856

+33 (0) 1-6930-3696

+39 (0) 2-249111-1

2-18-6, Yushima, Bunkyo-ku

Tokyo, 113-0034 Japan

Tel: 81-3-3818-8840

Fax: 81-3-3818-8841

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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NM27LV010TE250 [FAIRCHILD]

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