RF1K4922396 [FAIRCHILD]
2.5A, 30V, 0.150 Ohm, Dual P-Channel LittleFET⑩ Power MOSFET; 2.5A ， 30V ， 0.150欧姆，双P沟道LittleFET⑩功率MOSFET
| 型号： | RF1K4922396 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 2.5A, 30V, 0.150 Ohm, Dual P-Channel LittleFET⑩ Power MOSFET |
| 文件： | 总9页 (文件大小：236K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RF1K49223
Data Sheet
January 2002
2.5A, 30V, 0.150 Ohm, Dual P-Channel
LittleFET™ Power MOSFET
Features
• 2.5A, 30V
• r = 0.150Ω
The RF1K49223 Dual P-Channel power MOSFET is
manufactured using an advanced MegaFET process. This
process, which uses feature sizes approaching those of LSI
integrated circuits, gives optimum utilization of silicon,
resulting in outstanding performance. It is designed for use
in applications such as switching regulators, switching
converters, motor drivers, relay drivers, and low voltage bus
switches. This device can be operated directly from
integrated circuits.
DS(ON)
®
• Temperature Compensating PSPICE Model
• Thermal Impedance PSPICE Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Formerly developmental type TA49223.
Symbol
Ordering Information
PART NUMBER
PACKAGE
BRAND
RF1K49223
D1(8)
D1(7)
RF1K49223
MS-012AA
NOTE: When ordering, use the entire part number. For ordering in
tape and reel, add the suffix 96 to the part number, i.e. RF1K4922396.
S1(1)
G1(2)
D2(6)
D2(5)
S2(3)
G2(4)
Packaging
JEDEC MS-012AA
BRANDING DASH
5
1
2
3
4
©2002 Fairchild Semiconductor Corporation
RF1K49223 Rev. B
RF1K49223
o
Absolute Maximum Ratings T = 25 C Unless Otherwise Specified
A
RF1K49223
UNITS
Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
-30
-30
±20
V
V
V
DSS
Drain to Gate Voltage (R
= 20kΩ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
DGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
Drain Current
Continuous (Pulse Width = 5s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
2.5
A
D
Pulsed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
Refer to Peak Current Curve
DM
Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
Refer to UIS Curve
AS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
Derate Above 25 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
W
W/ C
D
o
o
0.016
o
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T , T
J
-55 to 150
C
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
o
300
260
C
C
L
o
pkg
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
o
o
1. T = 25 C to 125 C.
J
o
Electrical Specifications
T = 25 C, Unless Otherwise Specified
A
PARAMETER
SYMBOL
BV
TEST CONDITIONS
= 250µA, V = 0V, (Figure 12)
MIN
TYP
MAX
-
UNITS
V
Drain to Source Breakdown Voltage
Gate to Source Threshold Voltage
Zero Gate Voltage Drain Current
I
-30
-
-
DSS
D
GS
V
V
= V , I = 250µA, (Figure 11)
-1
-
-3
V
GS(TH)
GS
DS D
o
I
V
V
= -30V,
= 0V
T
T
= 25 C
-
-1
µA
µA
nA
Ω
DSS
DS
GS
A
A
o
= 150 C
-
-
-50
±100
0.150
0.360
40
Gate to Source Leakage Current
Drain to Source On Resistance
I
V
= ±20V
-
-
GSS
GS
r
I
= 2.5A,
V
= -10V
= -4.5V
-
-
DS(ON)
D
GS
GS
(Figure 9, 10)
= -15V, I
D
V
-
-
Ω
Turn-On Time
t
V
2.5A,
-
-
ns
ON
DD
R
R
= 6Ω, V = -10V,
L
GS
Turn-On Delay Time
Rise Time
t
-
9
-
ns
d(ON)
= 25Ω
GS
t
-
19
60
34
-
-
ns
r
Turn-Off Delay Time
Fall Time
t
-
-
ns
d(OFF)
t
-
-
ns
f
Turn-Off Time
t
-
140
35
ns
OFF
Total Gate Charge
Gate Charge at -10V
Threshold Gate Charge
Q
V
V
V
= 0V to -20V
= 0V to -10V
= 0V to -2V
V
= -24V,
2.5A,
= 9.6Ω
-
28
15
1.5
nC
nC
nC
g(TOT)
GS
GS
GS
DD
I
D
Q
-
19
g(-10)
R
L
I
= -1.0mA
Q
-
1.9
g(REF)
g(TH)
(Figure 14)
= 0V,
Input Capacitance
C
V
= -25V, V
GS
-
-
-
-
580
260
38
-
-
pF
pF
pF
ISS
OSS
RSS
DS
f = 1MHz
(Figure 13)
Output Capacitance
C
-
-
Reverse Transfer Capacitance
C
o
Thermal Resistance Junction to Ambient
R
Pulse Width = 1s
62.5
C/W
θJA
Device mounted on FR-4 material
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Reverse Recovery Time
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
-1.25
49
UNITS
V
V
I
I
= -2.5A
-
-
-
-
SD
SD
t
=-2.5A, dI /dt = 100A/µs
SD
ns
rr
SD
©2002 Fairchild Semiconductor Corporation
RF1K49223 Rev. B
RF1K49223
Typical Performance Curves
1.2
1.0
0.8
-3.0
-2.5
-2.0
-1.5
-1.0
0.6
0.4
0.2
0
-0.5
0
75
100
125
150
50
0
25
50
75
100
125
150
25
o
o
T , AMBIENT TEMPERATURE ( C)
T , AMBIENT TEMPERATURE ( C)
A
A
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
AMBIENT TEMPERATURE
10
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
1
0.02
0.01
P
DM
0.1
t
1
t
2
0.01
NOTES:
DUTY FACTOR: D = t /t
1
2
PEAK T = P
J
x Z
x R
+ T
JA A
DM
JA
θ
θ
SINGLE PULSE
0.001
-4
10
-5
-3
-2
-1
0
1
2
3
10
10
10
10
10
10
10
10
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
-100
-50
-10
o
T
= MAX RATED
FOR TEMPERATURES
ABOVE 25 C DERATE PEAK
CURRENT AS FOLLOWS:
V
= -20V
J
T = 25 C
A
GS
o
o
T
= 25 C
A
150 - T
I = I
A
25
V
= -10V
GS
125
5ms
10ms
-1
-0.1
-10
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
100ms
1s
OPERATION IN THIS
AREA MAY BE
DC
V
= -30V
-10
LIMITED BY r
DSS(MAX)
DS(ON)
-0.01
-1
10
-5
-4
-3
-2
-1
10
0
1
-0.1
-1
10
10
10
10
10
-100
V
, DRAIN TO SOURCE VOLTAGE (V)
t, PULSE WIDTH (s)
DS
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. PEAK CURRENT CAPABILITY
©2002 Fairchild Semiconductor Corporation
RF1K49223 Rev. B
RF1K49223
Typical Performance Curves (Continued)
-15
-20
If R = 0
AV
If R ≠ 0
V
= -20V
= -10V
= -8V
PULSE DURATION = 80µs
GS
t
= (L)(I )/(1.3*RATED BV
- V
)
DD
AS
DSS
DUTY CYCLE = 0.5% MAX
-10
V
GS
o
T
= 25 C
t
AV
= (L/R)ln[(I *R)/(1.3*RATED BV
- V ) +1]
DSS DD
A
AS
V
= -7V
-16
-12
-8
GS
V
GS
V
= -6V
GS
o
STARTING T = 25 C
J
V
= -5V
GS
o
STARTING T = 150 C
J
V
= -4.5V
GS
-4
-1
0.1
0
1
10
100
0
-1.5
-3.0
-4.5
-6.0
-7.5
t
, TIME IN AVALANCHE (ms)
AV
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 7. SATURATION CHARACTERISTICS
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
500
400
300
200
100
0
-20
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
= -15V
DD
V
= -15V
o
DD
150 C
-16
-12
-8
I
= -5.0A
= -2.5A
D
o
-55 C
I
D
o
25 C
I
= -1.25A
D
I
= -0.625A
D
-4
0
-6
-8
-10
-2
-4
0
-2
V
-4
-6
-8
-10
V
, GATE TO SOURCE VOLTAGE (V)
GS
, GATE TO SOURCE VOLTAGE (V)
GS
FIGURE 8. TRANSFER CHARACTERISTICS
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs
GATE VOLTAGE AND DRAIN CURRENT
2.0
1.5
1.0
0.5
0
1.2
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
= V , I = -250µA
GS
DS
D
V
= -10V, I = -2.5A
GS
D
1.0
0.8
0.6
0.4
-80
-80
-40
0
40
80
120
160
-40
0
40
80
120
160
o
o
T , JUNCTION TEMPERATURE ( C)
T , JUNCTION TEMPERATURE ( C)
J
J
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
©2002 Fairchild Semiconductor Corporation
RF1K49223 Rev. B
RF1K49223
Typical Performance Curves (Continued)
750
1.2
I
= -250µA
D
C
ISS
600
450
300
1.1
1.0
0.9
0.8
V
= 0V, f = 1MHz
GS
ISS
C
C
C
= C
+ C
GS GD
= C
RSS
OSS
GD
= C
C
C
+ C
DS GD
OSS
RSS
150
0
0
-5
V
-10
, DRAIN TO SOURCE VOLTAGE (V)
DS
-15
-20
-25
-80
-40
0
40
80
120
160
o
T , JUNCTION TEMPERATURE ( C)
J
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
-10.0
-30.0
V
= BV
DD
DSS
V
= BV
DSS
DD
-22.5
-15.0
-7.5
0
-7.5
-5.0
R
= 12Ω
L
I
= -0.26mA
G(REF)
V
= -10V
GS
PLATEAU VOLTAGES IN
DESCENDING ORDER:
V
V
V
V
= BV
-2.5
0
DD
DD
DD
DD
DSS
= 0.75 BV
= 0.50 BV
= 0.25 BV
DSS
DSS
DSS
I
I
G(REF)
G(REF)
t, TIME (µs)
20---------------------
80---------------------
I
I
G(ACT)
G(ACT)
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 14. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT
Test Circuits and Waveforms
V
DS
t
AV
L
0
VARY t TO OBTAIN
P
-
R
REQUIRED PEAK I
G
AS
V
DD
+
DUT
0V
V
DD
t
P
I
AS
V
GS
V
DS
I
AS
t
P
0.01Ω
BV
DSS
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 16. UNCLAMPED ENERGY WAVEFORMS
©2002 Fairchild Semiconductor Corporation
RF1K49223 Rev. B
RF1K49223
Test Circuits and Waveforms (Continued)
t
t
ON
OFF
t
t
d(OFF)
d(ON)
t
t
f
r
0
10%
10%
R
L
V
DS
V
GS
-
V
DS
90%
90%
V
DD
+
V
0
GS
V
GS
10%
50%
DUT
R
GS
50%
90%
PULSE WIDTH
FIGURE 18. RESISTIVE SWITCHING WAVEFORMS
FIGURE 17. SWITCHING TIME TEST CIRCUIT
V
DS
V
DS
Q
R
g(TH)
L
0
V
= -2V
GS
V
GS
-
V
= -10V
-V
GS
GS
V
DD
+
Q
g(-10)
V
= -20V
DUT
GS
V
DD
Q
g(TOT)
0
I
g(REF)
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORMS
Soldering Precautions
The soldering process creates a considerable thermal stress
on any semiconductor component. The melting temperature
of solder is higher than the maximum rated temperature of
the device. The amount of time the device is heated to a high
temperature should be minimized to assure device reliability.
Therefore, the following precautions should always be
observed in order to minimize the thermal stress to which the
devices are subjected.
4. The peak temperature in the soldering process should be
o
at least 30 C higher than the melting point of the solder
chosen.
5. The maximum soldering temperature and time must not
o
exceed 260 C for 10 seconds on the leads and case of
the device.
6. After soldering is complete, the device should be allowed
to cool naturally for at least three minutes, as forced cool-
ing will increase the temperature gradient and may result
in latent failure due to mechanical stress.
1. Always preheat the device.
2. The delta temperature between the preheat and solder-
o
ing should always be less than 100 C. Failure to preheat
7. During cooling, mechanical stress or shock should be
avoided.
the device can result in excessive thermal stress which
can damage the device.
3. The maximum temperature gradient should be less than
o
5 C per second when changing from preheating to sol-
dering.
©2002 Fairchild Semiconductor Corporation
RF1K49223 Rev. B
RF1K49223
PSPICE Electrical Model
SUBCKT RF1K49223 2 1 3 ;rev 4/7/97
CA 12 8 7.29e-10
CB 15 14 5.01e-10
CIN 6 8 5.55e-10
LDRAIN
ESG
5
DRAIN
2
-
+
8
6
10
RLDRAIN
RSLC1
51
DBODY 5 7 DBODYMOD
DBREAK 7 11 DBREAKMOD
DPLCAP 10 6 DPLCAPMOD
+
+
RSLC2
17
18
5
51
EBREAK
ESLC
-
-
50
EBREAK 5 11 17 18 -35.46
EDS 14 8 5 8 1
EGS 13 8 6 8 1
DPLCAP
RDRAIN
DBODY
ESG 5 10 8 6 1
EVTHRES 6 21 19 8 1
EVTEMP 6 20 18 22 1
EVTHRES
+
16
21
-
19
8
MWEAK
DBREAK
LGATE
EVTEMP
11
RGATE
GATE
1
6
-
+
18
22
MMED
9
20
IT 8 17 1
MSTRO
8
RLGATE
LSOURCE
LDRAIN 2 5 1e-9
LGATE 1 9 1.27e-9
LSOURCE 3 7 4.20e-10
CIN
SOURCE
3
7
RSOURCE
RLSOURCE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
S1A
S2A
RBREAK
12
15
13
8
14
13
17
18
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 19.3e-3
RGATE 9 20 7.44
RVTEMP
19
-
S1B
S2B
13
CB
CA
IT
14
RLDRAIN 2 5 10
+
+
RLGATE 1 9 12.7
RLSOURCE 3 7 4.2
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 65.37e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
22
RVTHRES
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*48),2.5))}
.MODEL DBODYMOD D (IS = 3.30e-13 RS = 4.56e-2 TRS1 =6.98e-4 TRS2 =8.08e-7 CJO = 8.21e-10 TT = 3.51e-8 M=0.4)
.MODEL DBREAKMOD D (RS = 8.18e- 1TRS1 =5.28e- 3TRS2 = -7.18e-5
.MODEL DPLCAPMOD D (CJO = 2.52e-1 0IS = 1e-3 0N = 10 M=0.6)
.MODEL MMEDMOD PMOS (VTO= -1.95 KP=0.75 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=7.44)
.MODEL MSTROMOD PMOS (VTO= -2.44 KP= 7.25 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MWEAKMOD PMOS (VTO= -1.68 KP=0.045 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=74.4 RS=0.1)
.MODEL RBREAKMOD RES (TC1 = 9.45e- 4TC2 = -1.01e-7)
.MODEL RDRAINMOD RES (TC1 = 3.69e-3 TC2 = 5.90e-6)
.MODEL RSLCMOD RES (TC1=3.46e-3 TC2= 1.26e-6)
.MODEL RSOURCEMOD RES (TC1=3.69e-3 TC2=5.90e-6)
.MODEL RVTHRESMOD RES (TC=-5.19e-4 TC2= 5.02e-6)
.MODEL RVTEMPMOD RES (TC1 = -3.54e- 3TC2 = -6.53e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 6.94 VOFF= 3.94)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 3.94 VOFF= 6.94)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.40 VOFF= -2.60)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.60 VOFF= 0.40)
.ENDS
NOTE:For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options;IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
©2002 Fairchild Semiconductor Corporation
RF1K49223 Rev. B
RF1K49223
PSPICE Thermal Model
JUNCTION
7
REV 28 Feb 97
RF1K49223
CTHERM1 7 6 1.00e-7
CTHERM2 6 5 9.00e-4
CTHERM3 5 4 3.00e-3
CTHERM4 4 3 4.00e-2
CTHERM5 3 2 5.20e-3
CTHERM6 2 1 1.90e-2
RTHERM1
CTHERM1
6
RTHERM1 7 6 7.10e-2
RTHERM2 6 5 1.90e-1
RTHERM3 5 4 5.95e-1
RTHERM4 4 3 4.27
RTHERM5 3 2 1.2e1
RTHERM6 2 1 1.04e2
RTHERM2
RTHERM3
RTHERM4
RTHERM5
RTHERM6
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
5
4
3
2
1
CASE
©2002 Fairchild Semiconductor Corporation
RF1K49223 Rev. B
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TruTranslation™
UHC™
QT Optoelectronics™
Quiet Series™
SILENTSWITCHERâ
FACT™
FACT Quiet Series™
UltraFETâ
STAR*POWER is used under license
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITYARISING OUT OF THE APPLICATION OR USE OFANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICESORSYSTEMSWITHOUTTHEEXPRESSWRITTENAPPROVALOFFAIRCHILDSEMICONDUCTORCORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Obsolete
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. H4
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