RF1S50N06LESM [FAIRCHILD]
Power Field-Effect Transistor, 50A I(D), 60V, 0.022ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-263AB,;
| 型号： | RF1S50N06LESM |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Power Field-Effect Transistor, 50A I(D), 60V, 0.022ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-263AB, 开关 晶体管 |
| 文件： | 总8页 (文件大小：460K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RFG50N06LE, RFP50N06LE, RF1S50N06LESM
Data Sheet
October 1999
File Number 4072.3
50A, 60V, 0.022 Ohm, Logic Level
N-Channel Power MOSFETs
Features
• 50A, 60V
Title These N-Channel enhancement mode power MOSFETs are
• r = 0.022Ω
DS(ON)
manufactured using the latest manufacturing process
FG5
06L
®
• Temperature Compensating PSPICE Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
technology. This process, which uses feature sizes
approaching those of LSI circuits, gives optimum utilization
of silicon, resulting in outstanding performance. They were
P50
designed for use in applications such as switching
o
6LE
regulators, switching converters, motor drivers, and relay
drivers. These transistors can be operated directly from
integrated circuits.
• 175 C Operating Temperature
• Related Literature
1S5
06L
M)
b-
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Formerly developmental type TA49164.
Symbol
Ordering Information
D
t
A,
PART NUMBER
PACKAGE
BRAND
FG50N06L
RFG50N06LE
TO-247
V,
RFP50N06LE
TO-220AB
TO-263AB
FP50N06L
F50N06LE
G
22
m,
gic
vel
RF1S50N06LESM
NOTE: When ordering, use the entire part number. Add the suffix 9A
to obtain the TO-263AB variant in tape and reel, i.e.
RF1S50N06LESM9A.
S
an-
Packaging
JEDEC STYLE TO-247
JEDEC TO-220AB
wer
OS-
Ts)
SOURCE
DRAIN
SOURCE
DRAIN
GATE
GATE
utho
DRAIN
(BOTTOM
SIDE METAL)
DRAIN (FLANGE)
ey-
rds
ter-
rpo-
on,
gic
JEDEC TO-263AB
vel
DRAIN
(FLANGE)
GATE
an-
SOURCE
wer
OS-
©2001 Fairchild Semiconductor Corporation
RFG50N06LE, RFP50N06LE, RF1S50N06LESM Rev. A
RFG50N06LE, RFP50N06LE, RF1S50N06LESM
o
Absolute Maximum Ratings T = 25 C, Unless Otherwise Specified
C
RFG50N06LE, RFP50N06LE,
RF1S50N06LESM
UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
60
60
10
V
V
V
A
DSS
DGR
GS
D
DM
Drain to Gate Voltage (R
= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
50
Refer to Peak Current Curve
Refer to UIS Curve
142
Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
AS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
W
D
o
o
Derate Above 25 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0.95
-55 to 175
W/ C
o
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T , T
C
J
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . T
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
o
o
300
260
C
C
L
pkg
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
o
o
1. T = 25 C to 150 C.
J
o
Electrical Specifications
T = 25 C, Unless Otherwise Specified
C
PARAMETER
SYMBOL
BV
TEST CONDITIONS
= 250µA, V = 0V, Figure 13
MIN
TYP
MAX
-
UNITS
V
Drain to Source Breakdown Voltage
Gate Threshold Voltage
I
60
1
-
-
-
DSS
D
GS
= V , I = 250µA, Figure 12
V
V
V
V
V
3
V
GS(TH)
GS
DS
DS
GS
DS D
Zero Gate Voltage Drain Current
I
= 55V, V
= 50V, V
= 0V
-
1
µA
µA
µA
Ω
DSS
GSS
GS
GS
o
= 0V, T = 150 C
-
-
250
10
0.022
230
-
C
Gate to Source Leakage Current
I
=
10V
-
-
Drain to Source On Resistance (Note 2)
Turn-On Time
r
I
= 50A, V
= 5V, Figure 11
-
-
DS(ON)
D
GS
t
V
R
R
= 30V, I = 50A,
-
-
ns
ON
DD
D
= 0.6Ω, V
= 5V,
L
GS
Turn-On Delay Time
Rise Time
t
-
20
170
48
90
-
ns
d(ON)
= 2.5Ω
GS
t
-
-
ns
r
Figures 10, 18, 19
Turn-Off Delay Time
Fall Time
t
-
-
ns
d(OFF)
t
-
-
ns
f
Turn-Off Time
t
-
165
120
70
2.7
ns
OFF
Total Gate Charge
Gate Charge at 5V
Threshold Gate Charge
Q
V
V
V
= 0V to 10V
= 0V to 5V
= 0V to 1V
V
= 48V,
-
96
57
2.2
nC
nC
nC
g(TOT)
GS
GS
GS
DD
= 50A,
I
D
Q
-
g(5)
R
= 0.96Ω
L
Q
-
g(TH)
(Figures 21, 21)
= 25V, V = 0V,
GS
Input Capacitance
C
V
-
-
-
-
-
-
2100
-
-
pF
pF
pF
ISS
OSS
RSS
DS
f = 1MHz
Figure 14
Output Capacitance
C
C
600
Reverse Transfer Capacitance
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
230
-
o
R
-
-
-
1.05
30
80
C/W
θJC
θJA
o
R
TO-247
C/W
o
TO-220AB and TO-263AB
C/W
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Diode Reverse Recovery Time
NOTES:
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
V
V
I
I
= 45A
-
-
-
-
1.5
SD
SD
SD
t
= 45A, dI /dt = 100A/µs
SD
125
ns
rr
2. Pulse test: pulse width ≤ 80µs, duty cycle ≤ 2%.
3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3).
©2001 Fairchild Semiconductor Corporation
RFG50N06LE, RFP50N06LE, RF1S50N06LESM Rev. A
RFG50N06LE, RFP50N06LE, RF1S50N06LESM
Typical Performance Curves Unless Otherwise Specified
1.2
60
50
40
30
20
10
0
1.0
0.8
0.6
0.4
0.2
0
0
25
50
75
100
125
o
150
175
25
50
75
100
125
o
150
175
T
, CASE TEMPERATURE ( C)
T
, CASE TEMPERATURE ( C)
C
C
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
1
0.5
P
0.2
DM
0.1
0.1
t
t
1
0.05
2
0.02
0.01
NOTES:
DUTY FACTOR: D = t /t
1
2
x R
PEAK T = P
x Z
+ T
JC C
J
DM
JC
θ
θ
SINGLE PULSE
0.01
-5
-4
-3
10
-2
10
-1
10
0
1
10
10
10
10
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
500
100
1000
o
= 25 C
= MAX RATED
T
o
= 25 C
C
T
C
T
J
V
= 10V
GS
100µs
V
= 5V
GS
100
1ms
10
1
FOR TEMPERATURES
THERMAL IMPEDANCE
MAY LIMIT CURRENT
IN THIS REGION
10ms
o
ABOVE 25 C DERATE PEAK
CURRENT AS FOLLOWS:
OPERATION IN THIS
AREA MAY BE
175 - T
150
C
I = I
LIMITED BY r
25
DS(ON)
10
-5
10
-4
10
-3
10
-2
-1
0
1
1
10
, DRAIN TO SOURCE VOLTAGE (V)
100
200
10
10
10
10
V
DS
t, PULSE WIDTH (s)
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. PEAK CURRENT CAPABILITY
©2001 Fairchild Semiconductor Corporation
RFG50N06LE, RFP50N06LE, RF1S50N06LESM Rev. A
RFG50N06LE, RFP50N06LE, RF1S50N06LESM
Typical Performance Curves Unless Otherwise Specified (Continued)
300
100
75
50
25
0
t
t
= (L/R)ln[(I *R)/(1.3*RATED BV
AS DSS
- V ) +1]
DD
o
AV
T
= 25 C
C
V
= 10V
= 5V
GS
If R ≠ 0
AV
If R = 0
= (L)(I )/(1.3*RATED BV
DSS
- V )
DD
V
AS
GS
100
V
= 4V
GS
o
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
STARTING T = 25 C
J
10
o
STARTING T = 150 C
J
V
= 3V
GS
V
= 2.5V
GS
1
0.01
0.1
t
1
10
100
0
1.5
3.0
4.5
6.0
,TIME IN AVALANCHE (ms)
V
, DRAIN TO SOURCE VOLTAGE (V)
AV
DS
NOTE: Refer to Intersil Application Notes AN9321 and AN9322
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
FIGURE 7. SATURATION CHARACTERISTICS
100
80
60
o
-55 C
V
= 15V
DD
o
I
= 12.5A
I
= 50A
I
= 100A
D
25 C
D
D
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
o
175 C
75
50
25
40
20
0
I
= 25A
D
V
= 15V
DD
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
1.5
3.0
4.5
6.0
V
, GATE TO SOURCE VOLTAGE (V)
V
, GATE TO SOURCE VOLTAGE (V)
GS
GS
FIGURE 8. TRANSFER CHARACTERISTICS
FIGURE 9. DRAINTO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
2.5
600
500
400
300
200
100
V
= 5V, I = 50A
D
GS
V
= 30V, I = 50A, R = 0.6Ω
D L
DD
t
r
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
2.0
1.5
1.0
0.5
t
d(OFF)
t
f
t
d(ON)
0
-80
-40
0
40
80
120
o
160
200
0
10
20
30
40
50
R
, GATE TO SOURCE RESISTANCE (Ω)
T , JUNCTION TEMPERATURE ( C)
GS
J
FIGURE 10. SWITCHING TIME vs GATE RESISTANCE
FIGURE 11. NORMALIZED DRAINTO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
©2001 Fairchild Semiconductor Corporation
RFG50N06LE, RFP50N06LE, RF1S50N06LESM Rev. A
RFG50N06LE, RFP50N06LE, RF1S50N06LESM
Typical Performance Curves Unless Otherwise Specified (Continued)
2.0
1.5
1.0
0.5
0
1.2
1.1
1.0
0.9
0.8
V
= V , I = 250µA
DS
GS
D
I
= 250µA
D
-80
-40
0
40
80
120
o
160
200
-80
-40
0
40
80
120
160
200
o
T , JUNCTION TEMPERATURE ( C)
T , JUNCTION TEMPERATURE ( C)
J
J
FIGURE 12. NORMALIZED GATETHRESHOLDVOLTAGE vs
JUNCTION TEMPERATURE
FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
60
5.0
3.75
2.5
1.25
0
2500
V
= BV
DSS
V
= BV
DD
DD DSS
C
ISS
2000
1500
1000
500
0
45
R
=1.2Ω
L
V
= 0V, f = 1MHz
GS
I
= 1.2mA
G(REF)
= 5V
C
C
C
= C
+ C
ISS
GS
GD
V
GS
= C
GD
RSS
OSS
30
15
0
≈ C
+ C
GD
DS
PLATEAU VOLTAGES IN
DESCENDING ORDER:
V
V
V
V
= BV
DD
DD
DD
DD
DSS
C
C
OSS
= 0.75 BV
= 0.50 BV
= 0.25 BV
DSS
DSS
DSS
RSS
I
I
G(REF)
G(REF)
t,TIME (µs)
0
5
10
15
20
25
---------------------
---------------------
20
80
I
I
G(ACT)
G(ACT)
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 15. NORMALIZED SWITCHINGWAVEFORMS FOR
CONSTANT GATE CURRENT
FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
Test Circuits and Waveforms
V
DS
BV
DSS
L
t
P
V
DS
I
VARY t TO OBTAIN
P
AS
+
-
V
DD
R
REQUIRED PEAK I
G
AS
V
DD
V
GS
DUT
t
P
I
AS
0V
0
0.01Ω
t
AV
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 17. UNCLAMPED ENERGY WAVEFORMS
©2001 Fairchild Semiconductor Corporation
RFG50N06LE, RFP50N06LE, RF1S50N06LESM Rev. A
RFG50N06LE, RFP50N06LE, RF1S50N06LESM
Test Circuits and Waveforms (Continued)
t
t
ON
OFF
t
d(OFF)
t
d(ON)
V
DS
t
t
f
r
V
DS
90%
90%
R
L
V
GS
+
10%
10%
0
V
DD
-
DUT
90%
50%
R
GS
V
GS
50%
PULSE WIDTH
10%
V
GS
0
FIGURE 18. SWITCHING TIME TEST CIRCUIT
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
V
DS
V
Q
R
DD
g(TOT)
L
V
DS
V
= 20V
GS
V
L
= 10V FOR
Q
OR Q
GS
DEVICES
g(10)
g(5)
V
GS
2
+
-
V
DD
V
= 10V
GS
V
GS
V
= 5V FOR
GS
2
L
DEVICES
DUT
V
= 2V
V
= 1V FOR
L DEVICES
GS
GS
2
I
0
g(REF)
Q
g(TH)
I
g(REF)
0
FIGURE 20. GATE CHARGE TEST CIRCUIT
FIGURE 21. GATE CHARGE WAVEFORMS
©2001 Fairchild Semiconductor Corporation
RFG50N06LE, RFP50N06LE, RF1S50N06LESM Rev. A
RFG50N06LE, RFP50N06LE, RF1S50N06LESM
PSPICE Electrical Model
SUBCKT 50N06LE 2 1 3 ;
rev 8/11/95
CA 12 8 3.73e-9
CB 15 14 3.73e-9
CIN 6 8 2.08e-9
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
LDRAIN
DPLCAP
DRAIN
2
5
10
RLDRAIN
RSLC1
51
EBREAK 11 7 17 18 66.5
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
DBREAK
+
RSLC2
5
ESLC
11
51
-
50
+
-
17
18
-
DBODY
RDRAIN
6
8
EBREAK
ESG
IT 8 17 1
EVTHRES
+
+
16
21
-
19
8
MWEAK
LDRAIN 2 5 4.0e-9
LGATE 1 9 6.0e-9
LSOURCE 3 7 3.0e-9
LGATE
EVTEMP
+
RGATE
GATE
1
6
-
18
22
MMED
9
20
MSTRO
8
RLGATE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
LSOURCE
CIN
SOURCE
3
7
RSOURCE
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 3.75e-3
RGATE 9 20 1.0
RLDRAIN 2 5 40
RLGATE 1 9 60
RLSOURCE
S1A
S2A
RBREAK
12
15
13
8
14
13
17
18
RLSOURCE 3 7 30
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 6.15e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
RVTEMP
19
S1B
S2B
13
CB
CA
IT
14
-
+
+
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
22
RVTHRES
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*200),4))}
.MODEL DBODYMOD D (IS = 1.70e-12 RS = 3.20e-3 TRS1 = 1.75e-3 TRS2 = 1.75e-6 CJO = 2.55e-9 IKF = 13 XTI = 5.2 TT = 7.00e-8 M = 0.47)
.MODEL DBREAKMOD D (RS = 1.70e-1 IKF = 0.1 TRS1 = 2.00e-3 TRS2 = 8.00e-7)
.MODEL DPLCAPMOD D (CJO = 2.00e-9 IS = 1e-30 VJ = 1.1 M = 0.83 N = 10)
.MODEL MMEDMOD NMOS (VTO = 2.00 KP = 5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.0)
.MODEL MSTROMOD NMOS (VTO = 2.42 KP = 128 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.60 KP = 0.01 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 10.0 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1.13e-3 TC2 = 0)
.MODEL RDRAINMOD RES (TC1 = 1.20e-2 TC2 = 6.00e-5)
.MODEL RSLCMOD RES (TC1 = 2.00e-3 TC2 = 1.00e-6)
.MODEL RSOURCEMOD RES (TC1 = 2.00e-3 TC2 =-1.00e-5)
.MODEL RVTHRESMOD RES (TC1 = -2.50e-3 TC2 = -8.50e-6)
.MODEL RVTEMPMOD RES (TC1 = -2.00e-3 TC2 = 5.00e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5.3 VOFF= -2.5)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.5 VOFF= -5.3)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.4 VOFF= 0.5)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.5 VOFF= -1.4)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
©2001 Fairchild Semiconductor Corporation
RFG50N06LE, RFP50N06LE, RF1S50N06LESM Rev. A
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUTTHE EXPRESS WRITTENAPPROVALOF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Obsolete
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. H
相关型号：
RF1S50N06LESM9A
Power Field-Effect Transistor, 50A I(D), 60V, 0.022ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-263AB,
FAIRCHILD
RF1S50N06SM9A
Power Field-Effect Transistor, 50A I(D), 60V, 0.022ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-263AB,
FAIRCHILD
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