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RFG70N06_NL [FAIRCHILD]

Power Field-Effect Transistor, 70A I(D), 60V, 0.014ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-247, LEAD FREE PACKAGE-3;
RFG70N06_NL
型号： RFG70N06_NL
厂家： FAIRCHILD SEMICONDUCTOR    FAIRCHILD SEMICONDUCTOR
描述：

Power Field-Effect Transistor, 70A I(D), 60V, 0.014ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-247, LEAD FREE PACKAGE-3

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RFG70N06, RFP70N06, RF1S70N06,  
RF1S70N06SM  
Data Sheet  
February 2005  
70A, 60V, 0.014 Ohm, N-Channel Power  
MOSFETs  
Features  
• 70A, 60V  
These are N-Channel power MOSFETs manufactured using  
the MegaFET process. This process, which uses feature  
sizes approaching those of LSI circuits, gives optimum  
utilization of silicon, resulting in outstanding performance.  
They were designed for use in applications such as  
switching regulators, switching converters, motor drivers and  
relay drivers. These transistors can be operated directly from  
integrated circuits.  
• r  
= 0.014Ω  
DS(on)  
®
• Temperature Compensated PSPICE Model  
• Peak Current vs Pulse Width Curve  
• UIS Rating Curve (Single Pulse)  
o
• 175 C Operating Temperature  
• Related Literature  
Formerly developmental type TA78440.  
- TB334 “Guidelines for Soldering Surface Mount  
Components to PC Boards”  
Ordering Information  
Symbol  
PART NUMBER  
PACKAGE  
BRAND  
RFG70N06  
D
RFG70N06  
TO-247  
RFP70N06  
TO-220AB  
TO-262AA  
TO-263AB  
RFP70N06  
F1S70N06  
F1S70N06  
G
RF1S70N06  
RF1S70N06SM  
S
NOTE: When ordering use the entire part number. Add the suffix 9A to  
obtain the TO-263AB variant in tape and reel, e.g. RF1S70N06SM9A.  
Packaging  
JEDEC STYLE TO-247  
JEDEC TO-263AB  
SOURCE  
DRAIN  
GATE  
DRAIN  
DRAIN  
(FLANGE)  
GATE  
(BOTTOM  
SIDE METAL)  
SOURCE  
JEDEC TO-262AA  
JEDEC TO-220AB  
SOURCE  
DRAIN  
SOURCE  
GATE  
DRAIN  
DRAIN  
(FLANGE)  
GATE  
DRAIN  
(FLANGE)  
©2005 Fairchild Semiconductor Corporation  
RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM Rev. D  
RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM  
o
Absolute Maximum Ratings  
T
= 25 C, Unless Otherwise Specified  
C
RFG70N06, RFP70N06  
RF1S70N06, RF1S70N06SM  
UNITS  
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V  
60  
60  
70  
V
V
A
DSS  
DGR  
Drain to Gate Voltage (R  
= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . .V  
GS  
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I  
D
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I  
Refer to Peak Current Curve  
DM  
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V  
±20  
Refer to UIS Curve  
150  
V
A
GS  
Single Pulse Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E  
AS  
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P  
W
D
o
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
1.0  
-55 to 175  
W/ C  
o
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . T , T  
C
J
STG  
Maximum Temperature for Soldering  
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . .T  
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . T  
o
300  
260  
C
C
L
o
pkg  
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the  
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
NOTE:  
o
o
1. T = 25 C to 150 C.  
J
o
Electrical Specifications  
T
= 25 C, Unless Otherwise Specified  
C
PARAMETER  
SYMBOL  
TEST CONDITIONS  
= 250µA, V = 0V (Figure 11)  
MIN  
TYP MAX UNITS  
Drain to Source Breakdown Voltage  
Gate Threshold Voltage  
BV  
I
60  
2
-
-
-
4
V
DSS  
D
GS  
V
V
V
V
V
= V , I = 250µA (Figure 10)  
-
-
V
GS(TH)  
GS  
DS  
DS  
GS  
DS  
D
Zero Gate Voltage Drain Current  
I
= 60V, V = 0V  
GS  
1
µA  
µA  
nA  
Ω
DSS  
o
= 0.8 x Rated BV  
, T = 150 C  
-
-
25  
±100  
0.014  
190  
-
DSS  
C
Gate to Source Leakage Current  
I
= ±20V  
-
-
GSS  
Drain to Source On Resistance (Note 2)  
Turn-On Time  
r
I
= 70A, V  
= 10V (Figure 9)  
= 30V, I ≈ 70A, R = 0.43Ω,  
-
-
DS(ON)  
D GS  
t
V
V
-
-
ns  
(ON)  
DD  
GS  
D
L
= 10V, R  
= 2.5Ω  
GS  
Turn-On Delay Time  
t
-
10  
137  
32  
24  
-
ns  
d(ON)  
(Figure 13)  
Rise Time  
t
-
-
ns  
r
Turn-Off Delay Time  
t
-
-
ns  
d(OFF)  
Fall Time  
t
-
-
ns  
f
Turn-Off Time  
t
-
73  
156  
85  
6.5  
-
ns  
(OFF)  
Total Gate Charge  
Q
V
V
V
V
= 0V to 20V  
= 0V to 10V  
= 0V to 2V  
V
R
= 48V, I = 70A,  
= 0.68Ω  
-
120  
65  
5.0  
2250  
792  
206  
-
nC  
nC  
nC  
pF  
pF  
pF  
C/W  
C/W  
C/W  
g(TOT)  
GS  
GS  
GS  
DS  
DD  
D
L
Gate Charge at 10V  
Q
-
g(10)  
I
= 2.2mA  
g(REF)  
Threshold Gate Charge  
Input Capacitance  
Q
-
(Figure 13)  
g(TH)  
C
= 25V, V  
GS  
= 0V, f = 1MHz  
-
ISS  
OSS  
RSS  
(Figure 12)  
Output Capacitance  
C
-
-
Reverse Transfer Capacitance  
Thermal Resistance, Junction to Case  
Thermal Resistance, Junction to Ambient  
C
-
-
o
o
o
R
-
1.0  
62  
30  
θJC  
θJA  
R
TO-220 and TO-263  
TO-247  
-
-
-
-
Source to Drain Diode Specifications  
PARAMETER  
Source to Drain Diode Voltage  
Reverse Recovery Time  
NOTES:  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP MAX UNITS  
V
I
I
= 70A  
-
-
1.5  
52  
V
SD  
SD  
t
= 70A, dI /dt = 100A/µs  
SD  
ns  
rr  
SD  
2. Pulse test: pulse width ≤300ms, duty cycle ≤2%.  
3. Repetitive rating: pulse width is limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3) and Peak Current  
Capability Curve (Figure 5).  
©2005 Fairchild Semiconductor Corporation  
RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM Rev. D  
RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM  
o
Typical Performance Curves  
T
= 25 C, Unless Otherwise Specified  
C
1.2  
80  
70  
1.0  
0.8  
0.6  
0.4  
0.2  
60  
50  
40  
30  
20  
10  
0
25  
0
50  
75  
100  
150  
125  
o
175  
0
25  
50  
75  
100  
125  
o
150  
175  
T
, CASE TEMPERATURE ( C)  
T , CASE TEMPERATURE ( C)  
C
C
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE  
TEMPERATURE  
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs  
CASE TEMPERATURE  
1
0.5  
0.2  
P
DM  
0.1  
0.1  
0.05  
t
1
t
2
0.02  
0.01  
NOTES:  
DUTY FACTOR: D = t /t  
1
2
SINGLE PULSE  
PEAK T = P  
x Z  
x R  
+ T  
JC C  
J
DM  
JC  
θ
θ
0.01  
-5  
-4  
-3  
10  
-2  
10  
-1  
0
1
10  
10  
10  
t, RECTANGULAR PULSE DURATION (s)  
10  
10  
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE  
500  
100  
1000  
o
= 25 C  
FOR TEMPERATURES  
ABOVE 25 C DERATE PEAK  
CURRENT AS FOLLOWS:  
T
C
o
100µs  
175 – T  
C
I = I  
-----------------------  
25  
150  
1ms  
OPERATION IN THIS  
AREA MAY BE  
V
= 10V  
GS  
10  
1
LIMITED BY r  
DS(ON)  
10ms  
100  
50  
o
TRANSCONDUCTANCE  
MAY LIMIT CURRENT  
IN THIS REGION  
T
T
= 25 C  
C
= MAX RATED  
J
SINGLE PULSE  
100  
1
10  
, DRAIN TO SOURCE VOLTAGE (V)  
-5  
-4  
-3  
-2  
-1  
10  
0
1
10  
10  
10  
10  
10  
10  
V
DS  
t, PULSE WIDTH (s)  
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA  
FIGURE 5. PEAK CURRENT CAPABILITY  
©2005 Fairchild Semiconductor Corporation  
RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM Rev. D  
RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM  
o
Typical Performance Curves  
T
= 25 C, Unless Otherwise Specified (Continued)  
C
300  
200  
If R = 0  
AV  
If R ≠ 0  
V
= 10V  
V
= 8V  
V
= 7V  
V
= 20V  
t
= (L)(I )/(1.3*RATED BV  
- V  
)
DD  
GS  
GS  
GS  
GS  
AS  
DSS  
t
= (L/R) ln [(I *R)/(1.3*RATED BV  
-V ) +1]  
DSS DD  
AV  
AS  
160  
120  
80  
40  
0
100  
o
PULSE DURATION = 80µs  
STARTING T = 25 C  
J
DUTY CYCLE = 0.5% MAX  
o
T
= 25 C  
C
V
= 6V  
GS  
V
= 5V  
o
GS  
STARTING T = 150 C  
J
V
= 4.5V  
GS  
10  
0.01  
1
0
1
2
3
4
5
0.1  
10  
t
, TIME IN AVALANCHE (ms)  
AV  
V
, DRAIN TO SOURCE VOLTAGE (V)  
DS  
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.  
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY  
FIGURE 7. SATURATION CHARACTERISTICS  
200  
2.5  
2
PULSE DURATION = 80µs  
PULSE DURATION = 250µs  
DUTY CYCLE = 0.5% MAX  
DUTY CYCLE = 0.5% MAX  
o
o
-55 C  
25 C  
V
= 10V, I = 70A  
GS  
D
V
= 15V  
DD  
160  
120  
o
175 C  
1.5  
1
80  
40  
0.5  
0
-80  
0
-40  
0
40  
80  
120  
160  
200  
0
2
4
6
8
10  
o
V
, GATE TO SOURCE VOLTAGE (V)  
T , JUNCTION TEMPERATURE ( C)  
GS  
J
FIGURE 8. TRANSFER CHARACTERISTICS  
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON  
RESISTANCE vs JUNCTION TEMPERATURE  
2.0  
1.5  
2.0  
1.5  
1.0  
0.5  
0
V
= V , I = 250µA  
DS  
GS  
D
I
= 250µA  
D
1.0  
0.5  
0
-80  
-40  
0
40  
80  
120  
o
160  
200  
-80  
-40  
0
40  
80  
120  
160  
200  
o
T , JUNCTION TEMPERATURE ( C)  
T , JUNCTION TEMPERATURE ( C)  
J
J
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs  
JUNCTION TEMPERATURE  
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN  
VOLTAGE vs JUNCTION TEMPERATURE  
©2005 Fairchild Semiconductor Corporation  
RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM Rev. D  
RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM  
o
Typical Performance Curves  
T
= 25 C, Unless Otherwise Specified (Continued)  
C
60  
10  
5000  
V
= 0V, f = 1MHz  
GS  
C
C
C
= C  
+ C  
ISS  
GS  
GD  
V
= BV  
DSS  
DD  
V
= BV  
DD DSS  
4000  
= C  
≈
RSS  
OSS  
GD  
C
45  
30  
7.5  
5
+ C  
DS  
GS  
C
ISS  
R
= 0.86Ω  
= 2.2mA  
L
3000  
2000  
I
G(REF)  
V
= 10V  
GS  
0.75 BV  
0.50 BV  
0.25 BV  
DSS  
DSS  
DSS  
C
OSS  
15  
0
2.5  
0
1000  
0
C
RSS  
I
I
25  
0
5
10  
15  
20  
G(REF)  
G(ACT)  
G(REF)  
G(ACT)  
20  
t, TIME (µs)  
80  
I
I
V
, DRAIN TO SOURCE VOLTAGE (V)  
DS  
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.  
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE  
FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR  
CONSTANT GATE CURRENT  
Test Circuits and Waveforms  
V
DS  
BV  
DSS  
L
t
P
V
DS  
I
VARY t TO OBTAIN  
P
AS  
+
-
V
DD  
R
REQUIRED PEAK I  
G
AS  
V
DD  
V
GS  
DUT  
t
P
I
AS  
0V  
0
0.01Ω  
t
AV  
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT  
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS  
t
t
ON  
OFF  
t
d(OFF)  
t
d(ON)  
V
DS  
t
t
f
r
V
DS  
90%  
90%  
R
L
V
GS  
+
10%  
10%  
0
0
V
DD  
-
DUT  
90%  
50%  
R
GS  
V
GS  
50%  
PULSE WIDTH  
10%  
V
GS  
FIGURE 16. SWITCHING TIME TEST CIRCUIT  
FIGURE 17. SWITCHING WAVEFORMS  
©2005 Fairchild Semiconductor Corporation  
RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM Rev. D  
RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM  
Test Circuits and Waveforms (Continued)  
V
DS  
V
DD  
Q
g(TOT)  
R
L
V
DS  
V
= 20V  
GS  
Q
V
g(10)  
GS  
+
-
V
DD  
V
= 10V  
V
GS  
GS  
DUT  
V
= 2V  
GS  
0
I
g(REF)  
Q
g(TH)  
I
g(REF)  
0
FIGURE 19. GATE CHARGE WAVEFORM  
FIGURE 18. GATE CHARGE TEST CIRCUIT  
©2005 Fairchild Semiconductor Corporation  
RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM Rev. D  
RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM  
PSPICE Electrical Model  
.SUBCKT RFG70N06 2 1 3 ;  
rev 3/20/92  
CA 12 8 5.56e-9  
CB 15 14 5.30e-9  
CIN 6 8 2.63e-9  
RLDRAIN  
LDRAIN  
DPLCAP  
5
10  
2
DRAIN  
DBODY 7 5 DBDMOD  
DBREAK 5 11 DBKMOD  
DPLCAP 10 5 DPLCAPMOD  
RSCL2  
RSCL1  
DBREAK  
+
51  
5
51  
ESCL  
50  
EBREAK 11 7 17 18 65.18  
EDS 14 8 5 8 1  
EGS 13 8 6 8 1  
ESG 6 10 6 8 1  
EVTO 20 6 18 8 1  
DBODY  
-
11  
+
6
8
RDRAIN  
ESG  
EBREAK  
MOS2  
17  
18  
16  
+
VTO  
+
-
-
RLGATE  
EVTO  
21  
GATE  
9
20  
+
6
-
18  
8
IT 8 17 1  
1
MOS1  
8
RGATE  
LGATE  
LDRAIN 2 5 1e-9  
LGATE 1 9 3.10e-9  
LSOURCE 3 7 1.82e-9  
RIN  
CIN  
RLSOURCE  
3
RSOURCE  
7
SOURCE  
LSOURCE  
MOS1 16 6 8 8 MOSMOD M = 0.99  
MOS2 16 21 8 8 MOSMOD M = 0.01  
S1A  
S2A  
12  
RBREAK  
15  
13  
8
14  
13  
17  
18  
RBREAK 17 18 RBKMOD 1  
RDRAIN 50 16 RDSMOD 4.66e-3  
RLDRAIN 2 5 10  
RGATE 9 20 1.21  
RLGATE 1 9 31  
S1B  
CA  
S2B  
13  
RVTO  
19  
VBAT  
CB  
IT  
14  
+
+
6
8
5
8
EDS  
EGS  
+
RIN 6 8 1e9  
-
-
RSOURCE 8 7 RDSMOD 3.92e-3  
RLSOURCE 3 7 18.2  
RVTO 18 19 RVTOMOD 1  
S1A 6 12 13 8 S1AMOD  
S1B 13 12 13 8 S1BMOD  
S2A 6 15 14 13 S2AMOD  
S2B 13 15 14 13 S2BMOD  
VBAT 8 19 DC 1  
VTO 21 6 0.605  
.MODEL DBDMOD D (IS = 7.91e-12 RS = 3.87e-3 TRS1 = 2.71e-3 TRS2 = 2.50e-7 CJO = 4.84e-9 TT = 4.51e-8)  
.MODEL DBKMOD D (RS = 3.9e-2 TRS1 =1.05e-4 TRS2 = 3.11e-5)  
.MODEL DPLCAPMOD D (CJO = 4.8e-9 IS = 1e-30 N = 10)  
.MODEL MOSMOD NMOS (VTO = 3.46 KP = 47 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)  
.MODEL RBKMOD RES (TC1 = 8.46e-4 TC2 = -8.48e-7)  
.MODEL RDSMOD RES (TC1 = 2.23e-3 TC2 = 6.56e-6)  
.MODEL RVTOMOD RES (TC1 = -3.29e-3 TC2 = 3.49e-7)  
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -8.35 VOFF= -6.35)  
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -6.35 VOFF= -8.35)  
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.0 VOFF= 3.0)  
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 3.0 VOFF= -2.0)  
.ENDS  
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global  
Temperature Options; written by William J. Hepp and C. Frank Wheatley.  
©2005 Fairchild Semiconductor Corporation  
RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM Rev. D  
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PowerTrench  
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SuperFET™  
SuperSOT™-3  
SuperSOT™-6  
SuperSOT™-8  
SyncFET™  
QS™  
HiSeC™  
I2C™  
QT Optoelectronics™ TinyLogic  
Quiet Series™  
RapidConfigure™  
RapidConnect™  
µSerDes™  
TINYOPTO™  
TruTranslation™  
UHC™  
i-Lo™  
ImpliedDisconnect™  
FACT Quiet Series™  
UltraFET  
Across the board. Around the world.™  
The Power Franchise  
ProgrammableActive Droop™  
SILENT SWITCHER UniFET™  
SMART START™  
VCX™  
DISCLAIMER  
FAIRCHILD SEMICONDUCTOR RESERVESTHE RIGHTTO MAKE CHANGES WITHOUTFURTHER NOTICETOANY  
PRODUCTS HEREINTO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOTASSUMEANYLIABILITY  
ARISING OUTOFTHEAPPLICATION OR USE OFANYPRODUCTOR CIRCUITDESCRIBED HEREIN; NEITHER DOES IT  
CONVEYANYLICENSE UNDER ITS PATENTRIGHTS, NORTHE RIGHTS OF OTHERS.  
LIFE SUPPORT POLICY  
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT  
DEVICES OR SYSTEMS WITHOUTTHE EXPRESS WRITTENAPPROVALOF FAIRCHILD SEMICONDUCTOR CORPORATION.  
As used herein:  
1. Life support devices or systems are devices or  
systems which, (a) are intended for surgical implant into  
the body, or (b) support or sustain life, or (c) whose  
failure to perform when properly used in accordance  
with instructions for use provided in the labeling, can be  
reasonably expected to result in significant injury to the  
user.  
2. A critical component is any component of a life  
support device or system whose failure to perform can  
be reasonably expected to cause the failure of the life  
support device or system, or to affect its safety or  
effectiveness.  
PRODUCT STATUS DEFINITIONS  
Definition of Terms  
Datasheet Identification  
Product Status  
Definition  
Advance Information  
Formative or  
In Design  
This datasheet contains the design specifications for  
product development. Specifications may change in  
any manner without notice.  
Preliminary  
First Production  
This datasheet contains preliminary data, and  
supplementary data will be published at a later date.  
Fairchild Semiconductor reserves the right to make  
changes at any time without notice in order to improve  
design.  
No Identification Needed  
Obsolete  
Full Production  
This datasheet contains final specifications. Fairchild  
Semiconductor reserves the right to make changes at  
any time without notice in order to improve design.  
Not In Production  
This datasheet contains specifications on a product  
that has been discontinued by Fairchild semiconductor.  
The datasheet is printed for reference information only.  
Rev. I15  

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