RFP25N06SM [FAIRCHILD]
Transistor;
| 型号： | RFP25N06SM |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Transistor |
| 文件： | 总8页 (文件大小：408K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RFP25N06, RF1S25N06SM
Data Sheet
July 1999
File Number 1492.4
25A, 60V, 0.047 Ohm, N-Channel Power
MOSFETs
Features
• 25A, 60V
[ /Title These N-Channel power MOSFETs are manufactured using
• rDS(ON) = 0.047Ω
the MegaFET process. This process, which uses feature
(RFP2
5N06,
RF1S2
5N06S
®
• Temperature Compensating PSPICE Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
sizes approaching those of LSI integrated circuits gives
optimum utilization of silicon, resulting in outstanding
performance. They were designed for use in applications
such as switching regulators, switching converters, motor
o
M)
/Sub-
ject
drivers, and relay drivers. These transistors can be operated
directly from integrated circuits.
• 175 C Operating Temperature
• Related Literature
Formerly developmental type TA09771.
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
(25A,
60V,
Ordering Information
Symbol
0.047
Ohm,
N-
Chan-
nel
PART NUMBER
RFP25N06
RF1S25N06SM
PACKAGE
TO-220AB
TO-263AB
BRAND
RFP25N06
F1S25N06
D
NOTE: When ordering use the entire part number. Add the suffix, 9A,
to obtain theTO-263AB variant in tape and reel, e.g. RF1S25N06SM9A.
G
Power
MOS-
FETs)
/Autho
r ()
S
Packaging
/Key-
words
(Inter-
sil
Corpo-
ration,
N-
JEDEC TO- 220AB
JEDEC TO-263AB
SOURCE
DRAIN
GATE
DRAIN
DRAIN
(FLANGE)
(FLANGE)
GATE
SOURCE
Chan-
nel
Power
MOS-
FETs,
TO-
220AB
, TO-
263AB
)
/Cre-
ator ()
©2001 Fairchild Semiconductor Corporation
RFP25N06, RF1S25N06SM Rev. A
RFP25N06, RF1S25N06SMS
o
Absolute Maximum Ratings T = 25 C, Unless Otherwise Specified
C
RFP25N06,
RF1S25N06SM
UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
60
60
20
V
V
V
A
DSS
Drain to Gate Voltage (R
= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
DGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
GS
Continuous Drain Current (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
25
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
(Figure 5)
DM
Single Pulse Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
(Figure 6)
AS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
72
W
D
o
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0.48
W/ C
o
Operating and Storage Junction Temperature Range . . . . . . . . . . . . . . . . . . T , T
J
-55 to 175
C
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . T
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
o
o
300
260
C
C
L
pkg
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
o
o
1. T = 25 C to 150 C.
J
o
Electrical Specifications
T = 25 C, Unless Otherwise Specified
C
PARAMETER
SYMBOL
BV
TEST CONDITIONS
= 250µA, V = 0V (Figure 11)
MIN
TYP
MAX
UNITS
V
Drain to Source Breakdown Voltage
Gate to Source Threshold Voltage
Zero Gate Voltage Drain Current
I
60
2
-
-
-
DSS
D
GS
V
V
V
= V , I = 250µA (Figure 10)
-
4
V
GS(TH)
GS
DS
DS
D
o
I
= 60V
T
T
= 25 C
-
1
µA
µA
nA
Ω
DSS
GSS
C
C
o
V
= 0V
= 150 C
-
-
-
50
GS
Gate to Source Leakage Current
Drain to Source On Resistance
Turn-On Time
I
V
=
20V
-
100
GS
r
I
= 25A, V
= 10V (Figure 9)
-
-
0.047
DS(ON)
D
GS
t
V
R
R
= 30V, I = 12.5A
-
-
60
ns
ON
DD
= 2.4Ω, V
D
GS
= 10V
L
Turn-On Delay Time
Rise Time
t
-
14
30
45
22
-
-
ns
d(ON)
= 10Ω
GS
(Figure 13)
t
-
-
ns
r
Turn-Off Delay Time
Fall Time
t
-
-
ns
d(OFF)
t
-
-
100
80
45
3
ns
f
Turn-Off Time
t
-
ns
OFF
Total Gate Charge
Gate Charge at 10V
Threshold Gate Charge
Input Capacitance
Q
V
V
V
V
= 0 to 20V
= 0 to 10V
= 0 to 2V
V = 48V, I = 25A,
DD D
-
-
nC
nC
nC
pF
pF
pF
g(TOT)
GS
GS
GS
DS
R
= 1.92Ω
L
Q
-
-
g(10)
g(TH)
I
= 0.75mA
g(REF)
(Figure 13)
Q
-
-
C
= 25V, V
= 0V
GS
-
975
330
95
-
-
ISS
OSS
RSS
f = 1MHz
(Figure 12)
Output Capacitance
Reverse Transfer Capacitance
C
C
-
-
-
-
o
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
R
(Figure 3)
-
2.083
62
C/W
θJC
θJA
o
R
-
-
C/W
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Reverse Recovery Time
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
1.5
UNITS
V
V
I
I
= 25A
-
-
-
-
SD
SD
SD
t
= 25A, dI /dt = 100A/µs
SD
125
ns
rr
©2001 Fairchild Semiconductor Corporation
RFP25N06, RF1S25N06SM Rev. A
RFP25N06, RF1S25N06SM
Typical Performance Curves Unless Otherwise Specified
30
25
20
15
1.2
1.0
0.8
0.6
0.4
0.2
0
10
5
0
25
175
50
0
25
75
100
125
o
150
50
75
T , CASE TEMPERATURE ( C)
C
100
150
125
175
o
T
, CASE TEMPERATURE ( C)
C
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
1
0.5
0.2
0.1
0.1
P
DM
0.05
0.02
0.01
t
1
t
2
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t /t
1 2
x R
PEAK T = P
x Z
+ T
C
J C
C
J
θ
J
DM
θ
0.01
10
-5
-4
10
-3
10
-2
10
-1
10
0
1
10
10
t
, RECTANGULAR PULSE DURATION (s)
1
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
200
100
o
o
T
T
= 25 C
V
= 20V
FOR TEMPERATURES ABOVE 25 C
DERATE PEAK CURRENT
CAPABILITY AS FOLLOWS:
C
J
GS
= MAX RATED
200
100
SINGLE PULSE
175 – T
C
V
= 10V
GS
I = I
-----------------------
25
150
100µs
10
OPERATION IN THIS
AREA MAY BE
1ms
LIMITED BY r
DS(ON)
10ms
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
100ms
DC
o
T
= 25 C
C
1
10
10
, DRAIN TO SOURCE VOLTAGE (V)
100
1
-5
10
-4
10
-3
10
-2
10
-1
10
0
1
10
10
V
DS
t, PULSE WIDTH (s)
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. PEAK CURRENT CAPABILITY
©2001 Fairchild Semiconductor Corporation
RFP25N06, RF1S25N06SM Rev. A
RFP25N06, RF1S25N06SM
Typical Performance Curves Unless Otherwise Specified (Continued)
100
70
V
= 20V
V
= 10V
V
= 8V
GS
GS
GS
60
50
40
30
20
10
0
PULSE DURATION = 80µs
o
STARTING T = 25 C
DUTY CYCLE = 0.5% MAX
J
o
T
= 25 C
C
V
= 7V
= 6V
10
GS
o
STARTING T = 150 C
J
V
GS
If R = 0
AV
If R ≠ 0
t
= (L)(I )/(1.3*RATED BV
- V )
DD
AS DSS
t
= (L/R)ln[(I *R)/(1.3*RATED BV
AS
-V ) +1]
V
= 5V
AV
DSS DD
GS
V
= 4.5V
GS
1
0.01
1
0.1
10
2
0
4
6
8
200
200
t
,TIME IN AVALANCHE (µs)
AV
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
NOTE: Refer to Intersil Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
FIGURE 7. SATURATION CHARACTERISTICS
2.5
2.0
1.5
70
PULSE DURATION = 80µs
o
-55 C
V
= 15V
o
DD
25 C
DUTY CYCLE = 0.5% MAX
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
60
50
40
30
V
= 10V, I = 25A
GS D
o
175 C
1.0
0.5
0
20
10
0
0
2
4
6
8
10
-80
-40
0
40
80
120
160
o
V
, GATE TO SOURCE VOLTAGE (V)
T , JUNCTION TEMPERATURE ( C)
GS
J
FIGURE 8. TRANSFER CHARACTERISTICS
FIGURE 9. NORMALIZED DRAINTO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
2.0
1.5
2.0
1.5
V
= V
DS
GS
I
= 250µA
D
I
= 250µA
D
1.0
0.5
0
1.0
0.5
0
-80
-40
0
40
80
120
160
-80
-40
0
40
80
120
200
160
o
o
T , JUNCTION TEMPERATURE ( C)
T , JUNCTION TEMPERATURE ( C)
J
J
FIGURE 10. NORMALIZED GATETHRESHOLDVOLTAGE vs
JUNCTION TEMPERATURE
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
©2001 Fairchild Semiconductor Corporation
RFP25N06, RF1S25N06SM Rev. A
RFP25N06, RF1S25N06SM
Typical Performance Curves Unless Otherwise Specified (Continued)
10
60
1600
V
= BV
DSS
V
= 0V, f = 1MHz
V
= BV
DD
GS
ISS
DD DSS
C
C
C
= C
+ C
GS GD
= C
RSS
OSS
GD
45
30
15
0
C
7.5
5.0
ISS
= C
DS
+ C
GD
1200
800
400
0
0.75 BV
DSS
C
OSS
0.50 BV
0.25 BV
DSS
DSS
2.5
0
R
= 2.4Ω
g(REF)
L
I
= 0.75mA
C
RSS
V
= 10V
GS
I
I
g(REF)
g(REF)
t,TIME (µs)
--------------------
--------------------
20
80
0
5
V
10
15
20
25
I
I
g(ACT)
g(ACT)
, DRAIN TO SOURCE VOLTAGE (V)
DS
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 13. NORMALIZED SWITCHINGWAVEFORMS FOR
CONSTANT GATE CURRENT
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
Test Circuits and Waveforms
V
DS
BV
DSS
L
t
P
V
DS
I
VARY t TO OBTAIN
P
AS
+
-
V
DD
R
REQUIRED PEAK I
G
AS
V
DD
V
GS
DUT
t
P
I
AS
0V
0
0.01Ω
t
AV
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
t
t
ON
OFF
t
d(OFF)
t
d(ON)
V
DS
t
t
f
r
V
DS
90%
90%
R
L
V
GS
+
10%
10%
0
0
V
DD
-
DUT
90%
50%
R
GS
V
GS
50%
PULSE WIDTH
10%
V
GS
FIGURE 16. SWITCHING TIME TEST CIRCUIT
FIGURE 17. RESISTIVE SWITCHING WAVEFORMS
©2001 Fairchild Semiconductor Corporation
RFP25N06, RF1S25N06SM Rev. A
RFP25N06, RF1S25N06SM
Test Circuits and Waveforms (Continued)
V
DS
V
DD
Q
R
g(TOT)
L
V
DS
V
= 20V
GS
V
Q
GS
g(10)
+
-
V
DD
V
= 10V
V
GS
GS
DUT
V
= 2V
GS
I
0
g(REF)
Q
g(TH)
I
g(REF)
0
FIGURE 18. GATE CHARGE TEST CIRCUIT
FIGURE 19. GATE CHARGE WAVEFORM
©2001 Fairchild Semiconductor Corporation
RFP25N06, RF1S25N06SM Rev. A
RFP25N06, RF1S25N06SM
PSPICE Electrical Model
.SUBCKT RFP25N06 2 1 3 ;
rev 8/19/94
CA 12 8 1.83e-9
CB 15 14 1.98e-9
CIN 6 8 9.7e-10
DPLCAP
5
DRAIN
2
10
DBODY 7 5 DBDMOD
LDRAIN
DBREAK 5 11 DBKMOD
DPLCAP 10 5 DPLCAPMOD
RSCL1
DBREAK
RSCL2
51
+
5
51
EBREAK 11 7 17 18 65.9
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTO 20 6 18 8 1
ESCL
-
50
+
DBODY
6
8
11
RDRAIN
E
SG
17
18
16
EBREAK
+
VTO
+
-
IT 8 17 1
MOS2
EVTO
GATE
21
+
-
6
9
20
GATE
18
8
LDRAIN 2 5 1e-9
LGATE 1 9 4.92e-9
LSOURCE 3 7 4.5e-9
MOS1
8
1
L
R
GATE
RIN
CIN
LSOURCE
RSOURCE
7
3
MOS1 16 6 8 8 MOSMOD M = 0.99
MOS2 16 21 8 8 MOSMOD M = 0.01
SOURCE
S1A
S2A
RBREAK 17 18 RBKMOD 1
RDRAIN 50 16 RDSMOD 1.1e-3
RGATE 9 20 2.88
12
RBREAK
15
13
8
14
13
17
18
S1B
CA
S2B
13
RIN 6 8 1e9
RSCL1 5 51 RSCLMOD 1e-6
RSCL2 5 50 1e3
RSOURCE 8 7 RDSMOD 20.3e-3
RVTO 18 19 RVTOMOD 1
RVTO
19
VBAT
CB
+
IT
14
+
5
8
6
8
EGS
EDS
+
-
-
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 8 19 DC 1
VTO 21 6 0.764
ESCL 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)*1e6/108,6))}
.MODEL DBDMOD D (IS = 2.32e-13 RS = 5.72e-3 TRS1 = 2.56e-3 TRS2 = -5.13e-6 CJO = 1.18e-9 TT = 5.62e-8)
.MODEL DBKMOD D (RS = 2.00e-1 TRS1 = 3.33e-4 TRS2 = 2.68e-6)
.MODEL DPLCAPMOD D (CJO = 6.55e-10 IS = 1e-30 N = 10)
.MODEL MOSMOD NMOS (VTO = 3.89 KP = 15.03 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL RBKMOD RES (TC1 = 1.04e-3 TC2 = -1.04e-6)
.MODEL RDSMOD RES (TC1 = 5.85e-3 TC2 = 1.77e-5)
.MODEL RSCLMOD RES (TC1 = 2.0e-3 TC2 = 1.5e-6)
.MODEL RVTOMOD RES (TC1 = -5.35e-3 TC2 = -3.77e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5.04 VOFF= -3.04)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.04 VOFF= -5.04)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.02 VOFF= 1.98)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 1.98 VOFF= -3.02)
.ENDS
NOTE: For further discussion of the PSPICE model consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global
Temperature Options; written by William J. Hepp and C. Frank Wheatley.
©2001 Fairchild Semiconductor Corporation
RFP25N06, RF1S25N06SM Rev. A
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
PACMAN™
POP™
PowerTrench
QFET™
QS™
QT Optoelectronics™
Quiet Series™
SILENT SWITCHER
SMART START™
Star* Power™
Stealth™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic™
UHC™
FAST
FASTr™
GlobalOptoisolator™
GTO™
HiSeC™
ISOPLANAR™
LittleFET™
MicroFET™
MICROWIRE™
OPTOLOGIC™
OPTOPLANAR™
ACEx™
Bottomless™
CoolFET™
CROSSVOLT™
DenseTrench™
DOME™
UltraFET™
VCX™
EcoSPARK™
E2CMOSTM
EnSignaTM
FACT™
FACT Quiet Series™
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TOANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOTASSUMEANY LIABILITYARISING OUT OF THEAPPLICATION OR USE OFANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUTTHE EXPRESS WRITTENAPPROVALOF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Obsolete
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. H
相关型号：
©2020 ICPDF网 联系我们和版权申明