SG6516_08 [FAIRCHILD]
PC Power Supply Supervisors; PC电源监控
| 型号： | SG6516_08 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | PC Power Supply Supervisors |
| 文件： | 总12页 (文件大小：693K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 2008
SG6516
PC Power Supply Supervisors
Features
Description
The SG6516 is designed to provide the supply voltage,
current supervisor, remote on/off (PSON), power good
(PGO) indicator, and fault protection (FPO) functions for
switching power systems.
Two 12V Sense Input Pins: VS12 and VS12B
Over-Voltage Protection (OVP) for 3.3V, 5V,
and two 12V
Over-Current Protection (OCP) for 3.3V, 5V,
and two 12V
For supervisory functions, it provides the over-voltage
protection (OVP) for 3.3V, 5V, and two 12V; over-
current protection (OCP) for 3.3V, 5V, and two 12V;
under-voltage protection (UVP) for 3.3V, 5V, and two
12V. When 3.3V, 5V, or 12V voltage decreases to 2.3V,
3.5V, and 9V, respectively, the under-voltage protection
function is enabled. FPO is set HIGH to turn off the
PWM controller IC. The voltage difference across
external current shunt is used for OCP functions. An
external resistor can be used to adjust the protection
threshold. An additional protection input pin provides
the flexibility for designing protection circuits.
Under-Voltage Protection (UVP) for 3.3V, 5V,
and two 12V
Open-Drain Output for PGO and FPO Pins
300ms Power-Good Delay
2.8ms PSON Control to FPO Turn-off Delay
48ms PSON Control Delay
No Lock-up During the Fast AC Power On/Off
Wide Supply Voltage Range: 4V to 15V
The power supply is turned on after a 48ms delay when
PSON signal is set from HIGH to LOW. To turn off the
power supply, the PSON signal is set from LOW to
HIGH with a delay of 48ms. The PGI circuitry provides a
power-down warning signal for PGO. When PGI input is
lower than the internal 1.25V reference voltage, the
PGO signal is pulled LOW.
Applications
Switch-Mode Power Supplies with Active PFC
Servo System Power Supplies
PC-ATX Power Supplies
Ordering Information
Packing
Part Number Operating Temperature Range
Package
Method
SG6516DZ
SG6516SZ
-40°C to +85°C
-40°C to +85°C
16-pin Dual In-Line Package (DIP)
16-pin Small Outline Package (SOP)
Rail
Tape & Reel
All packages are lead free per JEDEC: J-STD-020B standard.
© 2007 Fairchild Semiconductor Corporation
SG6516 • Rev. 1.0.2
www.fairchildsemi.com
Application Diagram
Figure 1.
Typical Application
© 2007 Fairchild Semiconductor Corporation
SG6516 • Rev. 1.0.2
www.fairchildsemi.com
2
Block Diagram
Figure 2. Function Block Diagram
© 2007 Fairchild Semiconductor Corporation
SG6516 • Rev. 1.0.2
www.fairchildsemi.com
3
Pin Configuration
Figure 3. Pin Configuration(Top View)
Pin Definitions
Pin #
Name
PGI
Description
1
2
Power Good Input. For ATX SMPS, it detects AC line voltage through the main transformer.
Ground.
GND
Fault Protection Output. Output signal to control the primary PWM IC through an opto-
coupler. When FPO is low, the PWM IC is enabled.
3
4
FPO
Remote on/off logic input from CPU or main board. The power supply is turned on/off after
a 48ms delay.
PSON
12V over-current protection sense input. For typical applications, this pin is connected to the
positive end of a current shunt through one resistor. When the voltage on IS12 is higher than
that of VS12 by 5mV, OCP is enabled.
5
6
IS12
RI
Reference setting. One external resistor, RI, connected between the RI and GND pins,
determines a reference current, IREF=1.25/RI, for OCP programming.
7
8
VS12B
IS5
Second 12V over/under-voltage control sense input.
5V over-current protection sense input.
9
IS33
VS12
VS33
VS5
3.3V over-current protection sense input.
12V over/under-voltage control sense input.
3.3V over/under-voltage control sense input.
5V over/under-voltage control sense input.
10
11
12
Supply voltage: 4.2V ~ 15V. For ATX SMPS, it is connected to 5V-standby and 12V through
diodes, respectively.
13
14
VDD
PGO
Power-Good logic Output, 0 or 1 (open-drain). Power good=1 means that the power supply is
good for operation. The power-good delay is 300ms.
© 2007 Fairchild Semiconductor Corporation
SG6516 • Rev. 1.0.2
www.fairchildsemi.com
4
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only. All voltage values, except differential voltage, are
given with respect to GND pin.
Symbol
Parameter
Min.
Max.
16
Unit
V
VDD
DC Supply Voltage
Input Voltage
PSON, PGI, VS5, IS5, VS33, IS33
VS12, VS12B, IS12
FPO, PGO
-0.3
-0.3
-0.3
-40
7.0
V
VIN
15.0
8.0
V
VOUT
TJ
Output Voltage
V
Operating Junction Temperature
+125
+150
+260
3.0
°C
°C
°C
KV
V
TSTG
TL
Storage Temperature Range
-55
Lead Temperature (Soldering)
Electrostatic Discharge Capability, Human Body Model
Electrostatic Discharge Capability, Machine Model
ESD
200
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Min.
Typ.
Max.
Unit
TA
Operating Ambient Temperature
-40
+85
°C
© 2007 Fairchild Semiconductor Corporation
SG6516 • Rev. 1.0.2
www.fairchildsemi.com
5
Electrical Characteristics
VDD=5V, TA=25°C, unless otherwise noted.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
VDD Section
VDD
IDD1
IDD2
tR
DC Supply Voltage
Supply Current 1
4.2
15.0
2.6
V
PSON=LOW
PSON=HIGH
1.7
1.0
mA
mA
ms
V
Supply Current 2
1.5
Supply Voltage Rising Time
VDD Start Threshold Voltage
1
VST
4.2
Over-Voltage (OVP) and Over-Current (OCP) Protections
VS33
3.7
5.7
3.9
6.1
4.1
6.5
VOVP
Over-Voltage Protection
V
VS5
VS12, VS12B
13.2
13.8
14.4
Ratio of Current-Sense Sink Current
to Current-Sense Setting Pin (RI)
Source Current
RI=18.5kΩ ~ 75kΩ
IREF
7.6
-3
8.0
8.4
VOFFSET OCP Comparator Input Offset Voltage
ILKG-FPO Leakage Current (FPO)
3
5
mV
µA
V
FPO=5V
VOL-FPO Low Level Output Voltage (FPO)
I
SINK 20mA
0.4
tOVP
tOCP
VRI
IRI
OVP Delay Time
OCP Delay Time
RI Pin Voltage
33
12.5
75
110
µs
ms
V
20.0
1.25
27.5
1.01•Typ.
62.5
0.98•Typ.
12.5
Output Current RI
µA
0.6V < PGI < 1.25V;
FPO=Low
tST-OCP
Start-up OCP / UVP Protection Time
49
75
114
ms
Under-Voltage Protection and PGI, PGO
VPGI_1
VPGI_2
Input Threshold Voltage
Input Threshold Voltage
PGI 1
0.98•Typ.
0.96•Typ.
2.1
1.25
0.60
2.3
3.5
9.0
75
1.02•Typ.
1.03•Typ.
2.5
V
V
PGI 2
VS33
VUVP
Under-Voltage Protection
V
VS5
3.3
3.7
VS12, VS12B
PGI>0.6V
PGI>1.25V
PGO=5V
VDD=12V; ISINK 10mA
8.5
9.5
tOND
tUVP
Under Voltage Turn-on Delay
UVP Delay
49
114
ms
ms
µA
V
2.4
3.2
4.0
ILKG-PGO Leakage Current (PGO)
5
VOL-PGO Low Level Output Voltage (PGO)
0.4
tPG
Timing PG Delay
200
90
300
150
450
ms
tND1
Noise Deglitch Time
210
µs
PSON Control
IPSON Input Pull-up Current
VIH
PSON=0V
120
48
µA
V
High-level Input Voltage
Low-level Input Voltage
2
VIL
0.8
67
V
PSON LOW to FPO
LOW
34
tPSON
Timing PSON to On/Off
ms
ms
PSON HIGH to PGO
LOW
34
48
67
tPSOFF
Timing PGO LOW to FPO HIGH
1.6
2.8
4.5
© 2007 Fairchild Semiconductor Corporation
SG6516 • Rev. 1.0.2
www.fairchildsemi.com
6
Functional Description
The SG6516 provides over-current protection for the
3.3V, 5V, and two 12V rails. Whenever an OCP
condition occurs at any of the voltage rails, PGO is
LOW and FPO is open. The internal OCP comparators
have a very small offset voltage (±3mV). The sink
currents of IS33, IS5, and IS12 are eight times the
current at the RI pin. The current at the RI pin is VRI/RI.
The following example demonstrates how to set the
over-current protection. If I1×R1 > IRI × R2, OCP is active.
If R1=5mΩ, RI=30KΩ, and the OCP active level is 35A;
the R2 resistor is:
I1 × R1
IRI × 8
R2
=
= 525Ω
Figure 4. OCP Set-up
(1)
where C is bypass noise, with a suggested value
between 1µF ~ 2.2µF
© 2007 Fairchild Semiconductor Corporation
SG6516 • Rev. 1.0.2
www.fairchildsemi.com
7
Timing Chart
Figure 5. Timing Diagram
© 2007 Fairchild Semiconductor Corporation
SG6516 • Rev. 1.0.2
www.fairchildsemi.com
8
Typical Performance Characteristics
1.900
1.800
1.700
1.600
1.500
1.400
8.500
8.300
8.100
7.900
7.700
7.500
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Temperature (℃)
-40
℃
-25
℃
-10
5
℃
20
35
50
65
80
℃
95
110 125
℃ ℃
℃
℃
℃
℃
℃
℃
Temperature (℃)
Figure 6. IREF vs. TA
Figure 7. IDD1 vs. TA
28.000
26.000
24.000
22.000
20.000
18.000
16.000
2.000
1.200
0.400
-0.400
-1.200
-2.000
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Temperature (℃)
-40℃ -25℃ -10℃ 5℃
20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Temperature (℃)
Figure 8. VOFFSET vs. TA
Figure 9. tOCP vs. TA
1.300
1.300
1.280
1.260
1.240
1.220
1.200
1.280
1.260
1.240
1.220
1.200
-40℃ -25℃ -10℃ 5℃
20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Temperature (℃)
-40℃ -25℃ -10℃ 5℃
20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Temperature (℃)
Figure 10. VRI vs. TA
Figure 11. VPGI vs. TA
© 2007 Fairchild Semiconductor Corporation
SG6516 • Rev. 1.0.2
www.fairchildsemi.com
9
Physical Dimensions
Figure 12. 14-PDIP
Millimeter
Inch
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
A
5.334
0.210
A1
A2
b
0.381
3.175
0.015
0.125
3.302
1.524
0.457
19.177
7.620
6.299
2.540
3.302
9.017
7˚
3.429
0.130
0.060
0.018
0.755
0.300
0.248
0.100
0.130
0.355
7˚
0.135
b1
D
18.669
6.121
19.685
6.477
0.735
0.241
0.775
0.255
E
E1
e
L
2.921
8.509
0˚
3.810
9.525
15˚
0.115
0.335
0˚
0.150
0.375
15˚
eB
θ˚
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
© 2007 Fairchild Semiconductor Corporation
SG6516 • Rev. 1.0.2
www.fairchildsemi.com
10
Physical Dimensions (Continued)
Figure 13. 14-SOIC
Millimeter
Symbol
Inch
Min.
Typ.
Max.
1.753
0.254
1.499
Min.
Typ.
Max.
0.069
0.010
0.059
A
A1
A2
b
1.346
0.101
1.244
0.053
0.004
0.049
0.406
0.203
0.016
0.008
c
D
E
e
9.804
3.810
10.008
3.988
0.386
0.150
0.394
0.157
1.270
0.050
H
L
5.791
0.406
6.198
1.270
0.228
0.016
0.244
0.050
F
0.381X45˚
0.015X45˚
y
0.101
0.004
θ˚
0˚
8˚
0˚
8˚
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
© 2007 Fairchild Semiconductor Corporation
SG6516 • Rev. 1.0.2
www.fairchildsemi.com
11
© 2007 Fairchild Semiconductor Corporation
SG6516 • Rev. 1.0.2
www.fairchildsemi.com
12
相关型号：
SG6610WN (新产品)
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