SG6901 [FAIRCHILD]
CCM PFC/Flyback PWM Combination Controller; CCM PFC / PWM反激组合控制器
| 型号： | SG6901 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | CCM PFC/Flyback PWM Combination Controller |
| 文件： | 总19页 (文件大小：715K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 2009
SG6901A
CCM PFC/Flyback PWM Combination Controller
Features
Description
The highly integrated SG6901A is designed for power
supplies with boost PFC and flyback PWM. It requires
very few external components to achieve versatile
protections. It is available in a 20-pin SOP package.
Interleaved PFC/PWM Switching
Low Startup and Operating Current
Innovative Switching Charge Multiplier Divider
A proprietary interleave-switching feature synchronizes
the PFC and PWM stages and reduces switching noise.
Multi-vector Control for Improved PFC Output
Transient Response
For PFC stage, the proprietary multi-vector control
scheme provides a fast transient response in a low-
bandwidth PFC loop, in which the overshoot and
undershoot of the PFC voltage are clamped. If the
feedback loop is broken, the SG6901A shuts off PFC to
prevent extra-high voltage on output.
Average-Current-Mode Control for PFC
Programmable Two-Level PFC Output Voltage
Protections
PFC and PWM Feedback Open-Loop Protection
Cycle-by-Cycle Current Limiting for PFC/PWM
Slope Compensation for PWM
For the flyback PWM, the synchronized slope
compensation ensures the stability of the current loop
under continuous-conduction-mode operation. Built-in
line-voltage compensation maintains constant output-
power limit. Hiccup operation during output overloading
is also guaranteed.
H/L Line Over-Power Compensation for PWM
Brownout Protection
Over-Temperature Protection (OTP)
In addition, SG6901A provides protection functions,
such as brownout and RI pin open/short protection.
Applications
Switching Power Supplies with Active PFC and
Standby Power
High-Power Adaptors
Ordering Information
Operating
Temperature Range
Packing
Eco
Status
Part Number
Package
Method
20-Lead, Small Outline Integrated
SG6901ASZ
-30°C to +85°C
RoHS
Tape & Reel
Circuit (SOIC), JEDEC
MS013, .300 inch, Wide Body
For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
© 2008 Fairchild Semiconductor Corporation
SG6901A • Rev. 1.0.2
www.fairchildsemi.com
Application Circuit
Figure 1. Typical Application
© 2008 Fairchild Semiconductor Corporation
SG6901A • Rev. 1.0.2
www.fairchildsemi.com
2
Block Diagram
Figure 2. Block Diagram
© 2008 Fairchild Semiconductor Corporation
SG6901A • Rev. 1.0.2
www.fairchildsemi.com
3
Marking Information
T- S=SOP
P- Z=Lead Free
Null=regular package
XXXXXXXX- Wafer Lot
Y: Year; WW: Week
V: Assembly Location
Figure 3. Top Mark
Pin Configuration
Figure 4. Pin Configuration
© 2008 Fairchild Semiconductor Corporation
SG6901A • Rev. 1.0.2
www.fairchildsemi.com
4
Pin Definitions
Pin #
Name
Description
Line voltage detection. The pin is used for PFC multiplier, RANGE control of PFC output
voltage, and brownout protection. For brownout protection, the controller is disabled after a
delay time when the VRMS voltage drops below a threshold.
1
VRMS
Reference setting. One resistor connected between RI and ground determines the switching
frequency. The switching frequency is equal to [1560 / RI] KHz, where RI is in KΩ. For example,
if RI is equal to 24KΩ, the switching frequency is 65KHz.
2
3
RI
Over-temperature protection. A constant current is output from this pin. An external NTC
thermistor must be connected from this pin to ground. The impedance of the NTC thermistor
decreases whenever the temperature increases. Once the voltage of the OTP pin drops below
the OTP threshold, the SG6901A is disabled.
OTP
PFC current amplifier output. The signal from this pin is compared with an internal sawtooth
to determine the pulse width for PFC gate drive.
4
5
IEA
The inverting input of the PFC current amplifier. Proper external compensation circuits result
in excellent input power factor via average-current-mode control.
IPFC
The non-inverting input of the PFC current amplifier and the output of multiplier. Proper
external compensation circuits results in excellent input power factor via average-current-mode
control.
6
7
IMP
ISENSE Current limit. A resistor from this pin to GND sets the current limit.
The control input for voltage-loop feedback of PWM stage. It is internally pulled high
8
FBPWM
through a 6.5kΩ resistance. Usually an external opto-coupler from secondary feedback circuit is
connected to this pin.
The current-sense input for the flyback PWM. Via a current sense resistor, this pin provides
the control input for peak-current-mode control and cycle-by-cycle current limiting.
9
IPWM
AGND
10
Signal ground.
Soft start. During startup, the SS pin charges an external capacitor with a 50µA (RI=24KΩ)
constant current source. The voltage on FBPWM is clamped by SS during startup. In the event
of a protection condition occurring and/or PWM being disabled, the SS pin is quickly
discharged.
11
SS
The totem-pole output drive for the flyback PWM MOSFET. This pin is internally clamped under
17V to protect the MOSFET.
12
13
14
15
16
OPWM
GND
Power ground.
The totem-pole output drive for the PFC MOSFET. This pin is internally clamped under 17V
to protect the MOSFET.
OPFC
VDD
The power supply pin.
The RANGE pin has high impedance whenever the VRMS voltage is lower than a threshold.
The PFC output voltage at low line can be reduced to improve efficiency.
RANGE
The PFC stage over-voltage input. The comparator disables the PFC output driver if the
voltage at this input exceeds a threshold. This pin can be connected to FBPFC or it can be
connected to the PFC boost output through a divider network.
17
18
OVP
The feedback input for PFC voltage loop. The inverting input of PFC error amplifier. This pin
is connected to the PFC output through a divider network.
FBPFC
The error amplifier output for PFC voltage feedback loop. A compensation network (usually
a capacitor) is connected between this pin and ground. A large capacitor value results in a
narrow bandwidth and improves the power factor.
19
20
VEA
IAC
This input is used to provide current reference for the multiplier.
© 2008 Fairchild Semiconductor Corporation
SG6901A • Rev. 1.0.2
www.fairchildsemi.com
5
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Symbol
VDD
IAC
Parameter
Min.
Max.
25
Unit
V
DC Supply Voltage
Input AC Current
OPWM, OPFC, IAC
Others
2
mA
V
VHIGH
VLOW
PD
-0.3
-0.3
25.0
7.0
V
Power Dissipation at TA< 50℃
1.15
+125
+150
+23.64
+260
4.5
W
TJ
Operating Junction Temperature
Storage Temperature Range
-40
-55
°C
°C
°C/W
°C
KV
V
TSTG
ӨJC
Thermal Resistance (Junction-to-Case)
Lead Temperature (Soldering)
TL
Human Body Model, JESD22-A114
Machine Model, JESD22-A115
ESD
Electrostatic Discharge Capability
250
Notes:
1. All voltage values, except differential voltage, are given with respect to GND pin.
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Operating Ambient Temperature
Min.
Max.
Unit
TA
-30
+85
°C
© 2008 Fairchild Semiconductor Corporation
SG6901A • Rev. 1.0.2
www.fairchildsemi.com
6
Electrical Characteristics
VDD=15V and TA=25°C unless otherwise specified.
Symbol
Parameter
Conditions
Min.
Typ.
Max. Units
VDD SECTION
VDD-OP
IDD-ST
Continuously Operating Voltage
Startup Current
20
25
V
0V < VDD < VDD-ON
10
6
µA
VDD=15V; OPFC,
OPWM Open; RI=24KΩ
IDD-OP
Operating Current
10
mA
VDD-ON
VDD-OFF
VDD-OVP
tD-VDDOVP
Start Threshold Voltage
Minimum Operating Voltage
VDD OVP Threshold
11
9
12
10
13
11
V
V
23.5
8
24.5
25.5
25
V
Debounce Time of VDD OVP
µs
OSCILLATOR SECTION
fOSC
RI
PWM Frequency
RI=24KΩ
62
65
68
KHz
RI Pin Resistance Range
RI Pin Open Protection
15.6
47.0
KΩ
If RI>RI-OPEN, SG6901A
Turns Off
RI-OPEN
200
2
KΩ
KΩ
If RI<RI-SHORT
SG6901A Turns Off
,
RI-SHORT
RI Pin Short Protection
VRMS SECTION (for UVP and RANGE)
RMS AC Voltage Under-Voltage
VRMS-UVP-1
0.75
0.80
0.85
V
V
Protection Threshold (with tUVP delay)
VRMS-UVP- VRMS-
VRMS-
VRMS-UVP-2 Recovery Level on VRMS
+
+
+
1
UVP-1
UVP-1
0.16V
0.18V
0.2V
When UVP Occurs, Interval from PFC
Off to PWM Off
tUVP-
Min+9
tUVP-
Min+14
tD-PWM
ms
ms
V
tUVP
Under-Voltage Protection Delay Time
150
195
240
VRMS-H
High VRMS Threshold for RANGE
Comparator
1.90
1.95
2.00
VRMS-L
Low VRMS Threshold for RANGE
Comparator
1.55
140
1.60
170
1.65
V
tRANGE
VOL
Range-Enable Delay Time
200
0.5
ms
V
Output Low Voltage of RANGE Pin
Io=1mA
IOH
Output High Leakage Current of
RANGE Pin
RANGE=5V
50
nA
Continued on the following page…
© 2008 Fairchild Semiconductor Corporation
SG6901A • Rev. 1.0.2
www.fairchildsemi.com
7
Electrical Characteristics
VDD=15V and TA=25°C unless otherwise specified.
Symbol
Parameter
Conditions
Min.
Typ. Max. Units
PFC STAGE
Voltage Error Amplifier
VREF
Av
Reference Voltage
Open-Loop Gain
2.95
3.00
60
3.05
V
dB
KΩ
V
Zo
Output Impedance
110
3.25
OVPPFC
PFC Over-Voltage Protection (OVP Pin)
3.20
60
3.30
120
PFC Feedback Voltage Protection
Hysteresis
△OVPPFC
90
mV
tOVP-PFC
VFBPFC-H
GFBPFC-H
VFBPFC-L
GFBPFC-L
IFBPFC-L
Debounce Time of PFC OVP
Clamp-High Feedback Voltage
Clamp-High Gain
40
70
3.15
0.5
120
µs
V
3.10
3.20
µA/mV
V
Clamp-Low Feedback Voltage
Clamp-Low Gain
2.75
2.85
6.5
2.90
mA/mV
mA
µA
Maximum Source Current
Maximum Sink Current
1.5
70
2.0
IFBPFC-H
110
0.40
70
UVPFBPFC PFC Feedback Under-Voltage Protection
tUVP-FBPFC Debounce Time of PFC UVP
CURRENT ERROR AMPLIFIER
0.35
40
0.45
120
V
µs
VOFFSET
AI
Input Offset Voltage ((-) > (+))
Open-Loop Gain
8
mV
dB
MHz
dB
V
60
1.5
70
BW
Unit Gain Bandwidth
CMRR
Common Mode Rejection Ratio
VCM=0 to +1.5V
VOUT-HIGH Output High Voltage
3.2
VOUT-LOW
IMR1, IMR2
Output Low Voltage
0.2
70
V
RI=24KΩ
(IMR=20+IRI•0.8)
Reference Current Source
50
3
µA
IL
Maximum Source Current
Maximum Sink Current
mA
mA
IH
0.25
Continued on the following page…
© 2008 Fairchild Semiconductor Corporation
SG6901A • Rev. 1.0.2
www.fairchildsemi.com
8
Electrical Characteristics
VDD=15V and TA=25°C unless otherwise specified.
Symbol
Parameter
Conditions
Min.
Typ. Max. Units
PEAK CURRENT LIMIT
IP
Constant Current Output
RI=24KΩ
90
100
110
µA
V
Peak Current Limit Threshold
Voltage Cycle-by-Cycle Limit (VSENSE
VRMS=1.05V
VRMS=3V
0.15
0.20
0.25
VPK
0.35
270
0
0.40
350
0.45
V
< VPK
)
tPD-PFC
tLEB-PFC
Propagation Delay
200
450
ns
ns
Leading-Edge Blanking Time
MULTIPLIER
IAC
Input AC Current
Multiplier Linear Range
360
280
µA
µA
IMO–max
Maximum Multiplier Current Output
RI=24KΩ
250
250
VRMS=1.05V; IAC=90µA;
Multiplier Current Output (Low-line,
High-Power)
IMO-1
200
µA
VEA=7.5V; RI=24KΩ
VRMS=3V; IAC=264µA;
Multiplier Current Output (High-line,
High-Power)
IMO–2
VIMP
65
85
µA
V
VEA=7.5V; RI=24KΩ
Voltage of IMP Open
3.4
3.9
4.4
PFC OUTPUT DRIVER
VZ
Output Voltage Maximum (Clamp)
VDD=20V
16
18
V
V
VOL-PFC
Output Voltage Low
VDD=15V; IO=100mA
1.5
Interval OPFC Lags Behind OPWM
at Startup
tPFC
VOH-PFC
tR-PFC
9.0
8
11.5
14.0
120
ms
V
Output Voltage High
Rising Time
VDD=13V; IO=100mA
VDD=15V; CL=5nF;
O/P=2V to 9V
40
70
60
ns
VDD=15V; CL=5nF;
tF-PFC
Falling Time
40
93
110
98
ns
%
O/P=9V to 2V
DCYMAX
PWM STAGE
FBPWM
Maximum Duty Cycle
FB to Current Comparator
Attenuation
Av-PWM
2.5
3.1
3.5
V/V
ZFB
IFB
Input Impedance
4
5
7
KΩ
mA
V
Maximum Source Current
0.8
4.2
1.2
4.5
1.5
4.8
FBOPEN-LOOP PWM Open-Loop Protection Voltage
PWM Open-Loop Protection Delay
tOPEN-PWM
Time
45
56
70
ms
ms
tOPEN-PWM- Interval of PWM Open-Loop
450
600
750
Protection Reset
Hiccup
Continued on the following page…
© 2008 Fairchild Semiconductor Corporation
SG6901A • Rev. 1.0.2
www.fairchildsemi.com
9
Electrical Characteristics
VDD=15V and TA=25°C unless otherwise specified.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
PWM CURRENT SENSE
Propagation Delay to
Output
tPD-PWM
VLIMIT-1
VLIMIT-2
tLEB-PWM
VDD=15V, OPWM<=9V
RANGE=Open
60
120
0.75
0.70
450
ns
V
Peak Current Limit
Threshold Voltage1
0.65
0.60
270
0.70
0.65
350
Peak Current Limit
Threshold Voltage2
RANGE=Ground
V
Leading-Edge Blanking
Time
ns
△VS=△VSLOPE x (Ton/T)
△VS: Compensation
Voltage Added to Current
Sense
△VSLOPE
Slope Compensation
0.45
0.50
16
0.55
V
V
PWM OUTOUT DRIVER
Output Voltage Maximum
(Clamp)
VZ-PWM
VDD=20V
18
VOL-PWM
VOH-PWM
Output Voltage Low
Output Voltage High
VDD=15V; IO=100mA
VDD=13V; IO=100mA
1.5
V
V
8
VDD=15V; CL=5nF;
O/P=2V to 9V
tR-PWM
tF-PWM
Rising Time
Falling Time
30
60
120
ns
VDD=15V; CL=5nF;
O/P=9V to 2V
30
73
50
78
110
83
ns
%
DCYMAXPWM Maximum Duty Cycle
OTP SECTION
IOTP
VOTP-ON
VOTP-OFF
tOTP
OTP Pin Output Current
Recovery Level on OTP
OTP Threshold Voltage
OTP Debounce Time
RI=24KΩ
90
1.35
1.15
8
100
1.40
1.20
110
1.45
1.25
25
µA
V
V
µs
SOFT START SECTION
Constant Current Output
for Soft-Start
ISS
RD
RT=24KΩ
44
50
56
µA
Discharge RDSON
470
Ω
© 2008 Fairchild Semiconductor Corporation
SG6901A • Rev. 1.0.2
www.fairchildsemi.com
10
Typical Performance Characteristics
Minimum Operating Voltage (VDD-OFF) vs. Temperature
Startup Current (IDD-ST) vs. Temperature
25
11.0
10.6
10.2
9.8
20
15
10
5
9.4
0
9.0
-40 -25 -10
5
20
35
50
65
80
95
110 125
-40 -25 -10
5
20
35
50
65
80
95 110 125
T emperature (°C)
T emperature (°C)
Figure 5. Startup Current
Figure 6. VDD Turn-Off Threshold Voltage
PWM Frequency (f OSC) vs. Temperature
Operating Current (IDD-OP) vs. Temperature
68
67
66
64
63
62
10.0
8.8
7.6
6.4
5.2
4.0
-40 -25 -10
5
20
35
50
65
80
95 110 125
-40 -25 -10
5
20
35
50
65
80
95
110 125
Temperature (°C)
Temperature (°C)
Figure 7. Operating Current
Figure 8. PWM Frequency
VDD Over-Voltage Protection (VDD-OVP) vs. Temperature
Start Threshold Voltage (VDD-ON) vs. Temperature
13.0
12.6
12.2
11.8
11.4
11.0
25.5
25.1
24.7
24.3
23.9
23.5
-40 -25 -10
5
20
35
50
65
80
95 110 125
-40 -25 -10
5
20
35
50
65
80
95 110 125
Temperature (°C)
Temperature (°C)
Figure 9. VDD Turn-On Threshold Voltage
Figure 10. VDD OVP Threshold Voltage
© 2008 Fairchild Semiconductor Corporation
SG6901A • Rev. 1.0.2
www.fairchildsemi.com
11
Typical Performance Characteristics
High VRMS Threshold for RANGE Comparator (VRMS-H) vs. Temperature
Reference Voltage (VREF) vs. Temperature
3.05
3.03
3.01
2.99
2.97
2.95
2.00
1.98
1.96
1.94
1.92
1.90
-40 -25 -10
5
20
35
50
65
80
95
110 125
-40 -25 -10
5
20
35
50
65
80
95 110 125
Temperature (°C)
Temperature (°C)
Figure 11. High VRMS Threshold for RANGE Comparator
Figure 12. Reference Voltage
Rising Time (tR-PFC) vs. Temperature
ꢀ
)
Low VRMS Threshold for RANGE Comparator (V
RMS-L
vs. Temperature
120
104
88
1.65
1.63
1.61
1.59
1.57
1.55
72
56
40
-40 -25 -10
5
20
35
50
65
80
95
110 125
-40 -25 -10
5
20
35
50
65
80
95 110 125
Temperature (°C)
Temperature (°C)
Figure 13. Low VRMS Threshold for RANGE Comparator
Figure 14. OPFC Rising Time
Falling Time (tF-PFC) vs. Temperature (°C)
PFC Over-Voltage Protection (OVPPFC) vs. Temperature
110
96
82
68
54
40
3.30
3.28
3.26
3.24
3.22
3.20
-40 -25 -10
5
20
35
50
65
80
95 110 125
-40 -25 -10
5
20
35
50
65
80
95 110 125
Temperature (°C)
Temperature (°C)
Figure 15. PFC OVP Threshold Voltage
Figure 16. OPFC Falling Time
© 2008 Fairchild Semiconductor Corporation
SG6901A • Rev. 1.0.2
www.fairchildsemi.com
12
Typical Performance Characteristics
Maximum Duty Cycle (DCYMAX) vs. Temperature
Peak Current Limit Threshold Voltage 1 (VLIMIT-1) vs. Temperature
98
0.75
97
96
95
94
93
0.73
0.71
0.69
0.67
0.65
-40 -25 -10
5
20
35
50
65
80
95 110 125
-40 -25 -10
5
20
35
50
65
80
95
110 125
Temperature (°C)
Temperature (°C)
Figure 17. PFC Maximum Duty Cycle
Figure 18. Peak Current Limit Threshold Voltage
PWM Open-Loop Protection Voltage (FBOPEN-LOOP) vs. Temperature
Peak Current Limit Threshold Voltage 2 (VLIMIT-2) vs. Temperature
0.70
4.80
4.68
4.56
4.44
4.32
4.20
0.68
0.66
0.64
0.62
0.60
-40 -25 -10
5
20
35
50
65
80
95 110 125
-40 -25 -10
5
20
35
50
65
80
95
110 125
Temperature (°C)
Temperature (°C)
Figure 19. PWM Open-Loop Protection Voltage
Figure 20. Peak Current Limit Threshold Voltage2
Falling Time (tF-PWM) vs. Temperature
PWM Maximum Duty Cycle (DCYMAXPWM) vs. Temperature (°C)
110
83
94
78
62
46
30
81
79
77
75
73
-40 -25 -10
5
20
35
50
65
80
95 110 125
-40 -25
-10
5
20
35
50
65
80
95
110 125
Temperature (°C)
Temperature (°C)
Figure 21. OPWM Falling Time
Figure 22. PWM Maximum Duty Cycle
© 2008 Fairchild Semiconductor Corporation
SG6901A • Rev. 1.0.2
www.fairchildsemi.com
13
Typical Performance Characteristics
OTP Threshold Voltage (VOTP-OFF) vs. Temperature
1.25
1.23
1.21
1.19
1.17
1.15
-40 -25 -10
5
20
35
50
65
80
95 110 125
Temperature (°C)
Figure 23.VDD OTPurn Threshold Voltage
© 2008 Fairchild Semiconductor Corporation
SG6901A • Rev. 1.0.2
www.fairchildsemi.com
14
Functional Description
improve the efficiency at low-line input. The RANGE pin
(open-drain structure) is used for the two-level output
voltage setting.
SG6901A is a highly integrated PFC/PWM combination
controller. Many functions and protections are built in to
provide a compact design. The following sections
describe the operation and function.
Switching Frequency and Current Sources
The switching frequency can be programmed by the
resistor RI connected between RI pin and GND. The
relationship is:
1560
RI (kΩ )
fOSC
=
(kHz)
(1)
Figure 25.Interleaved Switching Pattern
For example, a 24KΩ resistor RI results in a 65KHz
switching frequency. Accordingly, a constant current, IT,
flows through RI:
PFC Operation
The purpose of a boost active power factor corrector
(PFC) is to shape the input current of a power supply.
The input current waveform and phase follow that of the
input voltage. Average-current-mode control is utilized
for continuous-current-mode operation for the PFC
booster. With the innovative multi-vector control for
voltage loop and switching charge multiplier-divider for
current reference, excellent input power factor is
achieved with good noise immunity and transient
response. Figure 26 shows the total control loop for the
average-current-mode control circuit.
1.2V
RI (kΩ )
IT =
(mA)
(2)
IT is used to generate internal current reference.
Line Voltage Detection (VRMS)
Figure 24 shows a resistive divider with low-pass
filtering for line-voltage detection on the VRMS pin. The
VRMS voltage is used for the PFC multiplier, brownout
protection, and range control.
The current source output from the switching charge
multiplier-divider can be expressed as:
For brownout protection, SG6901A is disabled with a
195ms delay if the voltage VRMS drops below 0.8V.
IAC ×VEA
IMO = K ×
(
µA
)
(3)
2
For PFC multiplier and range control, refer to the PFC
Operation section below for details.
VRMS
As shown in Figure 26, the current output from the IMP
pin is the summation of IMO and IMR1. IMR1 and IMR2
are identical fixed-current sources used to pull high the
operating point of the IMP and IPFC pins since the
voltage across RS goes negative with respect to
ground. Constant current sources IMR1 and IMR2 are
typically 60µA.
Through the differential amplification of the signal
across RS, better noise immunity is achieved. The
output of IEA is compared with an internal sawtooth
and the pulse width for PFC is determined. Through the
average current-mode control loop, the input current IS
is proportional to IMO:
Figure 24.Line Voltage Detection Circuit
IMO ×R2 = IS ×RS
(4)
Interleave Switching
According to Equation 4, the minimum value of R2 and
maximum of RS can be determined since IMO should
not exceed the specified maximum value.
The SG6901A uses interleaved switching to
synchronize the PFC and flyback stages, which
reduces switching noise and spreads the EMI
emissions. Figure 25 shows off-time, tOFF, inserted
between the turn-off of the PFC gate drive and the turn-
on of the PWM.
There are different concerns in determining the value of
the sense resistor RS. The value of RS should be small
enough to reduce power consumption, but large
enough to maintain the resolution.
transformer (CT) may be used to improve efficiency of
high-power converters.
A
current
For an universal input (90 ~ 264VAC) power supply
applying active boost PFC and flyback as a second
stage, the output voltage of PFC is usually designed
around 250V at low line and 390V at high line. This can
© 2008 Fairchild Semiconductor Corporation
SG6901A • Rev. 1.0.2
www.fairchildsemi.com
15
The average total input power can be expressed as:
To achieve good power factor, the voltage for VRMS and
VEA should be kept as constant as possible, according
to Equation 5. Good RC filtering for VRMS and narrow
bandwidth (lower than the line frequency) for voltage
loop are suggested for better input current shaping.
The transconductance error amplifier has output
impedance ZO and a capacitor CEA (1µF ~ 10µF)
should be connected to ground. This establishes a
dominant pole f1 for the voltage loop:
Pin = V (rms) ×IIN
IN
(rms)
∝ VRMS ×IMO
IAC × VEA
∝ VRMS
×
×
2
VRMS
Vin
(6)
× VEA
RAC
∝ VRMS
2
VRMS
VEA
1
=
2 ×
f1 =
RAC
(5)
2π × ZO × CEA
From Equation 6, VEA, the output of the voltage error
amplifier, controls the total input power and the power
delivered to the load.
Figure 26.Average-Current-Mode Control Loop
Multi-Vector Error Amplifier
PFC Over-Voltage Protection
Although the PFC stage has a low bandwidth voltage
loop for better input power factor, the innovative multi-
vector error amplifier provides a fast transient response
to clamp the overshoot and undershoot of the PFC
output voltage.
Using a voltage divider from the output of PFC to the
OVP pin, the PFC output voltage can be safely
protected. Once the voltage on the OVP pin is over
OVPPFC, the OPFC is disabled. THE OPFC is not
enabled again until the OVP voltage falls below
OVPPFC.
0 shows the block diagram of the multi-vector error
amplifier. When the variation of the feedback voltage
exceeds ±5% of the reference voltage, the
transconductance error amplifier adjusts its output
impedance to increase the loop response.
Cycle-by-Cycle Current Limiting
SG6901A provides cycle-by-cycle current limiting for
both PFC and PWM stages. Figure 28 shows the peak
current limit for the PFC stage. The PFC gate drive is
terminated once the voltage on the ISENSE pin goes
below VPK
.
The voltage of VRMS determines the voltage of VPK. The
relationship between VPK and VRMS is shown in Figure 28.
The amplitude of the constant current, Ip, is determined
by the internal current reference according to:
1.2V
IP = 2×
(8)
RI
Figure 27.Multi-Vector Error Amplifier
© 2008 Fairchild Semiconductor Corporation
SG6901A • Rev. 1.0.2
www.fairchildsemi.com
16
Limited Power Control
Every time the output of the power supply is shorted or
overloaded, the FBPWM voltage increases. If the
FBPWM voltage is higher than a designed threshold,
FBOPEN-LOOP (4.5V) for longer than tOPEN-PWM
(56ms), the OPWM is turned off.
As long as the voltage on the VDD pin is larger than
VDD-OFF (minimum operating voltage), the OPWM is not
enabled. This protection is reset every tOPEN-PWM-Hiccup
interval.
A low-frequency hiccup mode protection
Figure 28.VRMS Controlled Current Limiting
prevents the power supply from being overheated
under overload conditions.
The peak current of the ISENSE is given by
(VRMS<1.05V):
Over-Temperature Protection
(IP ×RP )-0.2V
ISENSE_peak =
(8)
The OTP pin provides for over-temperature protection.
A constant current is output from this pin. If RI is equal
to 24KΩ, the magnitude of the constant current is
100µA. An external NTC thermistor must be connected
from this pin to ground, as shown as Figure 30. When
the OTP voltage drops below VOTP-OFF (1.2V), SG6901A
is disabled and does not recover until OTP voltage
exceeds VOTP-ON (1.4V).
RS
Flyback PWM and Slope Compensation
As shown in Figure 29, peak-current-mode control is
utilized for flyback PWM. The SG6901A inserts a
synchronized 0.5V ramp at the beginning of each
switching cycle. This built-in slope compensation
ensures stable operation for continuous current-mode
operation.
When the IPWM voltage, across the sense resistor,
reaches the threshold voltage (0.9V), the OPWM is
turned off after a small propagation delay tPD-PWM
.
To improve stability or prevent sub-harmonic
oscillation, synchronized positive-going ramp is
inserted at every switching cycle.
a
Figure 30.OTP Function
Soft Start
During startup of PWM stage, the SS pin charges an
external capacitor with a constant current source. The
voltage on FBPWM is clamped by the SS voltage
during startup. In the event of a protected condition
and/or PWM is disabled, the SS pin quickly discharges.
Gate Driver
SG6901A output stage is a fast totem-pole gate driver.
The output driver is clamped by an internal 18V Zener
diode to protect the external power MOSFET.
Figure 29.Peak Current Control Loop
© 2008 Fairchild Semiconductor Corporation
SG6901A • Rev. 1.0.2
www.fairchildsemi.com
17
Physical Dimensions
13.00
12.60
A
11.43
20
11
B
9.50
10.65 7.60
10.00 7.40
2.25
1
PIN ONE
INDICATOR
10
0.65
0.51
0.35
1.27
1.27
M
0.25
C B A
LAND PATTERN RECOMMENDATION
SEE DETAIL A
2.65 MAX
0.33
0.20
C
0.10
C
0.30
0.10
SEATING PLANE
0.75
0.25
X 45°
NOTES: UNLESS OTHERWISE SPECIFIED
(R0.10)
(R0.10)
A) THIS PACKAGE CONFORMS TO JEDEC
MS-013, VARIATION AC, ISSUE E
GAGE PLANE
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
0.25
8°
0°
D) CONFORMS TO ASME Y14.5M-1994
1.27
0.40
SEATING PLANE
E) LANDPATTERN STANDARD: SOIC127P1030X265-20L
F) DRAWING FILENAME: MKT-M20BREV3
(1.40)
DETAIL A
SCALE: 2:1
Figure 31. 20-Pin Small Outline Integrated Circuit (SOIC)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2008 Fairchild Semiconductor Corporation
SG6901A • Rev. 1.0.2
www.fairchildsemi.com
18
© 2008 Fairchild Semiconductor Corporation
SG6901A • Rev. 1.0.2
www.fairchildsemi.com
19
相关型号：
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