SI9435DY [FAIRCHILD]

P-Channel Logic Level PowerTrench MOSFET; P沟道逻辑电平的PowerTrench MOSFET
SI9435DY
元器件型号: SI9435DY
生产厂家: FAIRCHILD SEMICONDUCTOR    FAIRCHILD SEMICONDUCTOR
描述和应用:

P-Channel Logic Level PowerTrench MOSFET
P沟道逻辑电平的PowerTrench MOSFET

晶体小信号场效应晶体管开关光电二极管
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型号参数:SI9435DY参数
是否无铅 不含铅
是否Rohs认证 符合
生命周期Obsolete
IHS 制造商FAIRCHILD SEMICONDUCTOR CORP
零件包装代码SOT
包装说明SO-8
针数8
Reach Compliance Codeunknown
ECCN代码EAR99
风险等级5.66
Is SamacsysN
配置SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压30 V
最大漏极电流 (Abs) (ID)5.3 A
最大漏极电流 (ID)5.3 A
最大漏源导通电阻0.05 Ω
FET 技术METAL-OXIDE SEMICONDUCTOR
JESD-30 代码R-PDSO-G8
JESD-609代码e3
湿度敏感等级1
元件数量1
端子数量8
工作模式ENHANCEMENT MODE
最高工作温度150 °C
封装主体材料PLASTIC/EPOXY
封装形状RECTANGULAR
封装形式SMALL OUTLINE
峰值回流温度(摄氏度)260
极性/信道类型P-CHANNEL
最大功率耗散 (Abs)1 W
认证状态Not Qualified
子类别Other Transistors
表面贴装YES
端子面层Matte Tin (Sn)
端子形式GULL WING
端子位置DUAL
处于峰值回流温度下的最长时间NOT SPECIFIED
晶体管应用SWITCHING
晶体管元件材料SILICON
Base Number Matches1
MAX34334CSE前5页PDF页面详情预览
Si9435DY
January 2001
Si9435DY
P-Channel Logic Level PowerTrench
MOSFET
General Description
This P-Channel Logic Level MOSFET is produced
using
Fairchild
Semiconductor's
advanced
PowerTrench process that has been especially tailored
to minimize on-state resistance and yet maintain
superior switching performance.
These devices are well suited for low voltage and
battery powered applications where low in-line power
loss and fast switching are required.
Features
–5.3 A, –30 V. R
DS(ON)
= 50 mΩ @ V
GS
= –10 V
R
DS(ON)
= 80 mΩ @ V
GS
= –4.5 V
Low gate charge
Fast switching speed
High performance trench technology for extremely
low R
DS(ON)
High power and current handling capability
Applications
DC/DC converter
Load switch
Motor Drive
D
D
D
D
5
6
4
3
2
1
SO-8
S
S
S
G
7
8
Absolute Maximum Ratings
Symbol
V
DSS
V
GSS
I
D
P
D
Drain-Source Voltage
Gate-Source Voltage
Drain Current
– Continuous
– Pulsed
T
A
=25 C unless otherwise noted
o
Parameter
Ratings
–30
±20
(Note 1a)
Units
V
V
A
W
-5.3
-20
2.5
1.2
1.0
-55 to +150
Power Dissipation for Single Operation
(Note 1a)
(Note 1b)
(Note 1c)
T
J
, T
STG
Operating and Storage Junction Temperature Range
°C
Thermal Characteristics
R
θJA
R
θJC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
50
25
°C/W
°C/W
Package Marking and Ordering Information
Device Marking
9435
Device
Si9435DY
Reel Size
13’’
Tape width
12mm
Quantity
2500 units
2001
Fairchild Semiconductor International
Si9435DY Rev A(W)
Si9435DY
Electrical Characteristics
Symbol
BV
DSS
∆BV
DSS
∆T
J
I
DSS
I
GSSF
I
GSSR
T
A
= 25°C unless otherwise noted
Parameter
Drain–Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate–Body Leakage, Forward
Gate–Body Leakage, Reverse
(Note 2)
Test Conditions
V
GS
= 0 V, I
D
= –250
µA
I
D
= –250
µA,
Referenced to 25°C
V
DS
= –24 V,
V
GS
= 20 V,
V
GS
= –20 V,
V
GS
= 0 V
V
DS
= 0 V
V
DS
= 0 V
Min
–30
Typ
Max Units
V
Off Characteristics
–22
–1
100
–100
mV/°C
µA
nA
nA
On Characteristics
V
GS(th)
∆V
GS(th)
∆T
J
R
DS(on)
Gate Threshold Voltage
Gate Threshold Voltage
Temperature Coefficient
Static Drain–Source
On–Resistance
On–State Drain Current
Forward Transconductance
V
DS
= V
GS
, I
D
= –250
µA
I
D
= –250
µA,
Referenced to 25°C
V
GS
= –10 V,
I
D
= –5.3 A
V
GS
= –10 V, I
D
= –5.3 A, T
J
=125°C
V
GS
= –4.5 V, I
D
= –4.2A,
V
GS
= –10 V,
V
DS
= –15 V,
V
DS
= –5 V
I
D
= –5.3 A
–1
–1.7
4
38
54
55
–3
V
mV/°C
50
79
80
mΩ
I
D(on)
g
FS
–20
12
A
S
Dynamic Characteristics
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
(Note 2)
V
DS
= –15 V,
f = 1.0 MHz
V
GS
= 0 V,
690
306
77
pF
pF
pF
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
gs
Q
gd
Turn–On Delay Time
Turn–On Rise Time
Turn–Off Delay Time
Turn–Off Fall Time
Total Gate Charge
Gate–Source Charge
Gate–Drain Charge
V
DD
= –15 V,
V
GS
= –10 V,
I
D
= –1 A,
R
GEN
= 6
7
10
19
11
14
18
34
20
23
ns
ns
ns
ns
nC
nC
nC
V
DS
= –15 V,
V
GS
= –10 V
I
D
= –5.3 A,
14
2.4
4.8
Drain–Source Diode Characteristics and Maximum Ratings
I
S
V
SD
Maximum Continuous Drain–Source Diode Forward Current
Drain–Source Diode Forward
V
GS
= 0 V, I
S
= –5.3 A
Voltage
–5.3
(Note 2)
A
V
–0.86
–1.2
Notes:
1.
R
θJA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. R
θJC
is guaranteed by design while R
θCA
is determined by the user's board design.
a) 50°C/W when
2
mounted on a 1in
pad of 2 oz copper
b) 105°C/W when
2
mounted on a .04 in
pad of 2 oz copper
c) 125°C/W when mounted on a
minimum pad.
Scale 1 : 1 on letter size paper
2.
Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%
Si9435DY Rev A(W)
Si9435DY
Typical Characteristics
30
V
GS
= -10.0V
R
DS(ON)
, NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
2.5
V
GS
= -3.5V
2
-4.0V
1.5
-4.5V
-5.5V
-7.0V
1
-10.0V
25
20
15
10
5
0
0
-7.5V
-6.5V
-6.0V
-5.0V
-4.0V
-3.0V
1
2
3
4
5
0.5
0
5
10
15
-I
D
, DRAIN CURRENT (A)
-V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
0.2
1.6
I
D
= -5.3A
V
GS
= -10V
I
D
= -5.3A
1.4
0.15
1.2
0.1
1.0
0.05
0.8
T
A
= 125 C
T
A
= 25 C
o
o
0.6
-50
-25
0
25
50
75
100
o
0
125
150
2
4
6
8
10
T
J
, JUNCTION TEMPERATURE ( C)
-V
GS
, GATE TO SOURCE VOLTAGE (V)
Figure 3. On-Resistance Variation with
Temperature.
20
V
DS
= -10V
16
T
A
= -55 C
125 C
o
o
Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
100
25 C
10
o
V
GS
= 0V
12
1
T
A
= 125 C
25 C
o
o
8
0.1
-55 C
o
4
0.01
0
1
2
3
4
5
0.001
0
0.2
0.4
0.6
0.8
1
1.2
1.4
-V
GS
, GATE TO SOURCE VOLTAGE (V)
-V
SD
, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics.
Figure 6. Body Diode Forward Voltage Variation
with Source Current and Temperature.
Si9435DY Rev A(W)
Si9435DY
Typical Characteristics
10
I
D
= -5.3A
V
DS
= -5V
8
-15V
6
-10V
1000
f = 1 MHz
V
GS
= 0 V
800
C
ISS
600
C
OSS
4
400
2
200
C
RSS
0
0
5
10
15
0
0
5
10
15
20
25
30
Q
g
, GATE CHARGE (nC)
-V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Gate Charge Characteristics.
100
R
DS(ON)
LIMIT
10
100
µ
s
1ms
10ms
100ms
1s
1
V
GS
= -10V
SINGLE PULSE
R
θ
JA
= 125 C/W
T
A
= 25 C
0.01
0.1
1
10
100
0
o
o
Figure 8. Capacitance Characteristics.
50
SINGLE PULSE
R
θ
JA
= 125°C/W
T
A
= 25°C
40
30
10s
DC
20
0.1
10
0.001
0.01
0.1
1
10
100
-V
DS
, DRAIN-SOURCE VOLTAGE (V)
t
1
, TIME (sec)
Figure 9. Maximum Safe Operating Area.
Figure 10. Single Pulse Maximum
Power Dissipation.
1
D = 0.5
0.2
R
θ
JA
(t) = r(t) + R
θ
JA
0.1
0.05
0.02
0.01
SINGLE PULSE
0.1
R
θ
JA
= 125 C/W
P(pk)
t
1
t
2
T
J
- T
A
= P * R
θ
JA
(t)
Duty Cycle, D = t
1
/ t
2
o
0.01
0.001
0.0001
0.001
0.01
0.1
t
1
, TIME (sec)
1
10
100
1000
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1c.
Transient thermal response will change depending on the circuit board design.
Si9435DY Rev A(W)
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
ACEx™
Bottomless™
CoolFET™
CROSSVOLT™
DOME™
E
2
CMOS
TM
EnSigna
TM
FACT™
FACT Quiet Series™
FAST
DISCLAIMER
FASTr™
GlobalOptoisolator™
GTO™
HiSeC™
ISOPLANAR™
MICROWIRE™
OPTOLOGIC™
OPTOPLANAR™
PACMAN™
POP™
PowerTrench
QFET™
QS™
QT Optoelectronics™
Quiet Series™
SILENT SWITCHER
SMART START™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic™
UHC™
VCX™
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
2. A critical component is any component of a life
support device or system whose failure to perform can
systems which, (a) are intended for surgical implant into
be reasonably expected to cause the failure of the life
the body, or (b) support or sustain life, or (c) whose
support device or system, or to affect its safety or
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
effectiveness.
reasonably expected to result in significant injury to the
user.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Advance Information
Product Status
Formative or
In Design
Definition
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. G
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