SN74ACT574MTC [FAIRCHILD]
Bus Driver, ACT Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, TSSOP-20;
| 型号： | SN74ACT574MTC |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Bus Driver, ACT Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, TSSOP-20 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总10页 (文件大小：173K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
May 1998
74AC574 • 74ACT574
Octal D-Type Flip-Flop with 3-STATE Outputs
General Description
Features
n ICC and IOZ reduced by 50%
The AC/ACT574 is a high-speed, low power octal flip-flop
with a buffered common Clock (CP) and a buffered common
Output Enable ( OE). The information presented to the
D-type inputs is stored in the flip-flops on the LOW-to-HIGH
Clock (CP) transition.
n Inputs and outputs on opposite sides of package
allowing easy interface with microprocessors
n Useful as input or output port for microprocessors
n Functionally identical to AC/ACT374
The AC/ACT574 is functionally identical to the AC/ACT374
except for the pinouts.
n 3-STATE outputs for bus-oriented applications
n Outputs source/sink 24 mA
n ACT574 has TTL-compatible inputs
Ordering Code:
Order Number
74AC574PC
Package Number
V20A
Package Description
20-Lead Molded Dual-in-Line Package
74AC574SC
M20B
20-Lead (0.300" Wide) Molded Small Outline Package, JEDEC
20-Lead Molded Shrink Small Outline Package, EIAJ Type II
20-Lead Molded Dual-in-Line Package
74AC574SJ
M20D
74ACT574PC
74ACT574SC
74ACT574SJ
74ACT574MTC
V20A
M20B
20-Lead (0.300" Wide) Molded Small Outline Package, JEDEC
20-Lead Molded Shrink Small Outline Package, EIAJ Type II
20-Lead Thin Shrink Small Outline Package, JEDEC
M20D
MTC20
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagrams
Pin Assignment for DIP,
SOIC and TSSOP
DS009910-1
IEEE/IEC
DS009910-2
Pin Descriptions
Pin Names
D0–D7
CP
Description
Data Inputs
Clock Pulse Input
DS009910-4
OE
3-STATE Output Enable Input
3-STATE Outputs
O0–O7
™
FACT is a trademark of Fairchild Semiconductor Corporation.
© 1998 Fairchild Semiconductor Corporation
DS009910
www.fairchildsemi.com
Functional Description
The AC/ACT574 consists of eight edge-triggered flip-flops
with individual D-type inputs and 3-STATE true outputs. The
buffered clock and buffered Output Enable are common to all
flip-flops. The eight flip-flops will store the state of their indi-
vidual D-type inputs that meet the setup and hold time re-
quirements on the LOW-to-HIGH Clock (CP) transition. With
the Output Enable (OE) LOW, the contents of the eight
flip-flops are available at the outputs. When OE is HIGH, the
outputs go to the high impedance state. Operation of the OE
input does not affect the state of the flip-flops.
Function Table
Inputs
Internal Outputs
Function
OE CP
D
L
Q
NC
NC
L
ON
Z
H
H
H
H
L
H
Hold
H
H
L
Z
Hold
N
N
N
N
Z
Load
H
L
H
Z
Load
L
L
Data Available
Data Available
No Change in Data
No Change in Data
L
H
L
H
H
L
H
H
NC
NC
NC
NC
L
H
=
=
=
=
H
L
X
Z
HIGH Voltage Level
LOW Voltage Level
Immaterial
High Impedance
N =
LOW-to-HIGH Transition
=
NC No Change
Logic Diagram
DS009910-5
Please note that this diagram is provided only for the understanding of
logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings (Note 1)
Recommended Operating
Conditions
Supply Voltage (VCC
)
−0.5V to +7.0V
DC Input Diode Current (IIK
)
Supply Voltage (VCC
)
=
(Unless Otherwise Specified)
VI −0.5V
−20 mA
+20 mA
=
(AC)
2.0V to 6.0V
4.5V to 5.5V
0V to VCC
VI VCC +0.5V
(ACT)
DC Input Voltage (VI)
−0.5V to VCC +0.5V
Input Voltage (VI)
Output Voltage (VO)
Operating Temperature (TA)
Minimum Input Edge Rate (∆V/∆t)
AC Devices
DC Output Diode Current (IOK
)
=
0V to VCC
VO −0.5V
−20 mA
+20 mA
=
−40˚C to +85˚C
VO VCC +0.5V
DC Output Voltage (VO)
−0.5V to VCC +0.5V
DC Output Source or Sink Current
(IO
% to 70% of V
VIN from 30
±
±
)
50 mA
CC
@
VCC 3.3V, 4.5V, 5.5V
125 mV/ns
DC VCC or Ground Current
Per Output Pin (ICC or IGND
Minimum Input Edge Rate (∆V/∆t)
ACT Devices
)
50 mA
Storage Temperature (TSTG
Junction Temperature (TJ)
PDIP
)
−65˚C to +150˚C
VIN from 0.8V to 2.0V
@
VCC 4.5V, 5.5V
125 mV/ns
140˚C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. Fairchild does not recom-
™
mend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics for AC
VCC
=
=
Symbol
Parameter
TA 25˚C
TA −40˚C to +85˚C
Units
Conditions
(V)
Typ
Guaranteed Limits
=
VIH
Minimum High
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
1.5
2.1
3.15
3.85
0.9
2.1
3.15
3.85
0.9
VOUT 0.1V
Level Input
Voltage
2.25
2.75
1.5
V
V
V
V
or VCC − 0.1V
=
VIL
Maximum Low
Level Input
Voltage
VOUT 0.1V
2.25
2.75
2.99
4.49
5.49
1.35
1.65
2.9
1.35
1.65
2.9
or VCC − 0.1V
=
IOUT −50 µA
VOH
Minimum High
Level Output
Voltage
4.4
4.4
5.4
5.4
=
VIN VIL or VIH
2.56
3.86
4.86
2.46
3.76
4.76
=
IOH −12 mA
=
IOH −24 mA IOH
=
IOH −24 mA (Note 2)
=
IOUT 50 µA
VOL
Maximum Low
Level Output
Voltage
3.0
4.5
5.5
0.002
0.001
0.001
0.1
0.1
0.1
0.1
0.1
0.1
V
=
VIN VILor VIH
=
IOL 12 mA
3.0
4.5
5.5
5.5
0.36
0.36
0.36
0.44
0.44
0.44
=
IOL 24 mA
V
=
IOL 24 mA (Note 2)
=
±
±
IIN
Maximum Input
Leakage Current
Maximum
0.1
1.0
µA
VI
VCC, GND
(Note 4)
IOZ
=
VI (OE) VIL, VIH
=
±
±
3-STATE
5.5
0.25
2.5
µA
VI VCC, VGND
=
VO VCC, GND
Leakage Current
Minimum Dynamic
Output Current (Note 3)
Maximum Quiescent
Supply Current
=
VOLD 1.65V
IOLD
5.5
5.5
5.5
75
mA
mA
µA
=
VOHD 3.85V
IOHD
−75
40.0
=
ICC
4.0
VIN VCC
(Note 4)
or GND
Note 2: All outputs loaded; thresholds on input associated with output under test.
3
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DC Electrical Characteristics for AC (Continued)
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
@
@
Note 4:
I
and I
CC
3.0V are guaranteed to be less than or equal to the respective limit 5.5V V .
IN
CC
DC Electrical Characteristics for ACT
VCC
=
=
Symbol
Parameter
TA 25˚C
TA −40˚C to +85˚C
Units
Conditions
(V)
Typ
Guaranteed Limits
=
VIH
Minimum High Level
Input Voltage
4.5
5.5
4.5
5.5
4.5
5.5
1.5
1.5
2.0
2.0
0.8
0.8
4.4
5.4
2.0
2.0
0.8
0.8
4.4
5.4
V
V
V
VOUT 0.1V
or VCC − 0.1V
=
VIL
Maximum Low Level
Input Voltage
1.5
VOUT 0.1V
1.5
or VCC − 0.1V
=
IOUT −50 µA
VOH
Minimum High Level
4.49
5.49
=
VIN
VILor VIH
=
4.5
5.5
4.5
5.5
3.86
4.86
0.1
3.76
4.76
0.1
V
V
IOH −24 mA
=
IOH −24 mA (Note 5)
=
IOUT 50 µA
VOL
Maximum Low Level
Output Voltage
0.001
0.001
0.1
0.1
=
VIN VILor VIH
=
IOL 24 mA
4.5
5.5
5.5
0.36
0.36
0.44
0.44
V
=
IOL 24 mA (Note 5)
=
±
±
IIN
Maximum Input
0.1
1.0
µA
µA
VI VCC, GND
Leakage Current
Maximum 3-STATE
Leakage Current
Maximum ICC/Input
=
±
±
IOZ
5.5
0.25
2.5
VI VIL, VIH
=
VO
V
CC, GND
=
ICCT
5.5
5.5
0.6
1.5
mA
mA
VI VCC − 2.1V
=
VOLD 1.65V
I]OLD
Minimum
Dynamic Output
Current (Note 6)
75
=
VOHD 3.85V
IOHD
ICC
5.5
5.5
−75
40.0
mA
µA
=
Maximum Quiescent
Supply Current
4.0
VIN VCC
or GND
Note 5: All outputs loaded; thresholds on input associated with output under test.
Note 6: Maximum test duration 2.0 ms, one output loaded at a time.
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4
AC Electrical Characteristics for AC
=
TA −40˚C to +85˚C
VCC
(V)
(Note 7)
=
TA +25˚C
=
Symbol
Parameter
CL 50 pF
Units
=
CL 50 pF
Min
75
Typ
112
153
8.5
6.0
7.5
5.5
7.0
5.0
6.5
5.0
7.5
6.0
5.5
4.5
Max
Min
60
Max
fmax
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
Maximum Clock
Frequency
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
MHz
ns
95
85
Propagation Delay
CP to On
3.5
2.0
3.5
2.0
2.5
2.0
3.0
2.0
3.5
2.0
2.0
1.0
13.5
9.5
3.5
2.0
3.5
2.0
2.5
2.0
3.0
1.5
2.5
1.5
1.5
1.0
15.0
11.0
13.5
9.5
Propagation Delay
CP to On
12.0
8.5
ns
Output Enable Time
11.0
8.5
12.0
9.0
ns
Output Enable Time
Output Disable Time
Output Disable Time
10.5
8.0
11.5
9.0
ns
12.0
9.5
13.0
10.5
10.0
8.5
ns
9.0
ns
7.5
±
Note 7: Voltage Range 3.3 is 3.3V 0.3V
±
Voltage Range 5.0 is 5.0V 0.5V
5
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AC Operating Requirements for AC
VCC
(V)
(Note 8)
=
=
TA −40˚C to +85˚C
TA +25˚C
Symbol
Parameter
Units
=
=
CL 50 pF
CL 50 pF
Typ
0.5
0
Guaranteed Minimum
tS
Set-Up Time, HIGH or LOW
Dn to CP
3.3
5.0
3.3
5.0
3.3
5.0
2.5
1.5
1.5
1.5
6.0
4.0
3.0
2.0
1.5
1.5
7.0
5.0
ns
ns
ns
tH
Hold Time, HIGH or LOW
Dn to CP
−0.5
0
tW
CP Pulse Width
HIGH or LOW
3.5
2.0
±
Note 8: Voltage Range 3.3 is 3.3V 0.3V
±
Voltage Range 5.0 is 5.0V 0.5V
AC Electrical Characteristics for ACT
VCC
(V)
(Note 9)
=
=
TA −40˚C to +85˚C
TA +25˚C
Symbol
Parameter
Units
=
=
CL 50 pF
CL 50 pF
Min
100
2.5
Typ
110
7.0
Max
11.0
10.0
Min
85
Max
fmax
tPLH
Maximum Clock Frequency
Propagation Delay
CP to On
5.0
5.0
ns
ns
2.0
12.0
11.0
tPHL
Propagation Delay
CP to On
5.0
2.0
6.5
1.5
ns
tPZH
tPZL
tPHZ
tPLZ
Output Enable Time
Output Enable Time
Output Disable Time
Output Disable Time
5.0
5.0
5.0
5.0
2.0
2.0
2.0
2.0
6.4
6.0
7.0
5.5
9.5
9.0
1.5
1.5
1.5
1.5
10.0
10.0
11.5
9.0
ns
ns
ns
ns
10.5
8.5
±
Note 9: Voltage Range 5.0 is 5.0V 0.5V
AC Operating Requirements for ACT
VCC
(V)
(Note 10)
=
=
TA −40˚C to +85˚C
TA +25˚C
Symbol
Parameter
Units
=
=
CL 50 pF
CL 50 pF
Guaranteed
Minimum
Typ
tS
Set-Up Time, HIGH or LOW
Dn to CP
5.0
5.0
5.0
1.5
2.5
1.0
4.0
ns
ns
ns
tH
Hold Time, HIGH or LOW
Dn to CP
−0.5
2.5
tW
CP Pulse Width
HIGH or LOW
±
Note 10: Voltage Range 5.0 is 5.0V 0.5V
Capacitance
Symbol
Parameter
Typ
4.5
Units
pF
Conditions
=
VCC OPEN
CIN
Input Capacitance
=
VCC 5.0V
CPD
Power Dissipation Capacitance
40.0
pF
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6
7
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Molded Dual-in-Line Package
Package Number V20A
20-Lead (0.300" Wide) Molded Small Outline Package, JEDEC
Package Number M20B
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8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Molded Shrink Small Outline Package, EIAJ Type II
Package Number M20D
9
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package, JEDEC
Package Number MTC20
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE-
VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMI-
CONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or sys-
tems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Corporation
Fairchild Semiconductor
Europe
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Hong Kong Ltd.
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Japan Ltd.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
相关型号：
SN74ACT574PC
Bus Driver, ACT Series, 1-Func, 8-Bit, True Output, CMOS, PQCC20, PLASTIC, DIP-20
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