SPT7725BCU [FAIRCHILD]
8-BIT, 300 MSPS, FLASH A/D CONVERTER; 8 - BIT ， 300 MSPS ，FLASH A / D转换器
| 型号： | SPT7725BCU |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 8-BIT, 300 MSPS, FLASH A/D CONVERTER |
| 文件： | 总12页 (文件大小：136K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SPT7725
8-BIT, 300 MSPS, FLASH A/D CONVERTER
TECHNICAL DATA
AUGUST 17, 2001
FEATURES
APPLICATIONS
• Metastable errors reduced to 1 LSB
• Low input capacitance: 10 pF
• Wide input bandwidth: 210 MHz
• 300 MSPS conversion rate
• Digital oscilloscopes
• Transient capture
• Radar, EW, ECM
• Direct RF down-conversion
• Medical electronics: ultrasound, CAT instrumentation
• Typical power dissipation: 2.2 watts
GENERAL DESCRIPTION
of 2.2 W. A proprietary decoding scheme reduces meta-
stable errors to the 1 LSB level.
The SPT7725 is a monolithic flash A/D converter capable
of digitizing a two volt analog input signal into 8-bit digital The SPT7725 is available in 42-lead ceramic sidebrazed
words at a 300 MSPS (typ) update rate.
DIP, surface-mount 44-lead cerquad, and 46-lead PGA
packages (all are pin-compatible with the SPT7710); the
cerquad and PGA packages allow access to additional
reference ladder taps, an overrange bit, and a data ready
output. The SPT7725 is available in the industrial tem-
perature range.
For most applications, no external sample-and-hold is re-
quired for accurate conversion due to the device’s narrow
aperture time, wide bandwidth, and low input capacitance.
A single standard –5.2 volt power supply is required for
operation of the SPT7725, with nominal power dissipation
BLOCK DIAGRAM
Analog Input
AGND DGND VEE
(Force or Sense)
LINV MINV
VRTS
Preamp
Comparator
VRTF
256
255
DRINV
Clock
Buffer
MSB D7
DREAD
VR3
152
151
128
127
64
Overrange
D7 MSB
D6
VR2
ECL
256 to
Latches
and
D5
8-Bit
Encoder
Buffers
These functions are
available in the PGA and
cerquad packages only.
D4
D6
D5
D4
D3
D2
D1
D3
VR1
63
D2
2
D1
1
D0 LSB
VRBF
VRBS
CLK
CLK
LSB D0
2
Convert
Analog Input
(Sense or Force)
V
AGND
EE
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C
Supply Voltages
Temperature
Negative Supply Voltage (VEE TO GND) –7.0 to +0.5 V
Ground Voltage Differential .................... –0.5 to +0.5 V
Operating Temperature,ambient ............. –25 to +85 °C
junction ...................... +150 °C
Lead Temperature, (soldering 10 seconds) ..... +300 °C
Storage Temperature............................ –65 to +150 °C
Input Voltage
Analog Input Voltage ............................... VEE to +0.5 V
Reference Input Voltage .......................... VEE to +0.5 V
Digital Input Voltage ................................ VEE to +0.5 V
Reference Current VRTF to VRBF ........................ 25 mA
Note: 1. Operation at any Absolute Maximum Rating is not implied.See
Electrical Specifications for proper nominal applied conditions
in typical applications.
Output
Digital Output Current ............................... 0 to –30 mA
ELECTRICAL SPECIFICATIONS
TA= TMIN toTMAX, VEE=–5.2 V, RSource=50 Ω, VRBF=–2.00V, VR2=–1.00V, VRTF=0.00 V, ƒCLK=250 MHz, Duty Cycle=50%, unless otherwise specified.
TEST
TEST
SPT7725A
TYP
SPT7725B
TYP MAX UNITS
PARAMETERS
CONDITIONS LEVEL
MIN
MAX
MIN
DC Accuracy
Integral Linearity Error
Differential Linearity Error
No missing codes
ƒCLK = 100 kHz
ƒCLK = 100 kHz
VI
VI
–0.75 ±0.60 +0.75
–0.95 ±0.80 +0.95 LSB
–0.75
+0.75
–0.95
+0.95 LSB
Guaranteed
Guaranteed
Analog Input
Offset Error VRT
Offset Error VRB
Input Voltage Range
Input Capacitance
VI
VI
VI
–30
–30
–2.0
+30
+30
0.0
–30
–30
–2.0
+30 mV
+30 mV
0.0 Volts
Over full
input range
V
V
VI
V
10
15
250
10
15
250
pF
kΩ
500 µA
V/µs
Input Resistance
Input Current
Input Slew Rate
500
1,000
1,000
Large Signal Bandwidth
Small Signal Bandwidth
Clock Synchronous
Input Currents
VIN=F.S.
VIN=500 mVP-P
V
V
210
335
210
335
MHz
MHz
V
40
40
µA
Reference Input
Ladder Resistance
Reference Bandwidth
VI
V
100
250
200
10
300
100
250
200
10
300
Ω
MHz
Timing Characteristics
Maximum Sample Rate
Clock to Data Delay
Output Delay Tempco
CLK-to-Data Ready Delay (tD)
Aperture Jitter
IV
V
V
V
V
V
300
2.4
2
2.0
5
300
2.4
2
2.0
5
MSPS
ns
ps/°C
ns
ps
Acquisition Time
1.5
1.5
ns
Dynamic Performance
Signal-to-Noise Ratio
ƒIN = 3.58 MHz
ƒIN = 50 MHz
ƒIN = 3.58 MHz
ƒIN = 50 MHz
VI
VI
VI
VI
VI
VI
45
39
47
42
–52
–43
46
44
38
46
41
–50
–42
44
dB
dB
–46 dB
–39 dB
dB
Total Harmonic Distortion
–48
–40
Signal-to-Noise and Distortion ƒIN = 3.58 MHz
(SINAD) ƒIN = 50 MHz
44
37
42
35
39
37
dB
SPT7725
2
8/17/01
ELECTRICAL SPECIFICATIONS
TA= TMIN toTMAX, VEE=–5.2 V, RSource=50 Ω, VRBF=–2.00V, VR2=–1.00V, VRTF=0.00 V, ƒCLK=250 MHz, Duty Cycle=50%, unless otherwise specified.
TEST
TEST
SPT7725A
TYP
SPT7725B
TYP
PARAMETERS
CONDITIONS LEVEL
MIN
MAX
MIN
MAX UNITS
Digital Inputs
Digital Input High Voltage
(MINV, LINV)
Digital Input Low Voltage
(MINV, LINV)
Clock Low Width, tPWL
Clock High Width, tPWH
VI
–1.1
–0.7
–1.5
–1.1
–0.7 Volts
VI
VI
VI
–2.0
2.2
2.2
–2.0
2
–1.5 Volts
2.0
2.0
1.8
1.8
ns
ns
2
Digital Outputs
Digital Output High Voltage
Digital Output Low Voltage
50 Ω to –2 V
50 Ω to –2 V
VI
VI
–1.1
–1.1
Volts
–1.5 Volts
–1.5
Power Supply Requirements
Supply Current
+25 °C
+25 °C
VI
VI
425
2.2
550
2.9
425
2.2
550 mA
Power Dissipation
2.9
W
TEST LEVEL CODES
LEVEL TEST PROCEDURE
All electrical characteristics are subject to the
following conditions:
I
100% production tested at the specified temperature.
II
100% production tested at TA = +25 °C, and sample tested at the
specified temperatures.
All parameters having min/max specifications
are guaranteed. The Test Level column indi-
cates the specific device testing actually per-
formed during production and Quality Assur-
ance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.
III
IV
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design and characteri-
zation data.
V
Parameter is a typical value for information purposes only.
VI
100% production tested at TA = +25 °C. Parameter is guaranteed
over specified temperature range.
Unless otherwise noted, all test are pulsed
tests; therefore, TJ = TC = TA.
SPT7725
3
8/17/01
TYPICAL PERFORMANCE CHARACTERISTICS
SNR vs Input Frequency
THD vs Input Frequency
52
50
48
46
44
42
40
38
75
70
65
60
S = 250 MSPS
S = 250 MSPS
55
50
45
40
35
30
36
34
1
10
100
1
10
100
Input Frequency (MHz)
Input Frequency (MHz)
SINAD vs Input Frequency
SNR, THD, SINAD vs Temperature
52
50
48
50
S = 250 MSPS
IN = 100 MHz
S = 250 MSPS
45
40
35
30
46
44
42
40
38
36
34
THD
SNR
SINAD
1
10
100
40
20
0
20
40
60
80
Input Frequency (MHz)
Temperature (°C)
SPT7725
4
8/17/01
Figure 1 – Typical Interface Circuit 1
L
VEE
Analog Input
2.2 µF
.01 µF
5.2 V
*See below
Can Be Either
+
U1
Force Or Sense
AGND
Voltage
Limiter
LINV
MINV
VIN
RT
VRTF
Preamp
Comparator
256
MSB D7
Clock
Buffer
255
152
151
D6
Typical Voltage Limiter
D5
R
S
D1
49.9
D2
5.2
D1=D2=HP, 1N 5712
D4
128
127
V
R2
ECL
Latches
And
256 To
8-Bit
Encoder
.01 µF
Buffers
D3
D2
64
63
2
VEE
D1
10
V
Ref
2 V
2.2
+
1
Q1 (1N2907A)
VRBF
U2
.01 µF
LSB D0
Analog Input
Can Be Either
Force Or Sense
VEE
VIN
50 W
50 W
CLK
2
100116
Convert
CLK
.01 µF
DGND
2 V
(Analog)
.01 µF
.01 µF
AGND
VEE
2 V (Digital)
5.2 V
GENERAL DESCRIPTION
The SPT7725 has true differential analog and digital data
paths from the preamplifiers to the output buffers (Current
Mode Logic) for reducing potential missing codes while
rejecting common mode noise.
The SPT7725 is a fast monolithic 8-bit parallel flash A/D
converter. The nominal conversion rate is 300 MSPS and
the analog bandwidth is in excess of 200 MHz.A major ad-
vance over previous flash converters is the inclusion of Signature errors are also reduced by careful layout of the
256 input preamplifiers between the reference ladder and analog circuitry. Every comparator also has a clock buffer
input comparators. (See block diagram.) This not only re- to reduce differential delays and to improve signal-to-
duces clock transient kickback to the input and reference noise ratio. The output drive capability of the device can
ladder due to a low AC beta but also reduces the effect of provide full ECL swings into 50 Ω loads.
the dynamic state of the input signal on the latching char-
acteristics of the input comparators. The preamplifiers act TYPICAL INTERFACE CIRCUIT
as buffers and stabilize the input capacitance so that it re-
The typical interface circuit is shown in figure 1. The
mains constant for varying input voltages and frequencies
SPT7725 is relatively easy to apply depending on the
and, therefore, makes the part easier to drive than previ-
accuracy needed in the intended application. Wire-wrap
ous flash converters. The SPT7725 incorporates a propri-
may be employed with careful point-to-point ground con-
etary decoding scheme that reduces metastable errors
nections if desired, but to achieve the best operation, a
(sparkle codes or flyers) to a maximum of 1 LSB.
SPT7725
5
8/17/01
Figure 2 – Typical Interface Circuit 2 (PGA and Cerquad packages only)
*See below
+
U1
Voltage
Limiter
VCC
10 W
Analog
Input
VEE
DGND AGND
L
RT
Force
5.2 V
VCC
U1
2.2 µF
.01 µF
22
+
Q1
D1
VRTF
LINV
MINV
VEE
VIN
VRTS
Preamp Comparator
256
Overrange
D8
Typical Voltage Limiter
Clock
Buffer
R
R
S
192
D1
5.2
49.9
D2
MSB
D7
191
151
10-25 W
VR3
+
U2
D6
D5
D4
D3
D2
D1
.01 µF
U1 and U2=
Rail-to-Rail Op Amp
D1=HP, 1N5712
Q1=1N2222A
R
128
127
10-25 W
Q2=1N2907A
VR2
+
U2
ECL
Latches
And
R = 1 kW, .1%
256 to
8-Bit
Encoder
.01 µF
Buffers
R
64
10-25 W
V
+
R1
U2
.01 µF
63
2
R
LSB
D0
VEE
VREF
2 V
1
22 W
+
U2
VRBF
VRBS
VEE
.01 µF
DRINV
DREAD
CLK
2
Convert
100116
50 W
50 W
AGND
VEE
AGND
CLK
Analog Input
(Sense)
VIN
2 V
.01 µF
.01 µF
2 V
(Analog)
.01 µF
.01 µF
2 V (Digital)
5.2 V
VEE
VEE, AGND, DGND
double-sided PC board with a ground plane on the compo-
nent side separated into digital and analog sections will
give the best performance.The converter is bonded-out to
place the digital pins on the left side of the package and
the analog pins on the right side. Additionally, an RF bead
connection through a single point from the analog to digi-
tal ground planes will reduce ground noise pickup.
VEE is the supply pin with AGND as ground for the device.
The power supply pins should be bypassed as close to the
device as possible with at least a .01 µF ceramic capaci-
tor. A 1 µF tantalum should also be used for low frequency
suppression. DGND is the ground for the ECL outputs and
is to be referenced to the output pulldown voltage and
appropriately bypassed as shown in figure 1.
The circuit in figure 2 (PGA and cerquad packages only) is
intended to show the most elaborate method of achieving
the least error by correcting for integral nonlinearity, input
induced distortion, and power supply/ground noise.This is
achieved by the use of external reference ladder tap con-
nections, an input buffer, and supply decoupling.The func-
tion of each pin and external connections to other compo-
nents is as follows:
VIN (ANALOG INPUT)
There are two analog input pins that are tied to the same
point internally. Either one may be used as an analog input
sense and the other for input force. This is convenient for
testing the source signal to see if there is sufficient drive
capability.The pins can also be tied together and driven by
SPT7725
6
8/17/01
Table I – Output Coding
BINARY
INVERTED
MINV=LINV=1 MINV=1; LINV=0 MINV=0; LINV=1
TWOs COMPLEMENT
TRUE
TRUE INVERTED
MINV=LINV=0
D7_____D0
ANALOG INPUT VOLTAGE D8
D7_____D0
D7_____D0
D7_____D0
–2 V + 1/2 LSB
0
0
0
1
00000000
00000001
11111111
11111110
10000000
10000001
01111111
01111110
–1.0 V
01111111
10000000
10000000
01111111
11111111
00000000
00000000
11111111
0 V – 1/2 LSB
≥0 V
11111111
11111110
00000000
00000001
01111111
01111110
10000000
10000001
11111111
00000000
01111111
10000000
the same source. The SPT7725 is superior to similar de- VRBF, VRBS, VR1, VR2, VR3, VRTF, VRTS REFERENCE
vices, due to a preamplifier stage before the comparators. INPUTS (PGA AND CERQUAD PACKAGES ONLY)
This makes the device easier to drive because it has con-
These are five external reference voltage taps from –2 V
stant capacitance and induces less slew rate distortion.
(VRBF) to AGND (VRTF) that can be used to control integral
An optional input buffer may be used.
linearity over temperature. The taps can be driven by op
amps as shown in figure 2. These voltage level inputs can
CLK, CLK (CLOCK INPUTS)
be bypassed to AGND for further noise suppression if so
The clock inputs are designed to be driven differentially
desired. VRB and VRT have force and sense pins for moni-
with ECL levels. The clock may be driven single-ended
toring the top and bottom voltage references.
since CLK is internally biased to –1.3 V. (See clock input
circuit.) CLK may be left open, but a .01 µF bypass capaci- N/C
tor from CLK to AGND is recommended. NOTE: System
All Not Connected pins should be tied to DGND on the left
performance may be degraded due to increased clock
side of the package and to AGND on the right side of the
noise or jitter.
package.
MINV, LINV (OUTPUT LOGIC CONTROL)
DREAD – DATA READY; DRINV – DATA READY
These are ECL-compatible digital controls for changing INVERSE (PGA AND CERQUAD PACKAGES ONLY)
the output code from straight binary to two’s complement,
The data ready pin is a flag that goes high or low at the
etc. For more information, see table I. Both MINV and
output when data is valid or ready to be received. It is es-
LINV are in the logic low (0) state when they are left open.
sentially a delay line that accounts for the time neces-
The high state can be obtained by tying to AGND through
sary for information to be clocked through the SPT7725’s
a diode or 3.9 kΩ resistor.
decoders and latches. This function is useful for interfac-
ing with high-speed memory. Using the data ready output
to latch the output data ensures minimum set-up and hold
times. DRINV is a data ready inverse control pin. (See the
timing diagram.)
D0 TO D7 (DIGITAL OUTPUTS)
The digital outputs can drive ECL levels into 50 Ω when
pulled down to –2 V. When pulled down to –5.2 V, the out-
puts can drive 150 Ω to 1 kΩ loads.
D8 – OVERRANGE (PGA AND CERQUAD PACKAGES
ONLY)
VRBF, VR2, VRTF (REFERENCE INPUTS)
There are two reference inputs and one external reference
This is an overrange function. When the SPT7725 is in an
voltage tap. These are –2 V (VRBF), mid-tap (VR2), and
AGND (VRTF).The reference pins can be driven as shown
in figure 1. VR2 should be bypassed to AGND for further
SPT7725 into higher resolution systems.
noise suppression.
overrange condition, D8 goes high and all data outputs go
high as well. This makes it possible to include the
SPT7725
7
8/17/01
OPERATION
sequence from the top comparators, closest to VRTF (0 V),
down to the point where the magnitude of the input signal
changes sign (thermometer code). The output of each
comparator is then registered into four 64-to-6 bit decod-
ers when CLK is changed from high to low.
The SPT7725 has 256 preamp/comparator pairs that are
each supplied with the voltage from VRTF to VRBF divided
equally by the resistive ladder as shown in the block dia-
gram. This voltage is applied to the positive input of each
preamplifier/comparator pair. An analog input voltage ap- At the output of the decoders is a set of four 7-bit latches
plied at VIN is connected to the negative inputs of each that are enabled (track) when CLK changes from high to
preamplifier/comparator pair. The comparators are then low. From here, the outputs of the latches are coded into
clocked through each comparator’s individual clock buffer. 6 LSBs from 4 columns, and 4 columns are coded into
When CLK pin is in the low state, the master or input stage 2 MSBs. Next are the MINV and LINV controls for output
of the comparators compares the analog input voltage to inversions, which consist of a set of eight XOR gates.
the respective reference voltage. When CLK changes Finally, 8 ECL output latches and buffers are used to drive
from low to high, the comparators are latched to the state the external loads. The conversion takes one clock cycle
prior to the clock transition and output logic codes in from the input to the data outputs.
Figure 3 – Timing Diagram
N+2
N
N+1
Analog Input
Clock
VIN
tPW0
tPW1
CLK
CLK
Master
Comparator Output
Slave
6 Bit Latch Output
8 Bit Latch Output
N1
N
N+1
Data Output D0D7
Overrange D8
Data Ready
tD
Timing for PGA and Cerquad Packages Only
SPT7725
8
8/17/01
Figure 4 – Subcircuit Schematics
Input Circuit
Output Circuit
MINV, LINV Input Circuit
AGND
AGND
DGND
AGND
10 kW
VIN
VR
MINV
LINV
1.3 V
Data Out
16 kW
VEE
VEE
Figure 5 – Clock Input
Figure 6 – Burn-In Circuit (42-lead DIP Package only)
VEE
AGND
1N4736
2.0 V
R4
VREF
R4
R3
R1 R1 R1 R1 R1 R1 R1 R1
CLK
1.3 V
13 kW
CLK
D0
D1
D2
D3
D4
D5
D6
D7
13 kW
VIN
R2
VIN
VEE
CLK
CLK
R2
R2
CLK
CLK
LINV
MINV
EVALUATION BOARDS
R2
The EB7725 evaluation board is available to aid designers
in demonstrating the full performance of the SPT7725.
This board includes a voltage reference circuit, clock
driver circuit, output data latches, and an on-board recon-
struction of the digital data. An application note describing
the operation of this board, as well as application tips, is
also available. Contact the factory for price and delivery.
R
1 = 50 W 1/4 Watt CC 5%
2 = 1 kW 1/4 Watt CC 5%
R
2.0 V
R3 = 6.5 W 1/4 Watt CC 5%
R4 = 6.5 W 1/2 Watt CC 5%
VREF = 2.0 Volts
V
EE = 6.6 Volts
SPT7725
9
8/17/01
PACKAGE OUTLINES
42-Lead Sidebrazed DIP
INCHES
MIN
0.081
0.016
0.095
MILLIMETERS
42
1
SYMBOL
MAX
0.099
0.020
0.105
MIN
MAX
2.51
0.51
2.67
A
B
C
D
E
F
G
H
I
J
2.06
0.41
2.41
G
.050 typ
.050 typ
0.275
1.27
1.27
A
6.99
53.85
15.37
0.38
E
F
2.080
0.585
0.008
0.600
2.120
0.605
0.015
0.620
52.83
14.86
0.20
C
D
B
H
J
15.24
15.75
I
46-Lead Pin Grid Array
INCHES
MILLIMETERS
D
SYMBOL
MIN
MAX
MIN
MAX
A
A
B
C
D
E
F
0.890
0.910
22.61
23.11
E
B
0.100 typ
.045 dia
0.084
0.169
.020 dia
2.54 typ
.055 dia
0.096
0.193
1.14
2.13
4.29
0.51
1.40
2.44
4.90
0.76
Pin 1
.030 dia
G
.050 typ
1.27 typ
F
C Diameter
Stand-off Pin
G
SPT7725
10
8/17/01
44-Lead Cerquad
INCHES
MIN MAX
0.550 typ
MILLIMETERS
MIN MAX
13.97 typ
SYMBOL
A
B
C
D
C
D
0.685
0.037
0.709
0.041
17.40
0.94
18.00
1.04
0.016 typ
0.008 typ
0.027 0.051
0.006 typ
0.080 0.089
0.41 typ
0.20 typ
0.69 1.30
0.15 typ
2.03 2.26
E
A
B
F
G
H
A
B
05°
H
G
E
F
SPT7725
11
8/17/01
42
41
40
N/C
VRTF
N/C
PIN ASSIGNMENTS
1
2
3
PIN FUNCTIONS
VEE
N/C
LINV
9
8
7
6
5
4
3
2
1
Name
LINV
VEE
Function
A
B
C
D
E
F
VEE 39
4
5
VEE
D8
D5
D4
D3
D2
D1
D0
DGND
D0 through D6 Output Inversion Control Pin
Negative Analog Supply Nominally –5.2 V
Digital Ground
D6
D7
VEE
N/C
38
37
AGND
DGND
AGND
DREAD AGND
6
7
8
N/C 36
V
DGND
N/C
V
EE
D0 (LSB)
DGND
D0
EE
AGND
35
34
Bottom
View
D1
D2
D3
D4
MINV
CLK
LINV DRINV
Digital Data Output (LSB)
Digital Data Output
CLK
VIN
AGND
VR2
9
33
32
D1–D6
D7
V
V
AGND
AGND
10
DIP
EE
EE
11
Digital Data Output (MSB)
D7 Output Inversion Control Pin
Inverse ECL Clock Input Pin
ECL Clock Input Pin
AGND AGND
V
RTS
PGA
AGND 31
12
13
D5
D6
G
H
J
MINV
CLK
V
V
N/C
V
VIN
RBS
EE
RTF
30
29
28
AGND
14
15
16
17
D7 (MSB)
DGND
AGND
VEE
V
V
V
V
EE
RBF
R1
R3
N/C
CLK
AGND
VIN
N/C
AGND
V
AGND
V
AGND
V
IN
AGND
N/C
IN
R2
N/C 27
VEE
VEE
26
25
Analog Ground
18
19
MINV
N/C
Analog Input; Can be Connected to the
Input Signal or Used as a Sense
N/C 24
VRBF 23
N/C 22
20
21
CLK
CLK
VR2
Reference Voltage Tap 2 (–1.0 V typ)
Reference Voltage Top
VRTF
VRBF
Reference Voltage Bottom
DGND
AGND
VEE
1
2
33
AGND
VEE
32
LINV
N/C
3
4
5
6
31
30
29
The following pins are on PGA and cerquad packages only.
MINV
CLK
DRINV
N/C
DRINV
Data Ready Inverse
Data Ready Output
Cerquad
CLK
28
27
26
25
VEE
VEE
7
8
9
DREAD
AGND
AGND
VRBS
VRBF
AGND
AGND
VRTS
VRTF
Overrange Overrange Output D8
10
11
24
23
VR1
Reference Voltage Tap 1 (–1.5 V typ)
VR3
Reference Voltage Tap 3 (–0.5 V typ)
Reference Voltage Top, Sense
VRTS
VRBS
Reference Voltage Bottom, Sense
ORDERING INFORMATION
PART NUMBER
SPT7725AIJ
SPT7725BIJ
SPT7725AIG
SPT7725BIG
SPT7725AIQ
SPT7725BIQ
SPT7725BCU
LINEARITY
TEMPERATURE RANGE
–25 to +85 °C
–25 to +85 °C
–25 to +85 °C
–25 to +85 °C
–25 to +85 °C
–25 to +85 °C
+25 °C
PACKAGE TYPE
42L Ceramic S/B
42L Ceramic S/B
46L PGA
0.75 LSB
0.95 LSB
0.75 LSB
0.95 LSB
0.75 LSB
0.95 LSB
0.95 LSB
46L PGA
44L Cerquad
44L Cerquad
Die*
*Please see the die specification for guaranteed electrical performance.
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO
IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR
USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR
THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems which, (a) are
intended for surgical implant into the body, or (b) support or sustain life,
and whose failure to perform, when properly used in accordance with
instructions for use provided in the labeling, can be reasonably
expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or
system whose failure to perform can be reasonably expected to cause
the failure of the life support device or system, or to affect its safety or
effectiveness.
www.fairchildsemi.com
© Copyright 2002 Fairchild Semiconductor Corporation
SPT7725
12
8/17/01
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