SPT7730SCS [FAIRCHILD]
8-BIT, 3.0 MSPS, SERIAL OUTPUT A/D CONVERTER; 8位， 3.0 MSPS ，串行输出A / D转换器
| 型号： | SPT7730SCS |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 8-BIT, 3.0 MSPS, SERIAL OUTPUT A/D CONVERTER |
| 文件： | 总8页 (文件大小：64K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SPT7730
8-BIT, 3.0 MSPS, SERIAL OUTPUT A/D CONVERTER
FEATURES
APPLICATIONS
• 8-Bit, 1 kHz to 3.0 MSPS Analog-to-Digital Converter
• Monolithic CMOS
• Serial Output
• Handheld and Desktop Scanners
• DSP Interface Applications
• Portable Digital Radios
• Internal Sample-and-Hold
• Portable and Handheld Applications
• Automotive Applications
• Remote Sensing
• Analog Input Range: 0 to 2 V Nominal; 3.3 V Max
• Power Dissipation (Excluding Reference Ladder)
45 mW at +5 V
16 mW at +3 V
• Single Power Supply: +3 V to +5 V Range
• High ESD Protection: 3,000 V Minimum
GENERAL DESCRIPTION
The Fairchild 8-bit, 3.0 MSPS, serial analog-to-digital con-
verterdeliversexcellenthighspeedconversionperformance
with low cost and low power. The serial port protocol is
compatible with the serial peripheral interface (SPI) or
MICROWIRE™industry standard, high-speed synchronous
MPUinterfaces. Thelargeinputbandwidthandfasttransient
response time allow for CCD applications operating up to
3.0 MSPS.
The device can operate with a power supply range from +3 V
to +5 V with very low power dissipation. The small package
size makes this part excellent for handheld applications
where board space is a premium. The SPT7730 is available
in an 8-lead SOIC package over the commercial tempera-
ture range. Contact the factory for availability of die and
industrial temperature range versions.
BLOCK DIAGRAM
V
Ground
DD
Track-and-Hold
SAR
Serial
Output
Logic
Analog Input
Data Out
8-Bit
A/D
Clock
Timing And Control
Start Convert
V
V
REF+
REF-
1
ABSOLUTE MAXIMUM RATING (Beyond which damage may occur)
Output
Supply Voltages
...........................................................................+6 V
Data Out ................................................................10 mA
V
DD
Temperature
Input Voltages
Operating,
ambient ..................................... 0 to 70 °C
junction........................................ + 175 °C
Analog Input ................................................. -0.7 to +6 V
V
V
+ ........................................................... -0.7 to +6 V
REF
- ............................................................ -0.7 to +6 V
REF
Lead, Soldering (10 seconds) ........................... + 300 °C
Storage ................................................... -65 to + 150 °C
Clock and
............................................... -0.7 to +6 V
SC
Note: 1. Operation at any Absolute Maximum Ratings is not implied. See Electrical Specifications for proper nominal applied
conditions in typical applications.
ELECTRICAL SPECIFICATIONS
T
= +25 °C, V
= +5.0 V, V = 0 to +3 V, f
= 36 MHz, f = 3.0 MSPS, V
+ = +3.0 V, V - = 0.0 V, unless otherwise specified.
REF
A
DD
IN
CLK
S
REF
TEST
CONDITIONS
TEST
PARAMETERS
LEVEL
MIN
TYP
MAX
UNITS
DC ELECTRICAL CHARACTERISTICS
DC Performance
Resolution
8
±0.2
Bits
LSB
LSB
Differential Linearity
Integral Linearity
No Missing Codes
I
I
I
±0.5
±0.5
±0.2
Guaranteed
Analog Input
1
Input Voltage Range
IV
I
V
REF-
+4%
5
V
REF+
-6%
V
Input Resistance
Input Capacitance
Input Bandwidth (Small Signal)
Offset
MΩ
IV
IV
IV
IV
5
pF
30
MHz
-2
-2
+2
+2
% of FSR
% of FSR
Gain Error
Reference Input
Resistance
IV
250
-4%
280
0
350
Ω
1
Voltage Range
2
V
V
V
IV
IV
IV
IV
V
-∆
V
REF-
REF+
2
V
+∆
2/3 V
V
V
ns
REF+
REF-
DD
-V
(∆)
1/10 V
REF+ REF-
DD
Reference Settling Time
90
Timing Characteristics
Maximum Conversion Rate
Minimum Conversion Rate
Maximum External Clock Rate
Minimum External Clock Rate
Aperture Delay Time
I
3.0
1
1.0
12
MSPS
kSPS
MHz
kHz
ns
IV
I
36
12
IV
IV
IV
IV
5
5
8
Aperture Jitter Time
ps
Data Ouput LSB Hold Time
T
to T
6
ns
MIN
MAX
1
Percentages refer to percent of [(V
) -(V
)]
REF-
REF+
2
∆ = Minimum (V
-V
)
REF+ REF-
SPT7730
2
12/19/97
ELECTRICAL SPECIFICATIONS
T
= +25 °C, V
= +5.0 V, V = 0 to +3 V, f
= 36 MHz, f = 3.0 MSPS, V
+ = +3.0 V, V - = 0.0 V, unless otherwise specified.
REF
A
DD
IN
CLK
S
REF
TEST
TEST
PARAMETERS
CONDITIONS
LEVEL
MIN
TYP
MAX
UNITS
Dynamic Performance
Effective Number of Bits
f
= 500 kHz
IV
IV
IV
7.5
47
60
Bits
dB
IN
Signal-to-Noise Ratio
= 500 kHz
f
IN
Harmonic Distortion
= 500 kHz
f
dB
IN
3
Power Supply Requirements
+V Supply Voltage
+V Supply Current
DD
IV
IV
3
5.5
7
V
mA
DD
V
= 3.0 V
= 5.0 V
= 3.0 V
= 5.0 V
5.4
9
DD
DD
DD
DD
V
V
V
I
IV
I
10
22
50
mA
Power Dissipation
16
45
mW
mW
3
Excluding the reference ladder.
TEST LEVEL
TEST PROCEDURE
100% production tested at the specified temperature.
TEST LEVEL CODES
All electrical characteristics are subject to the
following conditions:
I
II
100% production tested at T =25 °C, and sample
A
tested at the specified temperatures.
All parameters having min/max specifications
are guaranteed. The Test Level column indi-
cates the specific device testing actually per-
formed during production and Quality Assur-
ance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.
III
QA sample tested only at the specified temperatures.
IV
Parameter is guaranteed (but not tested) by design
and characterization data.
V
Parameter is a typical value for information purposes
only.
VI
100% production tested at T = 25 °C. Parameter is
A
guaranteed over specified temperature range.
SPT7730
3
12/19/97
should be taken to ensure that the LSB is latched into an
external latch with the proper amount of set and hold time.
GENERAL DESCRIPTION AND OPERATION
The SPT7730 is an 8-bit analog-to-digital converter that
uses a successive approximation architecture to perform
data conversion. Each conversion cycle is 12 clocks in
DATA OUTPUT CODING
The coding of the output is straight binary. (See table I.)
Table I - Data Output Coding
length. When the Not Start Convert ( ) line is held low,
SC
conversion begins on the next rising edge of the input clock.
When the conversion cycle begins, the data output pin is
forced low until valid data output begins.
ANALOG INPUT
+FS - 1/2 LSB
+1/2 FS
OUTPUT CODE D7 - DO
1 1 1 1
ØXXX
OOOO
OOOO
1 1 1 Ø
XXXX
OOOØ
OOOO
The first two clock cycles are used to perform internal offset
calibrations and to track the analog input. The analog input
is then sampled using an internal track-and-hold amplifier on
the falling edge of the third clock cycle. On clock cycles 4
through 12, an 8-bit successive approximation conversion is
performed, and the data is output starting with the MSB.
+1/2 LSB
V
REF-
Ø indicates the flickering bit between logic O and 1.
X indicates the flickering bit between logic 1 and O.
Serial data output begins with output of the MSB. See the
Data Output Timing section for details. Each bit of the data
conversion is sequentially determined and placed on the
data output pin at the clock rate. This process continues until
the LSB has been determined and output. At this point, if the
ANALOG INPUT AND REFERENCE SETTLING TRACK
AND HOLD TIMING
Figure 9 shows the timing relationship between the input
clock and
versus the analog input tracking and reference
SC
settling. The analog input is tracked from the twelfth clock
cycleofthepreviousconversiontothethirdclockcycleofthe
current conversion. On the falling edge of the third clock
cycle, the analog input is held by the internal sample-and-
hold. After this sample, the analog input may vary without
affecting data conversion.
line is high, the data output pin will be forced into a high
SC
impedance state, and the converter will go into an idle state
waiting for the line to go low. This is referred to as Single
SC
Shot Mode. See Modes of Operation for details.
If the is either held low through the entire 12 clock
SC
conversioncycle(freerunmode)orisbroughtlowpriortothe
trailing edge of the twelfth clock cycle (synchronous mode),
the data output pin goes low and stays low until valid data
output begins. Because the chip has either remained se-
lectedinthefreerunmodeorhasbeenimmediatelyselected
again in the synchronous mode, the next conversion cycle
begins immediately after the twelfth clock cycle of the previ-
ous conversion. See Modes of Operation for details.
The reference ladder inputs (V
+ and V
REF
-) may be
REF
changed starting on the falling edge of the eleventh clock
cycle of the previous conversion and must be settled by the
falling edge of the third clock cycle of the current conversion.
(See figure 9.)
VOLTAGE REFERENCE AND ANALOG INPUT
The SPT7730 requires the use of a single external voltage
reference for driving the high side of the reference ladder.
TYPICAL INTERFACE CIRCUIT
The V
+ can be a maximum of 2/3 V . For example, if
REF
DD
CLOCK INPUT
V
= +5 V, then V
+ max = (2/3) 5 V = +3.3 V. The lower
REF *
DD
TheSPT7730requiresa50%±10%dutycycleclockrunning
at 12 times the desired sample rate. The clock may be
stopped in between conversion cycles without degradation
of operation (single shot type of operation), however, the
clock should remain running during a conversion cycle.
side of the ladder is typically tied to AGND (0.0 V) but can be
run up to a voltage that is 1/10th of V below V +:
DD
REF
V
- max. = V
+ - (1/10) V
.
DD
REF
REF
*
For example,
if V = +5 V and V
+ = 3 V, then
REF
DD
POWER SUPPLY
V
- max. = 3 V - (1/10) 5 V = 2.5 V.
REF
*
The SPT7730 requires only a single supply and operates
from3.0Vto5.0V. Fairchildrecommendsthata0.01µFchip
capacitor be placed as close as possible to the supply pin.
The+FullScale(+FS)oftheanaloginputisexpectedtobe6%
of [(V +)-(V -)] below V + and the -Full Scale (-FS)
REF
REF
REF
of the analog input is expected to be 4% of [(V
+) - (V -)]
REF REF
DATA OUTPUT SET UP AND HOLD TIMING
above V
-. (See figure 1.)
REF
As figure 8 shows, all of the data output bits (except the LSB)
remains valid for a duration equivalent to one clock period
and delayed by 8 ns after the falling edge of clock. Because
the data converter enters into a next conversion ready state
at the leading edge of clock 12, the LSB bit is valid for a
duration equivalent to only the clock pulse width low
and delayed by 8 ns after the falling edge of clock. Care
Therefore,
Analog +FS = V
+ - 0.06 * [(V
+) - (V
-)], and
-)].
REF
REF
REF
Analog -FS = V
- +0.04 * [(V
+) - (V
REF
REF
REF
For example,
if V
+ = 3 V and V
- = 0 V, then
REF
REF
Analog + FS = 3 V - 0.06 * [3 V- 0 V ] = 2.82 V, and
Analog - FS = 0 V + 0.04 * [3 V - 0 V] = 0.12 V.
SPT7730
4
12/19/97
Figure 1 - Analog Input Full-Scale Range
MODES OF OPERATION
V
REF
+
+FS
The SPT7730 has three modes of operation.The mode of
operation is based strictly on how the
is used.
SC
6% of [(V
REF
+) - (V
REF
-)]
SINGLE SHOT MODE
When
goes low, conversion starts on the next rising edge
SC
of the clock (defined as the first conversion clock). The MSB
of data is valid 8 ns after the falling edge of the fourth
conversion clock. (See figure 8.)
4% of [(V
+) - (V -)]
REF
REF
-FS
-
The conversion is complete after 12 clock cycles. At the
V
REF
falling edge of the twelfth clock cycle, if
selected), the data output goes to a high impedance state,
and no more conversions will take place until the next low
is high (not
SC
The drive requirements for the analog input are minimal
when compared to most other converters due to the
SPT7730’s extremely low input capacitance of only 5 pF and
very high input resistance of greater than 5 MΩ.
SC
event. (See the single shot mode timing diagram in figure 4.)
SYNCHRONIZED MODE
If the input buffer amplifier supply voltages are greater than
When
goes low, conversion will start on the next rising
SC
V
+ 0.7 V or less than Ground - 0.7 V, the analog input
DD
edge of the clock (defined as the first conversion clock). The
MSB is valid 8 ns after the falling edge of the fourth conver-
sion clock.
should be protected through a series resistor and a diode
clamping circuit as shown in figure 2.
Figure 2 - Recommended Input Protection Circuit
The first conversion is complete after 12 clock cycles. At
AV
+V
DD
any time after the falling edge of the twelfth clock cycle,
SC
may go low again to initiate the next conversion. When the
goes low, the conversion starts on the rising edge of the
next clock. (See the synchronized mode timing diagram
in figure 5.)
SC
D1
D2
Buffer
ADC
47 Ω
The data output will go to a high impedance state until the
next conversion is initiated.
FREE RUN MODE
-V
When
goes low, conversion starts on the next rising edge
SC
D1 = D2 = Hewlett Packard HP5712 or equivalent
of the clock (defined as the first conversion clock). The MSB
data is valid 8 ns after the falling edge of the fourth conver-
sion clock.
INPUT PROTECTION
All I/O pads are protected with an on-chip protection circuit
shown in figure 3. This circuit provides ESD robustness to
>3.0 kV and prevents latch-up under severe discharge
conditions without degrading analog transition times.
As long as
is held low, the device operates in the free run
SC
mode. New conversions start after every twelfth cycle with
valid data available 8 ns after the falling edge of the fourth
clock within each new conversion cycle.
Figure 3 - On-Chip Protection Circuit
The data output remains low between conversion cycles.
(See the free run mode timing diagram in figure 6.)
V
DD
Analog
120 Ω
120 Ω
Pad
SPT7730
5
12/19/97
Figure 4 - Single Shot Mode Timing Diagram
t
SC
Start Convert
Latch
MSB
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
Clock
High Z State
Serial Data Out
A7
A6
A5
A4
A3
A2
A1
A0
LSB
MSB
Start
Conversion
Sample
Analog Input
Figure 5 - Synchronous Mode Timing Diagram
t
t
SC
SC
Latch
MSB
Latch
MSB
Start Convert
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
11
A
12
A
1
B
2
B
3
B
4
B
5
B
Clock
High Z State
Serial Data Out
A7
A6
A5
A4
A1
A0
B7
MSB
LSB
MSB
Start
Sample
Analog Input
A
Sample
Analog Input
B
Figure 6 - Free Run Mode Timing Diagram
Latch
MSB
Start Convert
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
1
1
A
1
2
A
1
B
2
B
3
B
4
B
5
B
6
B
7
B
Clock
Serial Data Out
A7
A6
A5
A4
A1
A0
LSB
B7
B6
B5
MSB
MSB
Start
Sample
Analog Input
A
Sample
Analog Input
B
Figure 7 - Typical Interface Circuit
Figure 8 - Data Output Timing
t =8 ns
t =8 ns
t =8 ns
t =8 ns
d
d
d
d
V
+
V
DD
REF
REF IN
+V
DD
.01 µF
.01 µF
1
1
A
1
2
A
4
A
5
A
V
+V
REF+
0 V
DD
0 V
Analog In
Data Out
Clock
SC
V
Clock
IN
+V
V
-
DD
0 V
REF
Data Out
A7
MSB
A1
A0
LSB
+V
DD
Ground
0 V
SPT7730
6
12/19/97
Figure 9 - Analog Input Track-and-Hold Timing and Reference Settling-and-Hold Timing
Single Shot Mode
SC high, no B cycle)
Synchronous Mode
*
(
SC
Free Run Mode (SC always Ø)
Clock
1
A
2
A
3
A
4
A
11
A
12
A
1
B
2
B
3
B
4
B
V
REF+
Ref Hold
Ref Settling Window**
A
IN
Sample
Input
Sample
Input
*
The rising edge of the SC line can occur any time between the
rising edge of clock 1A and the falling edge of clock 12A.
The reference settling window can be extended in the
synchronous mode by adding extra clocks between conversion
cycles. The example shown is the minimum number of clocks
required (12) per conversion cycle.
**
PACKAGE OUTLINE
8-Lead SOIC
INCHES
MILLIMETERS
MIN MAX
4.98
A
SYMBOL
MIN
MAX
0.194
0.242
A
B
C
D
E
F
G
H
I
0.187
0.228
0.050 typ
0.014
0.005
0.060
0.055
0.149
0°
4.80
5.84
1.27 typ
0.35
0.13
1.55
1.40
3.81
0°
6.20
0.019
0.010
0.067
0.060
0.156
8°
0.49
0.25
1.73
1.55
3.99
8°
B
J
0.007
0.016
0.010
0.035
0.19
0.41
0.25
0.89
K
H
G
I
J
F
K
C
D
E
SPT7730
7
12/19/97
PIN FUNCTIONS
PIN ASSIGNMENTS
Name
Function
External V
+
1
2
3
4
8
7
6
5
V
REF
Analog In
External V
Analog In
Analog Signal Input
DD
Start Convert
Start Convert. A high-to-low transition on
this input begins the conversion cycle and
enables serial data output.
Data Out
Clock
-
REF
Ground
Clock
Clock that drives A/D conversion cycle and
the synchronous serial data output
Start Convert
Data Out
Serial Data. Tri-state serial data output for
the A/D result driven by the CLOCK input
External V
External V
+
-
External voltage reference for top of
reference ladder
REF
REF
External voltage reference for bottom of
reference ladder
V
Analog and Digital +3 V to +5 V
Power Supply Input
DD
GND
Analog and Digital Ground
ORDERING INFORMATION
PART NUMBER
TEMPERATURE RANGE
0 to +70 °C
PACKAGE
8L SOIC
Die*
SPT7730SCS
SPT7730SCU*
+25 °C
*Please see the die specification for guaranteed electrical performance.
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO
IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF
ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF
OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD'SPRODUCTSARENOTAUTHORIZEDFORUSEASCRITICALCOMPONENTSINLIFESUPPORTDEVICESORSYSTEMSWITHOUTTHE
EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems which, (a) are
intended for surgical implant into the body, or (b) support or sustain life,
and whose failure to perform, when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected
to result in a significant injury to the user.
2. A critical component is any component of a life support device or system
whose failure to perform can be reasonably expected to cause the failure
of the life support device or system, or to affect its safety or effectiveness.
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© Copyright 2002 Fairchild Semiconductor Corporation
SPT7730
8
12/19/97
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