SSP7N60B [FAIRCHILD]

600V N-Channel MOSFET; 600V N沟道MOSFET
SSP7N60B
型号: SSP7N60B
厂家: FAIRCHILD SEMICONDUCTOR    FAIRCHILD SEMICONDUCTOR
描述:

600V N-Channel MOSFET
600V N沟道MOSFET

文件: 总11页 (文件大小:916K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
SSP7N60B/SSS7N60B  
600V N-Channel MOSFET  
General Description  
Features  
These N-Channel enhancement mode power field effect  
transistors are produced using Fairchild’s proprietary,  
planar, DMOS technology.  
This advanced technology has been especially tailored to  
minimize on-state resistance, provide superior switching  
performance, and withstand high energy pulse in the  
avalanche and commutation mode. These devices are well  
suited for high efficiency switch mode power supplies.  
7.0A, 600V, R  
= 1.2@V = 10 V  
DS(on) GS  
Low gate charge ( typical 38 nC)  
Low Crss ( typical 23 pF)  
Fast switching  
100% avalanche tested  
Improved dv/dt capability  
TO-220F package isolation = 4.0kV (Note 6)  
D
G
TO-220  
SSP Series  
TO-220F  
SSS Series  
S
G
D S  
G D  
S
Absolute Maximum Ratings  
T = 25°C unless otherwise noted  
C
Symbol  
Parameter  
SSP7N60B  
SSS7N60B  
Units  
V
V
I
Drain-Source Voltage  
600  
DSS  
- Continuous (T = 25°C)  
Drain Current  
7.0  
4.4  
28  
7.0 *  
4.4 *  
28 *  
A
D
C
- Continuous (T = 100°C)  
A
C
I
(Note 1)  
Drain Current  
- Pulsed  
A
DM  
V
E
I
Gate-Source Voltage  
± 30  
420  
7.0  
V
GSS  
AS  
(Note 2)  
(Note 1)  
(Note 1)  
(Note 3)  
Single Pulsed Avalanche Energy  
Avalanche Current  
mJ  
A
AR  
E
Repetitive Avalanche Energy  
Peak Diode Recovery dv/dt  
14.7  
5.5  
mJ  
V/ns  
W
AR  
dv/dt  
P
Power Dissipation (T = 25°C)  
147  
48  
D
C
- Derate above 25°C  
Operating and Storage Temperature Range  
1.18  
0.38  
W/°C  
°C  
T , T  
-55 to +150  
300  
J
STG  
Maximum lead temperature for soldering purposes,  
T
°C  
L
1/8" from case for 5 seconds  
* Drain current limited by maximum junction temperature  
Thermal Characteristics  
Symbol  
Parameter  
SSP7N60B  
SSS7N60B  
Units  
°C/W  
°C/W  
°C/W  
R
R
R
Thermal Resistance, Junction-to-Case Max.  
Thermal Resistance, Case-to-Sink Typ.  
0.85  
0.5  
2.6  
--  
θJC  
θCS  
Thermal Resistance, Junction-to-Ambient Max.  
62.5  
62.5  
θJA  
©2002 Fairchild Semiconductor Corporation  
Rev. B, June 2002  
Electrical Characteristics  
T = 25°C unless otherwise noted  
C
Symbol  
Parameter  
Test Conditions  
Min  
Typ  
Max  
Units  
Off Characteristics  
BV  
V
= 0 V, I = 250 µA  
GS D  
Drain-Source Breakdown Voltage  
600  
--  
--  
--  
--  
V
DSS  
BV  
Breakdown Voltage Temperature  
Coefficient  
DSS  
I
= 250 µA, Referenced to 25°C  
0.65  
V/°C  
D
/
T  
J
I
V
V
V
V
= 600 V, V = 0 V  
--  
--  
--  
--  
--  
--  
--  
--  
10  
100  
100  
-100  
µA  
µA  
nA  
nA  
DSS  
DS  
GS  
Zero Gate Voltage Drain Current  
= 480 V, T = 125°C  
DS  
GS  
GS  
C
I
= 30 V, V = 0 V  
Gate-Body Leakage Current, Forward  
Gate-Body Leakage Current, Reverse  
GSSF  
DS  
I
= -30 V, V = 0 V  
GSSR  
DS  
On Characteristics  
V
V
V
V
= V , I = 250 µA  
Gate Threshold Voltage  
2.0  
--  
--  
4.0  
1.2  
--  
V
S
GS(th)  
DS  
GS  
DS  
GS  
D
R
Static Drain-Source  
On-Resistance  
DS(on)  
= 10 V, I = 3.5 A  
1.0  
8.2  
D
g
= 40 V, I = 3.5 A  
(Note 4)  
Forward Transconductance  
--  
FS  
D
Dynamic Characteristics  
C
C
C
Input Capacitance  
--  
--  
--  
1380  
115  
23  
1800  
150  
30  
pF  
pF  
pF  
iss  
V
= 25 V, V = 0 V,  
GS  
DS  
Output Capacitance  
oss  
rss  
f = 1.0 MHz  
Reverse Transfer Capacitance  
Switching Characteristics  
t
t
t
t
Turn-On Delay Time  
Turn-On Rise Time  
Turn-Off Delay Time  
Turn-Off Fall Time  
Total Gate Charge  
Gate-Source Charge  
Gate-Drain Charge  
--  
--  
--  
--  
--  
--  
--  
30  
80  
70  
170  
260  
180  
50  
ns  
ns  
d(on)  
V
= 300 V, I = 7.0 A,  
DD  
D
r
R
= 25 Ω  
G
125  
85  
ns  
d(off)  
f
(Note 4, 5)  
(Note 4, 5)  
ns  
Q
Q
Q
38  
nC  
nC  
nC  
g
V
V
= 480 V, I = 7.0 A,  
DS  
D
6.4  
15  
--  
= 10 V  
gs  
gd  
GS  
--  
Drain-Source Diode Characteristics and Maximum Ratings  
I
Maximum Continuous Drain-Source Diode Forward Current  
--  
--  
--  
--  
--  
--  
--  
7.0  
28  
1.4  
--  
A
A
S
I
Maximum Pulsed Drain-Source Diode Forward Current  
SM  
V
t
V
V
= 0 V, I = 7.0 A  
Drain-Source Diode Forward Voltage  
Reverse Recovery Time  
--  
V
SD  
GS  
S
= 0 V, I = 7.0 A,  
415  
4.6  
ns  
µC  
rr  
GS  
S
dI / dt = 100 A/µs  
Q
(Note 4)  
Reverse Recovery Charge  
--  
F
rr  
Notes:  
1. Repetitive Rating : Pulse width limited by maximum junction temperature  
2. L = 15.7mH, I = 7.0A, V = 50V, R = 25 Ω, Starting T = 25°C  
AS  
DD  
G
J
3.  
I
7.0A, di/dt 300A/µs, V  
BV Starting T = 25°C  
SD  
DD  
DSS, J  
4. Pulse Test : Pulse width 300µs, Duty cycle 2%  
5. Essentially independent of operating temperature  
6. Only for back side in V = 4.0kV and t = 0.3s  
iso  
©2002 Fairchild Semiconductor Corporation  
Rev. B, June 2002  
Typical Characteristics  
VGS  
Top :  
15.0V  
10.0 V  
8.0 V  
7.0 V  
6.5 V  
6.0 V  
5.5 V  
101  
101  
Bottom: 5.0V  
150oC  
25oC  
100  
100  
-55oC  
Notes :  
Notes :  
1. V = 40V  
μ
1. 250 s Pulse Test  
DS μ  
-1  
10  
2. 250 s Pulse Test  
2. TC = 25  
-1  
10  
-1  
10  
100  
101  
2
4
6
8
10  
VGS, Gate-Source Voltage [V]  
VDS, Drain-Source Voltage [V]  
Figure 1. On-Region Characteristics  
Figure 2. Transfer Characteristics  
5
4
3
2
1
0
101  
VGS = 10V  
VGS = 20V  
100  
150  
25  
Notes :  
1. V = 0V  
GS μ  
2. 250 s Pulse Test  
Note : T = 25  
J
-1  
10  
0
5
10  
15  
20  
25  
0.2  
0.4  
0.6  
0.8  
1.0  
1.2  
1.4  
ID, Drain Current [A]  
VSD, Source-Drain voltage [V]  
Figure 3. On-Resistance Variation vs  
Drain Current and Gate Voltage  
Figure 4. Body Diode Forward Voltage  
Variation with Source Current  
and Temperature  
3000  
2500  
2000  
1500  
1000  
500  
12  
10  
8
C
iss = Cgs + Cgd (Cds = shorted)  
Coss = Cds + C  
gd  
Crss = C  
gd  
VDS = 120V  
VDS = 300V  
VDS = 480V  
C
iss  
6
C
4
oss  
Notes :  
1. VGS = 0 V  
2. f = 1 MHz  
C
2
rss  
Note: ID = 7.0 A  
35  
0
0
10  
-1  
1
10  
100  
0
5
10  
15  
20  
25  
30  
40  
QG, Total Gate Charge [nC]  
VDS, Drain-Source Voltage [V]  
Figure 5. Capacitance Characteristics  
Figure 6. Gate Charge Characteristics  
©2002 Fairchild Semiconductor Corporation  
Rev. B, June 2002  
Typical Characteristics (Continued)  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
1.2  
1.1  
1.0  
Notes :  
0.9  
1. VGS = 0 V  
Notes :  
2. ID = 250 μA  
1. VGS = 10 V  
2. ID = 3.5 A  
0.8  
-100  
-100  
-50  
0
50  
100  
150  
200  
-50  
0
50  
100  
150  
200  
TJ, Junction Temperature [oC]  
T, Junction Temperature [oC]  
J
Figure 7. Breakdown Voltage Variation  
vs Temperature  
Figure 8. On-Resistance Variation  
102  
101  
100  
102  
Operation in This Area  
is Limited by R DS(on)  
Operation in This Area  
is Limited by R DS(on)  
100 µs  
10 µs  
100 µs  
101  
100  
1 ms  
1 ms  
10 ms  
10 ms  
100 ms  
DC  
DC  
-1  
10  
-1  
10  
Notes :  
Notes :  
1. TC = 25 oC  
1. TC = 25 oC  
2. T = 150 oC  
2. T = 150 oC  
J
J
3. Single Pulse  
3. Single Pulse  
-2  
-2  
10  
10  
0
1
10  
102  
103  
0
1
10  
10  
102  
103  
10  
VDS, Drain-Source Voltage [V]  
VDS, Drain-Source Voltage [V]  
Figure 9-1. Maximum Safe Operating Area  
for SSP7N60B  
Figure 9-2. Maximum Safe Operating Area  
for SSS7N60B  
8
6
4
2
0
25  
50  
75  
100  
125  
150  
TC, Case Temperature [  
]
Figure 10. Maximum Drain Current  
vs Case Temperature  
©2002 Fairchild Semiconductor Corporation  
Rev. B, June 2002  
Typical Characteristics (Continued)  
1 0 0  
D = 0 .5  
N otes  
1. Z θ JC(t)  
2. D uty Factor, D =t1/t2  
:
/W M ax.  
=
0.85  
0 .2  
3. T JM  
-
TC  
=
P D M * Zθ JC(t)  
1 0 -1  
0 .1  
0 .0 5  
PDM  
0 .0 2  
0 .0 1  
t1  
s in g le p u ls e  
t2  
1 0 -2  
1 0-5  
1 0-4  
1 0-3  
1 0-2  
1 0-1  
1 00  
1 01  
t1 , S q u a re W a v e P u ls e D u ra tio n [s e c ]  
Figure 11-1. Transient Thermal Response Curve for SSP7N60B  
D = 0 .5  
1 0 0  
0 .2  
N otes  
1. Zθ JC (t)  
2. D uty Factor, D =t1/t2  
:
/W M ax.  
=
2.6  
0 .1  
3. TJM  
- TC = P D M * Z θ JC(t)  
0 .0 5  
1 0 -1  
0 .0 2  
0 .0 1  
PDM  
t1  
t2  
sin g le p u lse  
1 0 -2  
1 0-5  
1 0-4  
1 0-3  
1 0-2  
1 0-1  
1 00  
1 01  
t1 , S qu a re W ave P u lse D u ra tion [se c]  
Figure 11-2. Transient Thermal Response Curve for SSS7N60B  
©2002 Fairchild Semiconductor Corporation  
Rev. B, June 2002  
Gate Charge Test Circuit & Waveform  
VGS  
Same Type  
50K  
as DUT  
Qg  
12V  
200nF  
10V  
300nF  
VDS  
VGS  
Qgs  
Qgd  
DUT  
3mA  
Charge  
Resistive Switching Test Circuit & Waveforms  
RL  
VDS  
90%  
VDS  
VDD  
VGS  
RG  
10%  
VGS  
DUT  
10V  
td(on)  
tr  
td(off)  
tf  
t on  
t off  
Unclamped Inductive Switching Test Circuit & Waveforms  
BVDSS  
--------------------  
BVDSS - VDD  
L
1
2
2
----  
EAS  
=
L IAS  
VDS  
I D  
BVDSS  
IAS  
RG  
VDD  
ID (t)  
VDD  
VDS (t)  
DUT  
10V  
t p  
t p  
Time  
©2002 Fairchild Semiconductor Corporation  
Rev. B, June 2002  
Peak Diode Recovery dv/dt Test Circuit & Waveforms  
+
DUT  
VDS  
_
I SD  
L
Driver  
RG  
Same Type  
as DUT  
VDD  
VGS  
• dv/dt controlled by RG  
• ISD controlled by pulse period  
Gate Pulse Width  
--------------------------  
VGS  
D =  
Gate Pulse Period  
10V  
( Driver )  
IFM , Body Diode Forward Current  
I SD  
di/dt  
( DUT )  
IRM  
Body Diode Reverse Current  
Body Diode Recovery dv/dt  
VSD  
VDS  
( DUT )  
VDD  
Body Diode  
Forward Voltage Drop  
©2002 Fairchild Semiconductor Corporation  
Rev. B, June 2002  
Package Dimensions  
TO-220  
4.50 ±0.20  
9.90 ±0.20  
(8.70)  
+0.10  
–0.05  
1.30  
ø3.60 ±0.10  
1.27 ±0.10  
1.52 ±0.10  
0.80 ±0.10  
+0.10  
–0.05  
0.50  
2.40 ±0.20  
2.54TYP  
2.54TYP  
[2.54 ±0.20]  
[2.54 ±0.20]  
10.00 ±0.20  
Dimensions in Millimeters  
©2002 Fairchild Semiconductor Corporation  
Rev. B, June 2002  
Package Dimensions (Continued)  
TO-220F  
2.54 ±0.20  
10.16 ±0.20  
ø3.18 ±0.10  
(7.00)  
(0.70)  
(1.00x45°)  
MAX1.47  
0.80 ±0.10  
#1  
0.35 ±0.10  
+0.10  
0.05  
0.50  
2.76 ±0.20  
2.54TYP  
2.54TYP  
[2.54 ±0.20]  
[2.54 ±0.20]  
9.40 ±0.20  
Dimensions in Millimeters  
©2002 Fairchild Semiconductor Corporation  
Rev. B, June 2002  
TRADEMARKS  
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not  
intended to be an exhaustive list of all such trademarks.  
OPTOLOGIC®  
OPTOPLANAR™  
PACMAN™  
UltraFET®  
VCX™  
ACEx™  
FASTr™  
FRFET™  
GlobalOptoisolator™  
GTO™  
HiSeC™  
I2C™  
ISOPLANAR™  
LittleFET™  
MicroFET™  
MicroPak™  
MICROWIRE™  
SMART START™  
SPM™  
STAR*POWER™  
Stealth™  
SuperSOT™-3  
SuperSOT™-6  
SuperSOT™-8  
SyncFET™  
Bottomless™  
CoolFET™  
CROSSVOLT™  
DOME™  
EcoSPARK™  
E2CMOS™  
EnSigna™  
FACT™  
POP™  
Power247™  
PowerTrench®  
QFET™  
QS™  
QT Optoelectronics™  
Quiet Series™  
SLIENT SWITCHER®  
TinyLogic™  
TruTranslation™  
UHC™  
FACT Quiet series™  
FAST®  
STAR*POWER is used under license  
DISCLAIMER  
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY  
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY  
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;  
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.  
LIFE SUPPORT POLICY  
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT  
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR  
CORPORATION.  
As used herein:  
1. Life support devices or systems are devices or systems  
which, (a) are intended for surgical implant into the body,  
or (b) support or sustain life, or (c) whose failure to perform  
when properly used in accordance with instructions for use  
provided in the labeling, can be reasonably expected to  
result in significant injury to the user.  
2. A critical component is any component of a life support  
device or system whose failure to perform can be  
reasonably expected to cause the failure of the life support  
device or system, or to affect its safety or effectiveness.  
PRODUCT STATUS DEFINITIONS  
Definition of Terms  
Datasheet Identification  
Product Status  
Definition  
Advance Information  
Formative or In  
Design  
This datasheet contains the design specifications for  
product development. Specifications may change in  
any manner without notice.  
Preliminary  
First Production  
This datasheet contains preliminary data, and  
supplementary data will be published at a later date.  
Fairchild Semiconductor reserves the right to make  
changes at any time without notice in order to improve  
design.  
No Identification Needed  
Obsolete  
Full Production  
This datasheet contains final specifications. Fairchild  
Semiconductor reserves the right to make changes at  
any time without notice in order to improve design.  
Not In Production  
This datasheet contains specifications on a product  
that has been discontinued by Fairchild semiconductor.  
The datasheet is printed for reference information only.  
©2002 Fairchild Semiconductor Corporation  
Rev. H6  
TRADEMARKS  
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is  
not intended to be an exhaustive list of all such trademarks.  
OPTOLOGICâ  
OPTOPLANAR™  
PACMAN™  
SMART START™ VCX™  
SPM™  
Stealth™  
SuperSOT™-3  
SuperSOT™-6  
SuperSOT™-8  
SyncFET™  
FASTr™  
FRFET™  
GlobalOptoisolator™  
GTO™  
ACEx™  
Bottomless™  
CoolFET™  
CROSSVOLT™  
DOME™  
EcoSPARK™  
E2CMOSTM  
EnSignaTM  
FACT™  
FACT Quiet Series™  
FAST â  
POP™  
HiSeC™  
Power247™  
PowerTrench â  
QFET™  
I2C™  
ISOPLANAR™  
LittleFET™  
MicroFET™  
MicroPak™  
MICROWIRE™  
TinyLogic™  
QS™  
TruTranslation™  
UHC™  
QT Optoelectronics™  
Quiet Series™  
SILENTSWITCHERâ  
UltraFET â  
DISCLAIMER  
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER  
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD  
DOES NOT ASSUME ANY LIABILITYARISING OUT OF THE APPLICATION OR USE OFANY PRODUCT  
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT  
RIGHTS, NOR THE RIGHTS OF OTHERS.  
LIFE SUPPORT POLICY  
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT  
DEVICESORSYSTEMSWITHOUTTHEEXPRESSWRITTENAPPROVALOFFAIRCHILDSEMICONDUCTORCORPORATION.  
As used herein:  
1. Life support devices or systems are devices or  
systems which, (a) are intended for surgical implant into  
the body, or (b) support or sustain life, or (c) whose  
failure to perform when properly used in accordance  
with instructions for use provided in the labeling, can be  
reasonably expected to result in significant injury to the  
user.  
2. A critical component is any component of a life  
support device or system whose failure to perform can  
be reasonably expected to cause the failure of the life  
support device or system, or to affect its safety or  
effectiveness.  
PRODUCT STATUS DEFINITIONS  
Definition of Terms  
Datasheet Identification  
Product Status  
Definition  
Advance Information  
Formative or  
In Design  
This datasheet contains the design specifications for  
product development. Specifications may change in  
any manner without notice.  
Preliminary  
First Production  
This datasheet contains preliminary data, and  
supplementary data will be published at a later date.  
Fairchild Semiconductor reserves the right to make  
changes at any time without notice in order to improve  
design.  
No Identification Needed  
Obsolete  
Full Production  
This datasheet contains final specifications. Fairchild  
Semiconductor reserves the right to make changes at  
any time without notice in order to improve design.  
Not In Production  
This datasheet contains specifications on a product  
that has been discontinued by Fairchild semiconductor.  
The datasheet is printed for reference information only.  
Rev. H7  

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