SSTV16857MTD [FAIRCHILD]
14-Bit Register with SSTL-2 Compatible I/O and Reset; 14位寄存器与SSTL - 2兼容的I / O和复位
| 型号： | SSTV16857MTD |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 14-Bit Register with SSTL-2 Compatible I/O and Reset |
| 文件： | 总7页 (文件大小：87K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 2000
Revised June 2005
SSTV16857 • SSTVN16857
14-Bit Register with SSTL-2 Compatible I/O and Reset
General Description
The SSTV16857 is a 14-bit register designed for use with
Features
■ Compliant with DDR-I registered module specifications
184 and 232 pin PC1600, 2100, and 2700 DDR DIMM
■ Operates at 2.5V 0.2V VDD
applications. The SSTVN16857 is
a 14-bit register
■ SSTL-2 compatible input and output structure
■ Differential SSTL-2 compatible clock inputs
■ Low power mode when device is reset
■ Industry standard 48 pin TSSOP package
designed for use with 184 and 232 pin PC3200 DDR DIMM
applications. These devices have a differential input clock,
SSTL-2 compatible data inputs and a LVCMOS compatible
RESET input. These devices have been designed for com-
pliance with the JEDEC DDR module and register specifi-
cations.
The devices are fabricated on an advanced submicron
CMOS process and are designed to operate at power sup-
plies of less than 3.6V’s.
Ordering Code:
Order Number Package Number
Package Description
SSTV16857MTD
MTD48
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
SSTVN16857MTD
(Preliminary)
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Name Description
Q1-Q14
D1-D14
SSTL-2 Compatible Output
SSTL-2 Compatible Inputs
RESET
CK
Asynchronous LVCMOS Reset Input
Positive Master Clock Input
CK
Negative Master Clock Input
VREF
VDDQ
VDD
Voltage Reference Pin for SSTL Level Inputs
Power Supply Voltage for Output Signals
Power Supply Voltage for Inputs
Truth Table
Dn
Qn
RESET
CK
CK
L
X or
X or
X or
L
Floating
Floating
Floating
H
H
H
H
L
H
X
X
L
H
L
H
L
Qn
Qn
H
L
H
X
Logic LOW
Logic HIGH
Don’t Care, but not floating unless noted
LOW-to-HIGH Clock Transition
HIGH-to-LOW Clock Transition
© 2005 Fairchild Semiconductor Corporation
DS500387
www.fairchildsemi.com
Functional Description
The SSTV16857 and SSTVN16587 are 14-bit registers
with SSTL-2 compatible inputs and outputs. Input data is
captured by the register on the positive edge crossing of
the differential clock pair.
RESET is removed, the system designer must insure the
clock and data inputs to the device are stable during the
rising transition of the RESET signal.
The SSTL-2 data inputs transition based on the value of
When the LV-CMOS RESET signal is asserted LOW, all
outputs and internal registers are asynchronously placed
into the LOW logic state. In addition, the clock and data dif-
ferential comparators are disabled for power savings. Out-
put glitches are prevented by disabling the internal
registers more quickly than the input comparators. When
VREF. VREF is a stable system reference used for setting
the trip point of the input buffers of the SSTV16857/
SSTVN16857 and other SSTL-2 compatible devices.
The RESET signal is a standard CMOS compatible input
and is not referenced to the VREF signal.
Logic Diagram
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions (Note 3)
Supply Voltage (VDDQ
Supply Voltage (VDD
)
0.5V to 3.6V
0.5V to 3.6V
)
Power Supply (VDDQ
SSTV16857
)
Reference Voltage (VREF
)
0.5V to 3.6V
2.3V to 2.7V
2.5V to 2.7V
Input Voltage (VI)
0.5V to VDD 0.5V
SSTVN16857
Output Voltage (VO)
Power Supply (VDD
)
Outputs Active (Note 2)
DC Input Diode Current (IIK
VI 0V
0.5V to VDDQ 0.5V
Operating Range
V
DDQ to 2.7V
)
Reference Supply (VREF VDDQ/2)
SSTV16857
50 mA
50 mA
1.15 to 1.35
1.25 to 1.35
VREF 40 mV
0V to VDD
VI VDD
SSTVN16857
DC Output Diode Current (IOK
VO 0V
)
Termination Voltage (VTT
Input Voltage
)
50 mA
50 mA
VO VDD
Output Voltage (VO)
DC Output Source/Sink Current
(IOH/IOL
Output in Active States
Output Current IOH/IOL
VDD 2.3V to 2.7V
0V to VDDQ
)
50 mA
DC VDD or Ground Current
SSTV16857
20 mA
20 mA
per Supply Pin (IDD or Ground)
Storage Temperature Range (Tstg
100 mA
VDD 2.5V to 2.7V
SSTVN16857
)
65 C to 150 C
Free Air Operating Temperature (TA)
0 C to 70 C
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the “Electrical
Characteristics” table are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Note 2: IO Absolute Maximum Rating must be observed.
Note 3: The RESET input of the device must be held at V
or GND to
DD
ensure proper device operation. The differential inputs must not be floating,
unless RESET is asserted LOW.
DC Electrical Characteristics (SSTV16857) (2.3V VDD 2.7V)
V
DD
Symbol
Parameter
Conditions
Min
Max
Units
(V)
2.3
2.3
V
V
V
V
V
V
Input LOW Clamp Voltage
Input HIGH Clamp Voltage
AC HIGH Level Input Voltage
AC LOW Level Input Voltage
DC HIGH Level Input Voltage
DC LOW Level Input Voltage
I
18 mA
18 mA
1.2
3.5
V
V
V
V
V
V
IKL
I
I
IKH
I
Data Inputs
Data Inputs
Data Inputs
Data Inputs
V
V
310mV
IH-AC
IL-AC
IH-DC
IL-DC
REF
V
V
310mV
REF
REF
150mV
REF
150mV
V
V
V
HIGH Level Input Voltage
LOW Level Input Voltage
RESET
RESET
1.7
V
V
IH
0.7
IL
Common Mode Input Voltage Range CLK, CLK
0.97
360
1.53
V
ICR
V
V
Peak to Peak Input Voltage
HIGH Level Output Voltage
CLK, CLK
100
16 mA
100
16 mA
or GND
mV
I(PP)
I
A
2.3 to 2.7
2.3
V
0.2
1.95
OH
OH
DD
V
V
I
OH
V
LOW Level Output Voltage
I
A
2.3 to 2.7
2.3
0.2
0.35
5.0
OL
OL
I
OL
I
I
Input Leakage Current
Static Standby
V
V
DD
2.7
A
A
I
I
RESET GND, I
0
10
25
DD
O
2.7
Static Operating
RESET
V
, I
0
DD
O
mA
V
V
or V
IH(AC) IL(AC)
I
3
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DC Electrical Characteristics (SSTV16857) (Continued)
V
DD
Symbol
Parameter
Conditions
Min
Max
Units
(V)
I
Dynamic Operating Current
Clock Only
RESET
V
, I
O
0
DDD
DD
V
V
or V
90
A/MHz
I
IH(AC)
IL(AC)
CK, CK Duty Cycle 50%
Dynamic Operating Current
per Data Input
RESET
V
, I
0
DD
O
2.7
V
V
or V
I
IH(AC) IL(AC)
CK, CK Duty Cycle 50%
Data Input ½ Clock
Rate 50% Duty Cycle
15
A/MHz
R
R
R
Output HIGH On Resistance
Output LOW On Resistance
I
I
I
20 mA
20 mA
2.3 to 2.7
2.3 to 2.7
2.5
7
7
20
20
4
OH
OL
O
OH
OL
O
| R - R
|
20 mA, T
A
25 C
OH
OL
DC Electrical Characteristics (SSTVN16857) (2.5V VDD 2.7V)
V
DD
Symbol
Parameter
Conditions
Min
Max
Units
(V)
2.5
2.5
V
V
V
V
V
V
Input LOW Clamp Voltage
Input HIGH Clamp Voltage
AC HIGH Level Input Voltage
AC LOW Level Input Voltage
DC HIGH Level Input Voltage
DC LOW Level Input Voltage
I
I
18 mA
18 mA
1.2
3.5
V
V
V
V
V
V
IKL
I
IKH
I
Data Inputs
Data Inputs
Data Inputs
Data Inputs
V
V
310mV
IH-AC
IL-AC
IH-DC
IL-DC
REF
V
V
310mV
REF
REF
150mV
REF
150mV
V
V
V
HIGH Level Input Voltage
LOW Level Input Voltage
RESET
RESET
1.7
V
V
IH
0.7
IL
Common Mode Input Voltage Range CLK, CLK
0.97
360
1.53
V
ICR
V
V
Peak to Peak Input Voltage
HIGH Level Output Voltage
CLK, CLK
mV
I(PP)
I
I
I
I
100
16 mA
100
16 mA
or GND
A
2.5 to 2.7
2.5
V
0.2
OH
OH
OH
OL
OL
DD
V
V
1.95
V
LOW Level Output Voltage
A
2.5 to 2.7
2.5
0.2
0.35
5.0
OL
I
I
Input Leakage Current
Static Standby
V
V
DD
2.7
A
A
I
I
RESET GND, I
0
10
25
DD
O
2.7
2.7
Static Operating
RESET
V
, I
0
DD
O
mA
V
V
or V
I
IH(AC) IL(AC)
I
Dynamic Operating Current
Clock Only
RESET
V
, I
O
0
DDD
DD
V
V
or V
90
15
A/MHz
I
IH(AC)
IL(AC)
CK, CK Duty Cycle 50%
Dynamic Operating Current
per Data Input
RESET
V
, I
0
DD
O
V
V
or V
I
IH(AC) IL(AC)
CK, CK Duty Cycle 50%
Data Input ½ Clock
Rate 50% Duty Cycle
A/MHz
R
R
R
Output HIGH On Resistance
Output LOW On Resistance
I
I
I
20 mA
20 mA
2.5 to 2.7
2.5 to 2.7
2.5
7
7
20
20
4
OH
OL
O
OH
OL
O
| R - R
|
20 mA, T
A
25 C
OH
OL
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4
AC Electrical Characteristics (SSTV16857) (Note 4)
T
0 C to 70 C, C
30 pF, R
L
50
A
L
Symbol
Parameter
V
2.5V 0.2V; V
2.5V 0.2V
Max
Units
DD
DDQ
Min
f
Maximum Clock Frequency
200
MHz
ns
MAX
t
t
Pulse Duration, CK, CK HIGH or LOW (Figure 2)
Differential Inputs Activation Time,
2.5
22
W
ACT
ns
(Note 5)
data inputs must be LOW after RESET HIGH (Figure 3)
Differential Inputs De-activation Time,
t
INACT
(Note 5)
data and clock inputs must be held at valid levels
(not floating) after RESET LOW
22
ns
t
t
Setup Time, Fast Slew Rate (Note 6)(Note 7) (Figure 5)
Setup Time, Slow Slew Rate (Note 7)(Note 8) (Figure 5)
Hold Time, Fast Slew Rate (Note 6)(Note 8) (Figure 5)
Hold Time, Slow Slew Rate (Note 7)(Note 8) (Figure 5)
Reset Removal Time (Figure 7)
0.65
0.9
S
ns
ns
0.75
0.9
10
H
t
t
ns
ns
REM
, t
Propagation Delay CLK, CLK to Q (Figure 4)
1.1
2.8
PHL PLH
n
t
t
Propagation Delay RESET to Q (Figure 6)
n
5.0
ns
ps
PHL
Output to Output Skew
200
SK(Pn-Pn)
Note 4: Refer to Figure 1 through Figure 7.
Note 5: This parameter is not production tested.
Note 6: For data signal input slew rate 1 V/ns.
Note 7: For data signal input slew rate 0.5 V/ns and 1 V/ns.
Note 8: For CK, CK signals input slew rates are 1 V/ns.
AC Electrical Characteristics (SSTVN16857) (Note 9)
T
0 C to 70 C, C
30 pF, R
L
50
A
L
Symbol
Parameter
V
2.5V 0.2V; V
2.5V 0.2V
Max
Units
DD
DDQ
Min
f
Maximum Clock Frequency
220
MHz
ns
MAX
t
t
Pulse Duration, CK, CK HIGH or LOW (Figure 2)
Differential Inputs Activation Time,
2.5
22
W
ACT
ns
(Note 5)
data inputs must be LOW after RESET HIGH (Figure 3)
Differential Inputs De-activation Time,
t
INACT
(Note 5)
Data and Clock Inputs must be held at valid levels
(not floating) after RESET LOW
22
ns
t
t
Setup Time, Fast Slew Rate (Note 9)(Note 12) (Figure 5)
Setup Time, Slow Slew Rate (Note 12)(Note 13) (Figure 5)
Hold Time, Fast Slew Rate (Note 11)(Note 13) (Figure 5)
Hold Time, Slow Slew Rate (Note 12)(Note 13) (Figure 5)
Reset Removal Time (Figure 7)
0.65
0.75
0.75
0.9
S
ns
ns
H
t
t
t
10
ns
ns
ns
REM
, t
Propagation Delay CLK, CLK to Q (Figure 4)
1.1
2.4
2.7
PHL PLH
PSS
n
Propagation Delay Simultaneous Switching CLK, CLK to Q (Note 14)
n
t
t
Propagation Delay RESET to Q (Figure 6)
n
5.0
ns
ps
PHL
Output to Output Skew
200
SK(Pn-Pn)
Note 9: Refer to Figure 1 through Figure 7.
Note 10: This parameter is not production tested.
Note 11: For data signal input slew rate 1 V/ns.
Note 12: For data signal input slew rate 0.5 V/ns and 1 V/ns.
Note 13: For CK, CK signals input slew rates are 1 V/ns.
Note 14: Simultaneous Switching is guaranteed by characterization.
5
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Capacitance (Note 15)
Symbol
Parameter
Min
Typ
Max
Units
Conditions
350 mV
1.25V, V 360 mV
C
Data Pin Input Capacitance
2.0
3.0
pF
V
V
V
2.5V, V
2.5V, V
2.5V, V
V
REF
IN
DD
DD
DD
I
CK, CK - Input Capacitance
RESET
2.5
2.5
3.5
3.5
pF
pF
ICR
I(PP)
V
to GND
DD
I
Note 15: T
25 C, f 1 MHz, Capacitance is characterized but not tested.
A
AC Loading and Waveforms (See Notes A through F below)
Note: C includes probe and jog capacitance
L
FIGURE 2. Voltage Waveforms - Pulse Duration
FIGURE 1. AC Test Circuit
Note: I tested with clock and data inputs held at V or GND,
DD
DD
and I
0 mA.
O
FIGURE 3. Voltage and Current Waveforms Inputs
Active and Inactive Times
FIGURE 4. Voltage Waveforms -
Propagation Delay Times
FIGURE 6. Voltage Waveforms -
RESET Propagation Delay Times
FIGURE 5. Voltage Waveforms - Setup and Hold Times
Note A: All input pulses are supplied by generators having
the following characteristics:
PRR 10 MHz, Z0 50 , input slew rate 1V/ns 20%
(unless otherwise specified).
Note B: The outputs are measured one at a time with one
transition per measurement.
Note C: VTT VREF VDD/2.
Note D: VIH VREF 310 mV (AC voltage levels) for differ-
ential inputs. VIH VDD for LVCMOS input.
Note E: VIL VREF 310 mV (AC voltage levels) for differ-
ential inputs. VIL GND for LVCMOS input.
Note F: Removal time (tREM) is tested with one data input
FIGURE 7. Voltage Waveforms -
RESET Removal Delay Times
held active HIGH. The propagation time from CK to the cor-
responding output must meet valid timing specifications for
the measurement to be accurate.
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6
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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7
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