FT2725 [FANGTEK]
2X11W Stereo Class-D Audio Power Amplifier with ALC & DRC;
| 型号： | FT2725 |
| 厂家： | 
Fangtek Ltd. |
| 描述： | 2X11W Stereo Class-D Audio Power Amplifier with ALC & DRC |
| 文件： | 总26页 (文件大小：1459K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ft2725
2X11W Stereo Class-D Audio Power Amplifier
with ALC & DRC
GENERAL DESCRIPTION
FEATURES
Wide supply voltage range from 3.7V to 9V
Automatic level control with adjustable threshold
High efficiency up to 89%
The ft2725 is a highly efficient 2X11W stereo Class-D
audio power amplifier with automatic level control (ALC)
and dynamic range compression (DRC). It operates
with a wide range of supply voltages from 3.7V to 9V.
When powered with 9V supply voltage, the ft2725 is
capable of delivering 11W per channel into a pair of 4Ω
speakers in a bridge-tied-load (BTL) configuration, or
15W into a single 3Ω speaker in parallel BTL (PBTL)
configuration, with 10% THD+N.
Maximum output power in Non-ALC mode
(VDD=9V, VALC>0.8*GVDD, 10% THD+N)
6W/Ch (8Ω load)
11W/Ch (4Ω load)
15W (3Ω load in PBTL configuration)
ALC output power in ALC Mode
(VDD=9V, VALC=0V, 0.3% THD+N)
The ft2725 features ALC with an adjustable threshold
for dynamic range control (DRC). The ALC constantly
monitors and safeguards the audio outputs against a
user-defined threshold voltage, preventing output
clipping distortion, excessive power dissipation, or
hazardous speaker over-load. Once an over-level
condition is detected, the ALC lowers the voltage gain
of the audio amplifiers proportionally to eliminate output
4.5W/Ch (8Ω load)
8.5W/Ch (4Ω load)
11.5W (3Ω load in PBTL configuration)
Low THD+N: 0.06%
(VDD=9V, f=1kHz, 4Ω load, Po=5W)
High PSRR: 76dB @ 1kHz
Wide ALC dynamic range: 10dB
Maximum voltage gain: 32.4dB
Volume fade-in and fade-out
clipping while maintaining
a
maximally-allowed
dynamic range of the audio outputs. The threshold
voltage of the ALC can be set at either the supply
voltage or an externally defined value.
Optional spread-spectrum (SS) audio outputs to
suppress EMI
Optional mono mode for PBTL configuration with
low-impedance audio speakers
As a filterless Class-D audio amplifier, the ft2725
features high efficiency (up to 89%), high PSRR (76dB
at 1kHz), and low EMI emissions, which reduce design
and manufacturing complexities, lower system cost and
PCB space.
Auto-recovering over-current & short-circuit
protection
Available in TSSOP-24L package
In ft2725, comprehensive protection features against
various operating faults ensure its safe and reliable
operation.
APPLICATIONS
Blue Tooth Speakers
Performance Audio Speakers
TV/Monitors
APPLICATION CIRCUIT
VDD
RAVDD 10Ω
CVDD
10uF
CVDD
220uF
+
CBYP
1uF
1
24
23
22
21
20
19
18
17
16
15
14
13
AGND
BYP
CINL1 0.33uF
CINR1
0.33uF
RINL1
RINL2 10K
10K
RINR1 10K
2
3
INNL
INPL
INNR
INNL
INPL
INNR
INPR
10K
RINR2
CINL2
0.33uF
CINR2
0.33uF
INPR
CGVDD
2.2uF
4
CAVDD
1uF
GVDD
ALC
AVDD
ATT
5
ALC
ATT
VDD
VDD
6
PVDDL
VOPL
PGNDL
VONL
PVDDL
SS
PVDDR
VOPR
PGNDR
VONR
PVDDR
PBTL
CPVDDL
1uF
7
CPVDDR
1uF
4.7Ω 10nF
4.7Ω
10nF
8
LSL
LSR
9
SPEAKER
SS
EN
10
11
12
SPEAKER
PBTL
MUTE
EN
MUTE
ft2725
Figure 1: Typical Audio Power Amplifier Application Circuit
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ft2725
PIN CONFIGURATION AND DESCRIPTION
AGND
INNL
INPL
GVDD
ALC
24 BYP
23
1
2
INNR
22 INPR
21 AVDD
20 ATT
3
4
5
19
18
17
6
PVDDR
VOPR
PVDDL
VOPL
7
8
PGNDR
PGNDL
VONL
16 VONR
15 PVDDR
9
10
11
12
PVDDL
14
PBTL
SS
EN
13
MUTE
ft2725P (TOP VIEW)
TYPE DESCRIPTION
NAME
AGND
INNL
PIN #
1
2
3
4
5
G
AI
Analog ground. Connect to the system ground GND.
Left-channel inverting audio input terminal.
INPL
AI
Left-channel non-inverting audio input terminal.
GVDD
ALC
AO
AI
Internally generated voltage supply. Connect to a 2.2µF capacitor for decoupling.
ALC and Dynamic Range Control. Connect to a 0.1µF capacitor for decoupling.
Power supply for the left-channel power amplifier’s output stage. Connect directly to
the system power supply VDD and add a 1µF capacitor for decoupling.
PVDDL
VOPL
6, 10
P
AO
G
7
8
Left-channel non-inverting audio output terminal.
Power ground for the output stage of the left-channel power amplifier. Connect to the
system ground GND.
PGNDL
VONL
SS
9
AO
DI
DI
DI
DI
Left-channel inverting audio output terminal.
11
12
13
14
Spread-Spectrum Select (Active High) with a 300kΩ internal pulldown resister.
Chip Enable (Active High) with a 300kΩ internal pulldown resister to ground.
Mute Control (Active High) with a 300kΩ internal pulldown resistor to ground.
PBTL Select (Active High) with a 300kΩ internal pulldown resistor to ground.
EN
MUTE
PBTL
Power supply for the right-channel power amplifier’s output stage. Connect directly to
the system power supply VDD and add a 1µF capacitor for decoupling.
PVDDR
VONR
15, 19
16
P
AO
G
Right-channel inverting audio output terminal.
Power ground for the output stage of the right-channel power amplifier. Connect to
the system ground GND.
PGNDR
17
VOPR
ATT
18
20
AO
DI
Right-channel non-inverting audio output terminal.
ALC Attack Time Select with a 300kΩ internal pulldown resistor to ground.
Power supply for internal analog circuitry. Connect to the system power supply
through a small decoupling resistor (10Ω). Also, add a 1µF capacitor for decoupling.
AVDD
21
P
INPR
INNR
BYP
22
23
24
AI
AI
Right-channel non-inverting audio input terminal.
Right-channel inverting audio input terminal.
AO
Common-mode bias for audio inputs. Connect to a 1µF capacitor for decoupling.
ORDERING INFORMATION
PART NUMBER
TEMPERATURE RANGE
PACKAGE
ft2725P
-40°C to +85°C
TSSOP-24L
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ft2725
REVISION HISTORY
Initial Release 1.0 (Jan., 2015)
Changed from Initial 1.0 (January, 2015) to Revision 1.1 (January, 2017)
1. Deleted the package option of QFN5x5-28L.
2. Changed input capacitors (CINL1, CINL2, CINR1, and CINR2) from 1.0µF to 0.33µF in Typical Application Circuits.
3. Revised Table 4, Typical Voltage Gain Settings & Input Resistor Values for Various Input Levels.
4. Added snubber circuits across audio outputs VOPL/R and VONL/R in Figure 1, 33, 34, 35, and 36.
Changed from Revision 1.1 (June, 2017) to Revision 1.2 (November, 2017)
1. Changed CPVDDL/R from 10µF to 1µF.
2. Added CVDD of 10µF//220µF onto the system power supply.
3. Updated Figure 1, Typical Application Circuit, on Page 1.
4. Updated Figure 33 and 34 on Page 24; Figure 35 and 36 on Page 25.
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ft2725
ABSOLUTE MAXIMUM RATINGS (Note 1)
PARAMETER
VALUE
Supply voltage, AVDD, PVDDL/R
All other Pins
-0.3V to 9.2V
-0.3V to VDD+0.3V
-65°C to +150°C
2000V
Storage Temperature
ESD Ratings-Human Body Model (HBM)
Junction Temperature
150°C
Maximum Soldering Temperature (@10 second duration)
260°C
Note 1: Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may damage the device or affect device reliability.
POWER DISSIPATION RATINGS (Note 2, 3)
PACKAGE
TA < +25°C
TA = +70°C
TA = +85°C
ΘJA
TSSOP-24L
3.1W
2.0W
1.7W
40°C/W
Note 2: The thermal pad of the package must be directly soldered onto a grounded metal island (as a thermal sink) on the system board.
Note 3: The power dissipation ratings are for a two-side, two-plane printed circuit board (PCB).
RECOMMENDED OPERATING CONDITIONS
Parameter
Conditions
MIN
3.7
TYP
MAX
9.0
UNIT
V
Supply Voltage，VDD (Note 4)
Operating Free-Air Temperature, TA
Minimum Load Resistance, RL
AVDD, PVDDL/R
-40
85
°C
3.0
Ω
Note 4: The peak supply voltage including its tolerance over various operating conditions must not exceed its absolute-maximum-rated
value (9.2v). Exposure to absolute-maximum-rated supply voltage may damage the device or affect device reliability permantly. For
applications where the system supply voltage might momentarily exceed the rating, it is strongly suggested to add an external Schottky
diode in series from the system power supply to ensure the peak suppy voltage not exceeding the absolute maximum rating.
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ft2725
IMPORTANT APPLICATION NOTES
1. For best noise performance, it is recommended to use differential inputs from the audio source for ft2725. In
a single-ended input application, the unused input of ft2725 should be AC-grounded at the audio source.
The impedance seen at the two differential inputs should be the same.
2. The ft2725 requires adequate power supply decoupling to ensure its optimum operation and performance in
output power, efficiency, distortion, and EMI emissions. Place respective decoupling capacitors individually
as close as possible to the device’s AVDD, GVDD, BYP, and PVDDL/R pins.
3. The ft2725 is a high performance, high power, stereo Class-D audio amplifier with an exposed thermal pad
on the underside of the device. The thermal pad should be directly soldered onto a ground plane, where
AGND and PGNDL/R pins are directly connected, as a thermal sink for proper power dissipation. Failure to
do so may result in the device prematurely going into thermal overload protection.
4. It is strongly recommended to employ power (PVDD) and ground (GND) planes for ft2725 on the system
board. Also, place a small decoupling resistor (10Ω) between AVDD and PVDD to prevent high frequency
Class-D transient spikes from interfering with the on-chip linear amplifiers.
5. Use a simple ferrite bead filter for further EMI suppression, as shown in Figure 31. Choose a ferrite bead
with a rated current no less than 3A or greater for applications with a load resistance less than 4Ω. Also,
place respective ferrite beard filters as individually close to VOPL/R and VONL/R pins as possible
6. To enhance long-term reliability, it is strongly recommended to add an RC snubber circuit, as shown in
Figure 32, between the two output pins of each individual channel, VOPL/R and VONL/R, to prevent the
device from accelerated deterioration or abrupt destruction due to excessive inductive flybacks that are
induced on fast output switching or by an over-current or short-circuit condition.
7. Do not short audio outputs (VOPL/R and VONL/R) directly to ground (AGND, PGNDL/R) or the supply
voltage (AVDD, PVDDL/R) as this might damage the device permanently, particularly when the supply
voltage is higher than 8.4V.
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ft2725
FUNCTIONAL BLOCK DIAGRAM
BYP
GVDD
AVDD
PBTL
PVDDL
VOPL
VONL
INPL
Class-D
Modulator
Input
Buffer
Output
Stage
INNL
PGNDL
OCP
OTP
Shutdown
EN
Control
ALC Control
Oscillator
Mute
Control
MUTE
UVLO
PGNDR
VOPR
INPR
INNR
Class-D
Modulator
Input
Buffer
Output
Stage
VONR
PVDDR
ALC
ATT
SS
AGND
PGND
Figure 2: Simplified Functional Block Diagram of ft2725
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ft2725
ELECTRICAL CHARACTERISTICS
VDD=9V, CIN=0.33µF, RIN=10kΩ, MUTE=Low, PBTL=Low, SS=Low, ATT=High, CBYP=1µF, CGVDD=2.2µF,
CAVDD=1µF, CPVDDL/R=1µF, f=1kHz, Load=4Ω+33µH, TA=25°C, unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
VDD
Supply Voltage
AVDD, PVDDL/R
VDD from Low to High
VDD from High to Low
VDD=9V
3.7
9.0
V
V
V
V
V
VUVLOUP
VUVLODN
GVDD
BYP
Power-Up Threshold Voltage
Power-Off Threshold Voltage
Regulator Output Voltage
Common-Mode Bias Voltage
3.2
2.9
6.2
3.1
5.8
2.8
6.6
3.4
VDD=9V
Supply Quiescent Current
Inputs AC-Grounded
MUTE=Low, No Load
Mute Current
Inputs AC-Grounded
Mute=High, No Load
VDD=9V, PBTL=Low
VDD=9V, PBTL=High
VDD=9V, PBTL=Low
VDD=9V, PBTL=High
13
18
23
mA
mA
mA
mA
IVDD
(Normal Mode)
4
6
8
IVDD_MUTE
(Mute Mode)
ISD
Shutdown Current
EN Low
10
µA
V
VIH
Digital High Level Input Voltage
Digital Low Level Input Voltage
Pulldown Resistor to Ground
EN, MUTE, SS, PBTL, ATT
EN, MUTE, SS, PBTL, ATT
EN, MUTE, SS, PBTL, ATT
1.2
VIL
0.4
V
RDOWN
300
kΩ
CLASS-D AMPLIFIER
THD+N=10%,
RL=4Ω
11
15
W/Ch
W
VALC>0.8*GVDD (Non-ALC Mode)
RL=3Ω in Mono Mode
RL=4Ω
PO, MAX
(VDD=9V)
9.0
12
W/Ch
W
THD+N=1%
VALC>0.8*GVDD (Non-ALC Mode)
RL=3Ω in Mono Mode
RL=4Ω
8.5
11.5
8.8
11.5
4.9
6.5
7.0
9.6
5.6
7.7
5.4
7.5
6.0
8.0
3.8
5.0
5.8
8.0
4.6
6.4
4.5
6.2
5.0
6.6
3.4
4.5
W/Ch
W
PO, ALC
VIN=0.36VRMS
(VDD=9V)
VALC<0.4V (ALC Mode)
RL=3Ω in Mono Mode
RL=4Ω
W/Ch
W
VIN=0.40VRMS
VALC=2.7V (DRC Mode)
PO, DRC
RL=3Ω in Mono Mode
RL=4Ω
(VDD=9V)
W/Ch
W
VIN=0.40VRMS
VALC=1.8V (DRC Mode)
RL=3Ω in Mono Mode
RL=4Ω
W/Ch
W
THD+N=10%,
VALC>0.8*GVDD (Non-ALC Mode)
RL=3Ω in Mono Mode
RL=4Ω
PO, MAX
(VDD=7.2V)
W/Ch
W
THD+N=1%
VALC>0.8*GVDD (Non-ALC Mode)
RL=3Ω in Mono Mode
RL=4Ω
W/Ch
W
PO, ALC
VIN=0.36VRMS
(VDD=7.2V)
VALC<0.4V (ALC Mode)
RL=3Ω in Mono Mode
RL=4Ω
W/Ch
W
VIN=0.40VRMS
VALC=2.16V (DRC Mode)
PO, DRC
RL=3Ω in Mono Mode
RL=4Ω
(VDD=7.2V)
W/Ch
W
VIN=0.40VRMS
VALC=1.44V (DRC Mode)
RL=3Ω in Mono Mode
RL=4Ω
W/Ch
W
THD+N=10%,
VALC>0.8*GVDD (Non-ALC Mode)
RL=3Ω in Mono Mode
RL=4Ω
PO, MAX
(VDD=6.5V)
W/Ch
W
THD+N=1%
VALC>0.8*GVDD (Non-ALC Mode)
RL=3Ω in Mono Mode
RL=4Ω
W/Ch
W
PO, ALC
VIN=0.36VRMS
(VDD=6.5V)
VALC<0.4V (ALC Mode)
RL=3Ω in Mono Mode
RL=4Ω
W/Ch
W
VIN=0.40VRMS
VALC=1.95V (DRC Mode)
PO, DRC
RL=3Ω in Mono Mode
RL=4Ω
(VDD=6.5V)
W/Ch
W
VIN=0.40VRMS
VALC=1.3V (DRC Mode)
RL=3Ω in Mono Mode
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ft2725
ELECTRICAL CHARACTERISTICS (Cont’d)
VDD=9V, CIN=0.33µF, RIN=10kΩ, MUTE=Low, PBTL=Low, SS=Low, ATT=High, CBYP=1µF, CGVDD=2.2µF,
CAVDD=1µF, CPVDDL/R=1µF, f=1kHz, Load=4Ω+33µH, TA=25°C, unless otherwise specified.
SYMBOL
CLASS-D AMPLIFIER (Cont’d)
Total Harmonic Distortion+Noise
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
RL=4Ω, Po=5W
0.06
%
VALC>0.8*GVDD (Non-ALC Mode)
Total Harmonic Distortion+Noise
VALC<0.4V (ALC Mode)
VIN=0.36VRMS
RL=4Ω, Po=8.5W
RL=3Ω, Po=11.5W
RL=4Ω, Po=8.8W
RL=3Ω, Po=11.5W
RL=4Ω, Po=4.9W
RL=3Ω, Po=6.5W
0.3
0.4
0.6
0.6
0.3
0.4
%
%
%
%
%
%
THD+N
Total Harmonic Distortion+Noise
VALC=2.7V (DRC Mode)
VIN=0.40VRMS
Total Harmonic Distortion+Noise
VALC=1.8V (DRC Mode)
VIN=0.40VRMS
AV
Overall Voltage Gain
Input Resistance
RIN=10kΩ
28
15
dB
kΩ
kΩ
mV
RIN
@ INNL/R, INPL/R
@ VOPL/R, VONL/R, EN=Low
No Load
ROUT-SD
VOS
Output Resistance in Shutdown
Output Offset Voltage
2.5
±10
AV=28dB, Inputs AC-Grounded
A-weighted
VN
Idle-Channel Noise
150
µVRMS
η
Power Efficiency
VDD=9V, Po=8W, RL=4Ω
f=1kHz
89
76
70
%
PSRR
CMRR
Power Supply Rejection Ratio
Common Mode Rejection Ratio
dB
dB
f=1kHz
Maximum Output (6VRMS) with
THD+N<1%, RL=4Ω, AV=20dB,
A-weighted
SNR
Signal-to-Noise Ratio
92
dB
Crosstalk
TSTUP
TSD
Channel Separation
Po=5W, f=1kHz
80
160
20
dB
ms
ms
kHz
A/Ch
A/Ch
A
Startup Time
Shutdown Mode Settling Time
PWM Output Carrier Frequency
fSW
360
3.2
2.7
4.2
3.6
40
VDD=9V, Stereo Mode
VDD=7.2V, Mono Mode
VDD=9V, Stereo Mode
VDD=7.2V, Mono Mode
ILIMIT
Over-Current Limit
A
TOCP
TOTP
THYS
Over-Current Recovery Time
Over-Temperature Threshold
Over-Temperature Hysteresis
ms
C
160
20
C
AUTOMATIC LEVEL CONTROL (ALC)
AMAX
Maximum ALC Attenuation
ALC Attack Time
10
2
dB
ms
ms
ms
V
ATT=Low
ATT=High
TATTACK
TRELEASE
50
500
ALC Release Time
ALC Mode
0.4
0.5*GVD
VALC
Operating Mode Threshold
DRC Mode
0.6
V
Non-ALC Mode
0.8*GVDD
V
FADE-IN & FADE-OUT
TFADEIN
Fade-In Time
20
10
ms
ms
TFADEOUT
Fade-Out Time
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ft2725
TYPICAL PERFORMANCE CHARACTERISTICS
VDD=9V, CIN=0.33µF, RIN=10kΩ, MUTE=Low, PBTL=Low, SS=Low, ATT=High, CBYP=1µF, CGVDD=2.2µF,
CAVDD=1µF, CPVDDL/R=1µF, f=1kHz, Load=4Ω+33µH, TA=25°C, unless otherwise specified.
DESCRIPTION
CONDITIONS
FIGURE #
RL=8Ω+33µH, Vin=0.3VRMS, ALC & Non-ALC Modes, PBTL=Low
RL=4Ω+33µH Vin=0.3VRMS, ALC & Non-ALC Modes, PBTL=Low
RL=3Ω+33µH, Vin=0.3VRMS, ALC & Non-ALC Modes, PBTL=High
3
4
5
Output Power vs. Supply Voltage
RL=4Ω+33µH, Vin=0.4VRMS, DRC Mode
VDD=8.8V & 7.2V & 6.5V
Output Power vs. VALC
6
7
8
RL=4Ω+33µH, DRC (VALC=2.7V)
Non-ALC, ALC, DRC Modes
Output Power vs. Input Voltage
RL=4Ω+33µH, DRC Mode
VALC=1.8V, 2.2V, 2.7V
Efficiency vs. Output Power
THD+N vs. Output Power
VDD=8.8V, RL=4Ω+33µH, Non-ALC Mode
RL=4Ω+33µH, Non-ALC Mode
9
10
11
RL=4Ω+33µH, ALC & Non-ALC Modes
THD+N vs. Input Voltage
RL=4Ω+33µH, DRC Mode
VALC=1.8V, 2.2V, 2.7V
12
THD+N vs. Input Frequency
PSRR vs. Frequency
RL=4Ω+33µH, ALC Mode, Po=5W
RL=4Ω+33µH, Inputs AC-Grounded
RL=4Ω+33µH, Vo=2.0VRMS, R-CH to L-CH
13
14
15
16
Crosstalk vs. Input Frequency
Quiescent Current vs. Supply Voltage Input AC-Grounded, No Load, ALC Mode
Vin=0.2VRMS ~ 0.63VRMS, RL=4Ω+33µH
ALC Attack & Release Time
17
18
VALC=0V (ALC Mode), ATT=Low
Vin=0.2VRMS ~ 0.63VRMS, RL=4Ω+33µH
ALC Attack & Release Time
VALC=2.7V (DRC Mode), ATT=Low
(VOP-VON) Startup Waveforms
(VOP-VON) Shutdown Waveforms
RL=4Ω+33µH, Vin=0.1VRMS, ALC Mode
RL=4Ω+33µH, Vin=0.1VRMS, ALC Mode
RL=4Ω+33µH, Vin=0.2VRMS, SS=Low
RL=4Ω+33µH, Vin=0.2VRMS, SS=High
19
20
21
22
Broadband Output Spectrum
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ft2725
TYPICAL PERFORMANCE CHARACTERISTICS (Cont’d)
Output Power vs. Supply Voltage
Output Power vs. Supply Voltage
7000
6000
5000
4000
3000
2000
1000
0
12000
11000
10000
9000
8000
7000
6000
5000
4000
3000
2000
1000
0
RL=8Ω+33uH, ALC On, Vin=0.3Vrms
RL=8Ω+33uH, Non-ALC, THD+N=1%
RL=8Ω+33uH, Non-ALC, THD+N=10%
RL=4Ω+33uH, ALC On, Vin=0.3Vrms
RL=4Ω+33uH, Non-ALC, THD+N=1%
RL=4Ω+33uH, Non-ALC, THD+N=10%
3
4
5
6
7
8
9
3
4
5
6
7
8
9
Supply Voltage (V)
Supply Voltage (V)
Figure 3: Output Power vs. Supply Voltage
Figure 4: Output Power vs. Supply Voltage
Output Power vs. Supply Voltage
18000
Output Voltage vs. Valc
8
7
6
5
4
16000
RL=3Ω+33uH, ALC On, Vin=0.3Vrms
14000
RL=3Ω+33uH, Non-ALC, THD+N=1%
RL=3Ω+33uH, Non-ALC, THD+N=10%
12000
10000
8000
6000
4000
2000
0
3
VDD=8.8V
2
VDD=7.2V
VDD=6.5V
1
0
3
4
5
6
7
8
9
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Valc (V)
Supply Voltage (V)
Figure 5: Output Power vs. Supply Voltage
Figure 6: Output Power vs. VALC (DRC Mode)
Output Power vs. Input Voltage (VDD=9V)
Output Power vs. Input Voltage (VDD=9V)
14000
14000
12000
10000
8000
6000
4000
2000
0
12000
10000
8000
6000
4000
2000
0
DRC Mode, VALC=1.8V
DRC Mode, VALC=2.2V
DRC Mode, VALC=2.7V
Non-ALC Mode
ALC Mode
DRC Mode, VALC=2.7V
0
200
400
600
800
1000
1200
1400
0
200
400
600
800
1000
1200
1400
Input Voltage (mVrms)
Input Voltage (mVrms)
Figure 7: Output Power vs. Input Voltage
Figure 8: Output Power vs. Input Voltage (DRC Mode)
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ft2725
TYPICAL PERFORMANCE CHARACTERISTICS (Cont’d)
Efficient vs. Output Power
THD+N vs. Output Power
100
90
80
70
60
50
40
30
20
10
0
100
10
1
L-CH only, Non-ALC
R-ch only, Non-ALC
VDD=8.8V, f=1kHz, Non-ALC
0
0
0
2000
4000
6000
8000
10000
12000
10
100
1000
10000
100000
Output Power / Channel (mW)
Output Power (mW)
Figure 9: Efficiency vs. Output Power
Figure 10: THD+N vs. Output Power
THD+N vs. Input Voltage
THD+N vs. Input Voltage (VDD=9V)
100
10
100
10
1
1
DRC Mode, VALC=1.8V
DRC Mode, VALC=2.2V
DRC Mode, VALC=2.7V
0.1
0.01
0.1
0.01
ALC On, VALC=0V
Non-ALC
0
200
400
600
800
1000
1200
1400
10
100
1000
10000
Input Voltage (mVrms)
Input Voltage (mVrms)
Figure 11: THD+N vs. Input Voltage
Figure 12: THD+N vs. Input Voltage (DRC Mode)
PSRR vs. Frequency
THD+N vs. Frequency
0
-10
-20
-30
10
1
L-CH, Po=5W
R-CH, Po=5W
PSRR, Input AC-Ground
-40
-50
-60
-70
-80
-90
0.1
0.01
10
100
1000
10000
100000
10
100
1000
10000
100000
Frequency (Hz)
Frequency (Hz)
Figure 13: THD+N vs. Frequency
Figure 14: PSRR vs. Frequency
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ft2725
TYPICAL PERFORMANCE CHARACTERISTICS (Cont’d)
Crosstalk vs. Frequency
Quiescent Current vs. Supply Voltage
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
18
16
14
12
10
8
L to R, Po(L-CH)=5W
R to L, Po(R-CH)=5W
6
Quiescent Current
4
2
0
3
4
5
6
7
8
9
10
100
1000
10000
100000
Supply Voltage (V)
Frequency (Hz)
Figure 15: Crosstalk vs. Frequency
Figure 16: Quiescent Current vs. Supply Voltage
VOP
X: 0.25s/div
VOP
X: 0.25s/div
Release Time (0.5s)
Release Time (0.5s)
Vin=0.2V ~ 0.63V
1kHz
Vin=0.2V ~ 0.63V
VON
1kHz
RMS,
RMS,
VON
Attack Time (2ms)
Attack Time (2ms)
X: 2ms/div
Y: 5V/div
X: 2ms/div
Y: 5V/div
VOP-VON (33kHz Lowpass Filer)
VOP-VON (33kHz Lowpass Filer)
Figure 17: ALC Attack & Release Time (ALC Mode)
Figure 18: ALC Attack & Release Time (DRC Mode)
VOP
VON
EN
VOP
VON
EN
VOP-VON (33kHz Lowpass Filer)
VOP-VON (33kHz Lowpass Filer)
X: 20ms/div
Y: 2V/div
X: 5ms/div
Y: 2V/div
Figure 19: (VOP-VON) Startup Waveforms
Figure 20: (VOP-VON) Shutdown Waveforms
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ft2725
TYPICAL PERFORMANCE CHARACTERISTICS (Cont’d)
SS=Low
SS=High
X: 500kHz/div
Y: 20dB/div
X: 500kHz/div
Y: 20dB/div
Figure 21: Broadband Output Spectrum
Figure 22: Broadband Output Spectrum
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ft2725
APPLICATION INFORMATION
The ft2725 is a highly efficient 2X11W stereo Class-D audio power amplifier with automatic level control (ALC)
and dynamic range compression (DRC). It operates with a wide range of supply voltages from 3.7V to 9V.
When powered with 9V supply voltage, the ft2725 is capable of delivering 11W per channel into a pair of 4Ω
speakers in a bridge-tied-load (BTL) configuration, or 15W into a single 3Ω speaker in parallel BTL (PBTL)
configuration, with 10% THD+N.
The ft2725 features ALC with an adjustable threshold for dynamic range control (DRC). The ALC constantly
monitors and safeguards the audio outputs against a user-defined threshold voltage, preventing output clipping
distortion, excessive power dissipation, or hazardous speaker over-load. Once an over-level condition is
detected, the ALC lowers the voltage gain of the audio amplifiers proportionally to eliminate output clipping
while maintaining for a maximally-allowed dynamic range of the audio outputs. The threshold voltage of the ALC
can be set at either the supply voltage or an externally defined value.
In ft2725, three operating modes, i.e., ALC, DRC, and Non-ALC, are available that can be selected via the ALC
pin. The Non-ALC mode configures the device in a conventional Class-D operation, where the output power is
maximized without ALC operation. In ALC mode, the output limiting voltage is set at the supply voltage. In DRC
mode, the threshold voltage for dynamic range compression is adjustable and set at a user-defined value that is
linearly proportional to the voltage applied onto the ALC pin.
As a filterless Class-D audio amplifier, the ft2725 features high efficiency (up to 89%), high PSRR (76dB at
1kHz), and low EMI emissions, which reduce design and manufacturing complexities, lower system cost and
PCB space. These features make ft2725 an ideal audio solution for portable and plug-in consumer electronic
devices.
As specifically designed for portable applications, the ft2725 incorporates a shutdown mode to minimize the
power consumption by holding the EN pin to ground. It also includes comprehensive protection features against
various operating faults such as over-current, short-circuit, over-temperature, or under-voltage for a safe and
reliable operation.
AUTOMATIC LEVEL CONTROL (ALC)
The automatic level control is to maintain the audio output signals for a maximum voltage swing without
distortion when an excessive input that may cause output clipping is applied. With the ALC function, the ft2725
lowers the gain of the amplifier to an appropriate value such that the clipping at the outputs is substantially
eliminated. It also eliminates the clipping of the output signal due to the reduction of the power-supply voltage.
Output Signal when Supply Voltage is Sufficiently Large
Output Signal in ALC Off Mode
Output Signal in ALC On Mode
Attack Time
Release Time
Figure 23: Automatic Level Control Diagram
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ft2725
The attack time and release time of the ALC are shown in Table 1. The attack time is defined as the time
interval required for the gain to fall to its steady-state gain less 3dB approximately, assumed that a sufficiently
large input signal is applied. The release time is the time interval required for the amplifier to exit out of the
present mode of operation.
Attack Time (ms)
Release Time (ms)
ATT Logic Level
Low
2
500
500
High
50
Table 1: Attack Time & Release Time
OPERATING MODE CONTROL
As described in Table 2, depending upon the voltage applied onto the ALC pin, the ft2725 can be configured in
one of the three operating modes: ALC (automatic level control with a fixed threshold voltage at VDD), DRC
(automatic level control with an adjustable threshold voltage defined by the voltage at the ALC pin), and
Non-ALC. If the voltage at the ALC pin is set less than 0.4V, the ft2725 operates in ALC mode, where the
threshold voltage of ALC is set at the supply voltage, VDD. In this case, the output peak voltage is limited to a
value that is substantially close to the supply voltage VDD. If the voltage at the ALC pin is set in the range from
0.6V to 0.5*GVDD, the ft2725 operates in DRC mode, where audio compression will be performed for the audio
outputs exceeding the defined threshold voltage. In this case, the threshold voltage of DRC is linearly
proportional to the voltage at the ALC pin. If the voltage at the ALC pin is set higher than 0.8*GVDD, the ft2725
operates in Non-ALC mode, where the ft2725 operates as a conventional Class-D amplifier without ALC or
DRC function. In this case, the output voltage will clip when the output peak voltage reaches beyond VDD.
Voltage at ALC
VALC < 0.4V
Mode of Operation
ALC (with fixed threshold voltage at VDD)
DRC (with adjustable threshold voltage)
Non-ALC
0.6V < VALC < 0.5*GVDD
VALC > 0.8*GVDD
Table 2: Operating Mode Control
VOLTAGE GAIN SETTING
In ft2725, the voltage gain of the audio amplifier can be externally adjusted by inserting external input resistors,
RIN, in series with the input capacitors, as depicted in Figure 24 and 25. In both figures, it is required that CIN =
CINL1 = CINL2 = CINR1 = CINR2, RIN = RINL1 = RINL2 = RINR1 = RINR2.
CINL1
CINL2
RINL1
RINL2
CINL1
CINL2
RINL1
RINL2
INNL
INPL
INNL
INPL
INNL
INPL
INNL
RINR1
RINR2
RINR1
RINR2
CINR1
CINR2
CINR1
CINR2
INNR
INPR
INNR
INPR
INNR
INNR
INPR
Figure 24: Gain Setting (Differential Inputs)
Figure 25: Gain Setting (Single-Ended Input)
The value of RIN (in kΩ) for a given voltage gain can be calculated by Equation 1, where AV is the voltage gain of
the audio amplifier.
625
A V =
(1)
RIN +15
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ft2725
Table 3 shows suitable resistor values of RIN that can be used for various voltage gains.
RIN (kΩ)
10
28
16
26
20
25
24
24
30
23
36
22
39
21
47
20
56
19
62
18
AV (dB)
Table 3: External Input Resistor Values Required for Various Voltage Gains
The choice of the voltage gain will strongly influence the loudness and quality of audio sounds. In general, the
higher the voltage gain is, the louder the sound is perceived. However an excessive voltage gain may cause
audio outputs to be severely clipped for high-level (loud) audio sounds. On the other hand, an unusually low
gain may cause relatively low-level (quite) sounds soft or inaudible. Thus it is crucial to choose a proper voltage
gain for well balanced audio quality.
The voltage gain is chosen based upon various system-level considerations including the supply voltage, the
dynamic range of audio sources and speaker loads, and the desired sound effects. As a general guideline,
the voltage gain can be simply expressed in Equation 2. In the equation, VIN, MAX (in VRMS) is the maximum input
level from the audio source, PVDD (in volts) is the supply voltage, and α is the design parameter, which ranges
from 0.65 to 2.2. The higher α is, the higher the average output power (louder) is, with some degree of
compression for high-level audio sounds.
α × PVDD
(2)
AV =
V
IN,MAX
As an example, Table 4 shows the voltage gains for various input levels and PVDD settings with α at about 1.2.
In the table, RIN is the external input resistor in series with the input capacitor.
PVDD
(V)
VIN, MAX
(VRMS)
RIN
(kΩ)
AV
(V/V)
AV
(dB)
Po, ALC (W)
with 4Ω+33µH Load
0.3
0.5
0.7
1.0
0.3
0.5
0.7
0.3
0.5
0.7
10
20
36
62
16
33
47
20
36
56
25
18
12
8
28
25
22
18
26
22
20
25
22
19
9.0
7.2
8.5
5.2
20
13
10
18
12
9
6.5
4.2
Table 4: Typical
for Various Input Levels
Voltage Gain Settings & Input Resistor Values
GVDD SUPPLY
The GVDD is an internally generated supply voltage for internal circuitry. It can also be used as the supply
voltage for the resistor divider to set the voltage at the ALC pin. It is recommended to decouple GVDD with a
2.2µF ceramic capacitor to ground for stable operation. Note that the current drawn from GVDD by external
circuitry, including the resistor divider at the ALC pin, must be kept less than 0.5mA.
ADJUSTABLE DRC THRESHOLD VOLTAGE
In conventional Class-D audio amplifiers with ALC operation, the output peak voltage is limited with respect to
the supply voltage applied to the device. The ft2725 features a DRC mode whose threshold (knee) voltage can
be externally set via the ALC pin. The threshold voltage (VKNEE) is linearly proportional to the voltage at the ALC
pin, as described by Equation 3.
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ft2725
V
= 3× VALC
(3)
KNEE
In Equation 3, VALC is the voltage at the ALC pin and can be set by a resistor divider from GVDD (an internally
generated reference voltage) to ground, as shown in Figure 26. It is strongly recommended to add a 0.1µF
capacitor from the ALC pin to ground for a stable operation. For best accuracy, the parallel combination of the
resistor divider should be close to 100kΩ.
GVDD
R1
ALC
C1
R2
ft2725
Figure 26: Typical Circuit Setting VALC
Table 5 shows typical values of R1 and R2 that can be used to derive various VALC. In the table, the
corresponding DRC threshold voltage and the output power where DRC commences for each individual setting
are also shown.
R1 (kΩ)
200
R2 (kΩ)
82
R2/(R1+R2) GVDD (V)
VALC (V)
1.8
VKNEE (V) Po (W) @ 4Ω
0.29
0.32
0.36
0.40
0.43
6.2
6.2
6.2
6.2
6.2
5.4
6.0
6.6
7.5
8.1
3.6
4.5
5.4
7.0
8.2
170
82
2.0
180
100
100
100
2.2
150
2.5
130
2.7
Table 5: Typical Resistor Values of R1 & R2 (VDD=9V) for Various DRC Threshold Voltages
In DRC mode, the ALC lowers the voltage gain for high-level (loud) audio outputs that are above the threshold,
while maintaining a constant and relatively high voltage gain for low-level (quiet) audio outputs. In this manner,
relatively quite sounds become louder while louder sounds remain unclipped. The net effect of DRC is to keep
the audio volume fairly constant over a range from medium to high level sounds while allowing relatively quiet
sounds of the music much more audible. For most applications, it is recommended to set the voltage gain at its
highest value (AV=32.4dB), if possible, for the device operating in DRC mode.
For most applications, VALC can be set in the range from 0.3*GVDD (or 0.2*VDD) to 0.45*GVDD (or 0.3*VDD).
A lower VALC allows audio compression commencing at a lower audio output with a lower compression ratio. On
the contrary, a higher VALC makes audio compression commencing at a higher audio output with a higher
compression ratio. Note that the ALC mode (VALC < 0.4V) is one of the exceptional cases of DRC where the
DRC threshold is set at a value substantially close to the supply voltage with a fairly large compression ratio.
Figure 27 illustrates the transfer (gain) function of the output (in dBVrms) with respect to the input (in dBVrms)
for ft2725 operating with VDD=9V and AV=32.4dB in DRC mode for three different values of VALC. As shown in
the figure, the voltage gain is constant at 32.4dB for low-level audio output (less than the threshold) while the
voltage gain for high-level audio output (more than the threshold) is gradually lowered as the audio output
grows larger. In a sense, the audio output is compressed as the audio output is larger than the threshold.
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ft2725
Output Voltage vs. Input Voltage (VDD=9V)
18
16
14
12
10
8
DRC Mode, VALC=1.8V
DRC Mode, VALC=2.2V
DRC Mode, VALC=2.7V
-24
-20
-16
-12
-8
-4
0
Input Voltage (dBVrms)
Figure 27: Output Voltage vs. Input Voltage (in dBVrms)
MONO MODE
The ft2725 features an optional mono mode that allows the left and right channels to operate in parallel BTL
configuration, delivering up to 15W into a single 3Ω speaker. Apply a logic-high to PBTL pin to enable mono
mode. In mono mode, as shown in Figure 28, an audio input signal applied to the left channel is routed to the
H-bridge of both channels. The ft2725 operates in stereo mode by driving a logic-low to PBTL pin or leave the
pin unconnected. Driving PBTL low or leaving it unconnected while the audio outputs VOPL/R and VONL/R are
wired together in PBTL configuration can trigger the over-current or thermal overload protection or both. The
mono mode of ft2725 is configured by:
Connect PBTL to logic-high to set the device in mono mode.
Connect INPR and INNR pins (pin 22 and 23) directly to BYP.
Audio input signals are applied to INPL and INNL pins (pin 2 and 3).
Connect VOPL to VONL and VOPR to VONR using heavy PCB traces as close as possible to the
device.
Place the speaker between the left and right-channel outputs.
BYP
CIN
1UF
CBYP
1UF
RIN
RIN
10K
10K
INNL
INPL
INNR
INPR
IN
CIN
1UF
VOPR
VONR
LS
GVDD
PBTL
SPEAKER
VOPL
VONL
Cs
1UF
Figure 28: Application Circuit of Mono Mode in PBTL Configuration
VOLUME FADE-IN & FADE-OUT
The volume fade-in/out function operates when toggled EN or MUTE state. This function is used to reduce
intermittent sound considerably and eliminate uncomfortable feeling.
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ft2725
Fade In
Time
Fade Out
Time
Figure 29: Fade-In Waveform
Figure 30 Fade-Out Waveform
SHUTDOWN AND STARTUP
The ft2725 employs the EN pin to minimize power consumption while it is not in use. When the EN pin is pulled
to ground, the ft2725 is forced into shutdown mode, where all the analog circuitry is de-biased and the supply
current is thus reduced to less than 10µA, and the differential outputs are shorted to ground through an internal
resistor (2.5kΩ) individually. Once in shutdown mode, the EN pin must remains low for at least 20ms (TSD), the
shutdown settling time, before it can be brought high again. When the EN pin is asserted high, the device exits
out of the shutdown mode and enters into the normal mode of operation after the startup time (TSTUP) of 160ms.
Note that an internal pulldown resistor of 300kΩ is implemented onto the EN pin. Furthermore, the shutdown
mode is the state when the power supply is first applied to the device. Whenever possible, it is recommended to
assert EN high to exit the device out of the shutdown mode only after the device is properly started up. Also,
place the amplifiers in the shutdown mode prior to removing the power supply voltage for best power-off pop
performance.
MUTE CONTROL
In ft2725, the MUTE pin is used to control the operation of the output stages of both channels. When playing
music, the MUTE pin is pulled low and the output stages of audio amplifiers are enabled. When the MUTE pin is
asserted high, the output stages of audio amplifiers are de-biased while the differential audio outputs VOPL/R
and VONL/R are pulled to ground through on-chip resistors individually.
CLICK-AND-POP SUPPRESSION
The ft2725 features comprehensive click-and-pop suppression. During startup, the click-and-pop suppression
circuitry reduces any audible transients internal to the device. When entering into shutdown, the differential
audio outputs VOPL/R and VONL/R ramp down to ground quickly and simultaneously.
PSRR ENHANCEMENT
With a dedicated pin for the common-mode voltage bias and an external holding capacitor onto the pin, the
ft2725 achieves a PSRR, 76dB at 1kHz.
PROTECTION MODES
The ft2725 incorporates various protection functions against possible operating faults for a safe operation. It
includes Under-voltage Lockout (UVLO), Over-Current Protection (OCP), and Over-Temperature Shutdown
(OTSD).
Under-Voltage Lockout (UVLO)
The ft2725 incorporates a circuitry to detect a low supply voltage for a safe and reliable operation. When
the supply voltage is first applied, the ft2725 will remain inactive until the supply voltage exceeds 3.2V
(VUVLU). When the supply voltage is removed and drops below 2.9V (VUVLD), the ft2725 enters into shutdown
mode immediately.
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ft2725
Over-Temperature Shutdown (OTSD)
When the die temperature exceeds a preset threshold, the device enters into the over-temperature
shutdown mode, where the differential audio outputs VOPL/R and VONL/R are pulled to ground through
on-chip resistors individually. The device will resume normal operation once the die temperature returns to
a lower temperature, which is about 20C lower than the threshold.
Over-Current Protection (OCP)
During operation, the output of Class-D amplifier constantly monitors for any over-current and/or
short-circuit conditions. When a short-circuit condition between two differential outputs, differential output
to AVDD, PVDDL, PVDDR or ground is detected, the output stage of the amplifier is immediately forced
into high impedance state. Once the fault condition persists over a prescribed period, the ft2725 then
enters into the shutdown mode and remains in this mode for about 40ms (TOCP), the over-current recovery
time. When the shutdown mode times out, the ft2725 will initiate another start-up sequence and then check
if the short-circuit condition has been removed. If the fault condition is still present, the ft2725 will repeat
itself for the process of a startup followed by detection, qualification, and shutdown. It is so-called the
hiccup mode of operation. Once the fault condition is removed, the ft2725 automatically restores to its
normal mode of operation.
Although the output stages of the Class-D audio amplifiers can withstand a short between VOPL/R
and VONL/R pins, do not short audio output pins (VOPL/R and VONL/R) directly to ground pins
(AGND, PGNDL/R) or the supply voltage pins (AVDD, PVDDL/R) as this might damage the device
permanently, particularly when the supply voltage is higher than 8.4V.
LOW-EMI FILTERLESS OUTPUT STAGE
Traditional Class-D amplifiers require for the use of external LC filters, or shielding, to meet EN55022B
electromagnetic-interference (EMI) regulation standards. The ft2725 applies an edge-rate control circuitry to
reduce EMI emission, while maintaining high power efficiency. Above 10MHz, the wideband spectrum looks
like noise for EMI purposes.
EMI REDUCTION
The ft2725 does not require an LC output filter for short connections from the amplifier to the speakers.
However, additional EMI suppressions can be made by use of a ferrite bead in conjunction with a capacitor, as
shown in Figure 31. Choose a ferrite bead with low DC resistance (DCR) and high impedance (100Ω ~ 330Ω) at
high frequencies (>100MHz). The current flowing through the ferrite bead must be also taken into consideration.
The effectiveness of ferrites can be greatly aggravated at much lower than the rated current values. Choose a
ferrite bead with a rated current value no less than 4A. The capacitor value varies based on the ferrite bead
chosen and the actual speaker lead length. Choose a capacitor less than 1nF based on EMI performance.
Place the ferrite and capacitor as close to the output terminals (VOPL/R and VONL/R) as possible for the best
EMI performance. Also, the capacitors should be grounded to power ground (PGNDL/R).
Ferrite
Chip Bead
VOP
SPEAKER
1nF
Ferrite
Chip Bead
VON
1nF
Figure 31: Ferrite Bead Filter to Reduce EMI
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ft2725
RC SNUBBER CIRCUIT
For applications where the power supply is rated more than 7.2V or the load resistance less than 4Ω, it may
become necessary to add an RC snubber circuit between the two output pins of each individual channel,
VOPL/R and VONL/R, to prevent the device from accelerated deterioration or abrupt destruction due to
excessive inductive flybacks that are induced on fast output switching or by an over-current or short-circuit
condition. Note that the snubber circuit at the audio outputs also lowers the EMI emissions of the Class-D audio
amplifiers.
VOP
SPEAKER
R
4.7Ω
C
10nF
VON
Figure 32: RC Snubber Circuit of Class-D Amplifiers’ Outputs
SPREAD-SPECTRUM AUDIO OUTPUTs
The Class-D audio amplifiers in ft2725 can be operated at a fixed or jittered PWM frequency via the SS pin. By
asserting the SS pin high, the Class-D audio amplifiers operate in a jittered PWM frequency, which results in
further reduction of EMI emissions, with negligible penalty on THD+D, of the Class-D audio amplifiers. On the
other hand (the SS pin is left open or shorted to ground), the Class-D audio amplifiers operate at a fixed
frequency.
PWM Frequency
Fixed
SS Logic Level
Low
High
Jittered
Table 6: Spread-Spectrum Select
SUPPLY DECOUPLING CAPACITOR (CAVDD, CPVDDL, CPVDDR)
The ft2725 as a high-performance stereo audio power amplifier requires sufficient decoupling of the power
supply to ensure its high efficiency operation with low total harmonic distortion. Sufficient power supply coupling
also prevents oscillations for long lead lengths between the amplifier and the speakers. In light of power
efficiency and EMI, it is strongly recommended to use power and ground planes to reduce parasitic resistance
and inductance.
Place a low equivalent-series-resistance (ESR) ceramic capacitor (X7R or X5R), 1µF or greater, as close to
AVDD pin as possible. Also, a small decoupling resistor, typically 10Ω, can be placed between AVDD and the
system power supply to keep high frequency transient spikes from entering the on-chip linear amplifiers.
For best audio quality and reliability, place a 1µF low-ESR ceramic capacitor (CPVDDL/R) individually close to
PVDDL/R pins. In tandem with each 1µF capacitor, add a small, good quality, low-ESR ceramic capacitor of
0.047µF, within 2mm of the PVDDL/R pins, for high-frequency filtering and EMI reduction.
INPUT CAPACITOR (CINL1, CINL2, CINR1, CINR2)
The input DC decoupling capacitors are recommended to bias the incoming audio inputs to a proper DC level.
The input capacitor CIN, in conjunction with the amplifier input resistance (including both internal 15kΩ and
external resistor RIN, if any) forms a highpass filter that removes the DC bias of the audio inputs. The corner
frequency, fC, of the highpass filter is given by Equation 4.
fC = 1 / [2 x π x (RIN +15kΩ) x CIN]
(4)
where CIN = CINL1, CINL2, CINR1, or CINR2
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ft2725
RIN is the external input resistance for a specific voltage gain. Note that the variation of the actual input
resistance will affect the voltage gain proportionally. Thus choose input resistors with a tolerance of 5% or
better.
Choose CIN such that fC is well below the lowest frequency of interest. Setting it too high affects the amplifiers’
low-frequency response. Consider an example where the specification calls for AV=28dB and a flat frequency
response down to 20Hz. In this example, RIN=10kΩ and CIN is calculated to be about 0.32µF; thus 0.33µF, as a
common choice of capacitance, can be chosen for CIN.
Note that any mismatch in capacitance between two audio inputs will cause a mismatch in the corner
frequencies. Severe mismatch may also cause turn-on pop noise, PSRR, CMRR performance. Choose input
capacitors with a tolerance of ±5% or better.
Furthermore, the type of the input capacitor is crucial to audio quality. For best audio quality, use capacitors
whose dielectrics have low-voltage coefficients, such as tantalum or aluminum electrolytic. Capacitors with
high-voltage coefficients, such as ceramics, may result in increased distortion at low frequencies. Other factors,
including the constraints of the overall system such as the physical size of the speakers, are to be considered
when designing the input filter.
PRINTED CIRCUIT BOARD (PCB) LAYOUT
Decoupling capacitors - CAVDD should be placed as close as possible to AVDD pin. CPVDDL/R should be placed
as individually close as possible to PVDDL/R pins. Large (100µF or greater) bulk power supply decoupling
capacitors should be placed close to ft2725.
Grounding - The AVDD decoupling capacitor should be grounded to analog ground AGND. The PVDD
decoupling capacitors should be grounded to power ground PGND. Analog ground and power ground should
be connected to a central ground in a star manner or a ground plan.
EMI - The ferrite EMI filter as shown in Figure 31 should be placed as close to the output terminals as possible
for the best EMI performance. Keep the current loop from each of the outputs through the ferrite bead and the
small filter cap and back to PGND as small and tight as possible. The size of this current loop determines its
effectiveness as an antenna.
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ft2725
TYPICAL APPLICATION CIRCUITS
VDD
RAVDD 10Ω
CVDD
10uF
CVDD
220uF
+
CBYP
1uF
1
24
23
22
21
20
19
18
17
16
15
14
13
AGND
BYP
INNR
CINL1 0.33uF
CINR1
0.33uF
RINL1
10K
RINR1 10K
2
3
INNL
INPL
INNR
INPR
INNL
INPL
10K
RINL2 10K
RINR2
CINL2
0.33uF
CINR2
0.33uF
INPR
CGVDD 2.2uF
4
CAVDD
1uF
GVDD
ALC
AVDD
ATT
5
VDD
VDD
6
PVDDL
VOPL
PGNDL
VONL
PVDDL
SS
PVDDR
VOPR
PGNDR
VONR
PVDDR
PBTL
CPVDDL
1uF
7
CPVDDR
1uF
4.7Ω 10nF
4.7Ω
10nF
8
LSL
LSR
9
SPEAKER
10
11
12
SPEAKER
EN
EN
MUTE
ft2725
Figure 33: Differential Inputs in ALC Mode with Fast ALC Attack
VDD
RAVDD 10Ω
CVDD
10uF
CVDD
220uF
+
CBYP
1
2
24
23
22
21
20
19
18
17
16
15
14
13
1uF
AGND
INNL
INPL
BYP
INNR
CINL1 0.33uF
CINR1
0.33uF
RINL1
RINL2 10K
10K
RINR1 10K
INL
INR
10K
RINR2
CINL2
0.33uF
3
CINR2
0.33uF
INPR
CGVDD
2.2uF
4
CAVDD
1uF
GVDD
ALC
AVDD
ATT
5
VDD
VDD
6
PVDDL
VOPL
PGNDL
VONL
PVDDL
SS
PVDDR
VOPR
PGNDR
VONR
PVDDR
PBTL
CPVDDL
1uF
7
CPVDDR
1uF
4.7Ω 10nF
4.7Ω
10nF
8
LSL
LSR
9
SPEAKER
10
11
12
SPEAKER
EN
MUTE
EN
MUTE
ft2725
Figure 34: Single-Ended Inputs in Non-ALC Mode
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ft2725
TYPICAL APPLICATION CIRCUITS (Cont’d)
VDD
RAVDD 10Ω
CVDD
10uF
CVDD
220uF
+
GVDD
1
CBYP
1uF
24
23
22
21
20
19
18
17
16
15
14
13
AGND
INNL
INPL
BYP
INNR
CINL1 0.33uF
CINR1
0.33uF
RINL1
10K
RINR1 10K
2
3
INNL
INPL
INNR
INPR
10K
RINL2 10K
CGVDD
RINR2
CINL2
0.33uF
CINR2
0.33uF
INPR
4
CAVDD
1uF
GVDD
ALC
AVDD
ATT
GVDD
2.2uF
5
VDD
VDD
6
PVDDL
VOPL
PGNDL
VONL
PVDDL
SS
PVDDR
VOPR
PGNDR
VONR
PVDDR
PBTL
CPVDDL
1uF
7
CPVDDR
1uF
4.7Ω 10nF
4.7Ω
10nF
8
LSL
LSR
9
SPEAKER
10
11
12
SPEAKER
MUTE
GVDD
EN
EN
MUTE
ft2725
Figure 35: Differential Inputs in ALC Mode with Slow ALC Attack & Spread–Spectrum Audio Outputs
VDD
RAVDD 10Ω
CVDD
10uF
CVDD
220uF
+
1
2
24
23
22
21
20
19
18
17
16
15
14
13
AGND
INNL
INPL
BYP
INNR
Audio Input
CIN1
0.33uF
10K
RIN1
CIN2
RIN2
10K
0.33uF
3
INPR
CGVDD
2.2uF
4
CAVDD 1uF
GVDD
ALC
AVDD
ATT
5
VDD
VDD
6
PVDDL
VOPL
PGNDL
VONL
PVDDL
SS
PVDDR
VOPR
PGNDR
VONR
PVDDR
PBTL
CPVDDL
1uF
7
CPVDDR
1uF
8
LSR
9
4.7Ω
10nF
10
11
12
4.7Ω
SPEAKER
EN
EN
MUTE
10nF
ft2725P
Figure 36: Single-Ended Input in Non-ALC Mode in PBTL Configuration
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ft2725
PHYSICAL DIMENSIONS
TSSOP-24L PACKAGE OUTLINE DIMENSIONS
Unit: mm
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ft2725
IMPORTANT NOTICE
1. Disclaimer: The information in document is intended to help you evaluate this product. Fangtek, LTD.
makes no warranty, either expressed or implied, as to the product information herein listed, and reserves
the right to change or discontinue work on this product without notice.
2. Life support policy: Fangtek’s products are not authorized for use as critical components in life support
devices or systems without the express written approval of the president and general counsel of Fangtek
Inc. As used herein
Life support devices or systems are devices or systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be reasonably expected to result in a significant
injury to the user.
A critical component is any component of a life support device or system whose failure to perform can be
reasonably expected to cause the failure of the life support device or system, or to affect its safety or
effectiveness.
3. Fangtek assumes no liability for incidental, consequential or special damages or injury that may result
from misapplications or improper use or operation of its products
4. Fangtek makes no warranty or representation that its products are subject to intellectual property
license from Fangtek or any third party, and Fangtek makes no warranty or representation of
non-infringement with respect to its products. Fangtek specifically excludes any liability to the customer or
any third party arising from or related to the products’ infringement of any third party’s intellectual property
rights, including patents, copyright, trademark or trade secret rights of any third party.
5. The information in this document is merely to indicate the characteristics and performance of Fangtek
products. Fangtek assumes no responsibility for any intellectual property claims or other problems that
may result from applications based on the document presented herein. Fangtek makes no warranty with
respect to its products, express or implied, including, but not limited to the warranties of merchantability,
fitness for a particular use and title.
6. Trademarks: The company and product names in this document may be the trademarks or registered
trademarks of their respective manufacturers. Fangtek is trademark of Fangtek, LTD.
CONTACT INFORMATION
Fangtek Electronics (Shanghai) Co., Ltd
Room 501A, No.10, Lane 198, Zhangheng Road
Zhangjiang Hi-tech Park, Pudong District
Shanghai, China, 201204
Tel: +86-21-61631978
Fax: +86-21-61631981
Website:
www.fangtek.com.cn
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26
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