FM8P73BAP [FEELING]
EPROM-Based 8-Bit Microcontroller with 10 bit ADC;
| 型号： | FM8P73BAP |
| 厂家： | 
Feeling Technology |
| 描述： | EPROM-Based 8-Bit Microcontroller with 10 bit ADC 可编程只读存储器 电动程控只读存储器 微控制器 |
| 文件： | 总57页 (文件大小：2693K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EELING
FM8P73B
EPROM-Based 8-Bit Microcontroller 10 bit ADC
Devices Included in this Data Sheet:
FM8P73BA : 16-pin EPROM device
FM8P73BB : 14-pin EPROM device
FM8P73BC : 18-pin EPROM device with VR pin
FM8P73BD : 16-pin EPROM device with VR pin
FEATURES
Total 11 channel 10bit AD converter with ±2LSB resolution
All instructions are single cycle except for program branches which are two-cycles
14-bit wide instructions
Configurable CPU clock per instruction cycle: Focs/4 and Fosc/2
All EPROM area GOTO instruction
All EPROM area subroutine CALL instruction
8-bit wide data path
6-level deep hardware stack
1K x 14 bits on chip EPROM
27x8 bits on chip special purpose registers and 64 x 8 bits on chip general purpose registers (SRAM)
Operating speed: DC-20 MHz clock input, or DC-100 ns instruction cycle
Direct, indirect addressing modes for data accessing
Three real time down-count Timer with 3-bit programmable prescaler
- TMR1: 8-bit, PWM1(Period) & Timer
- TMR2: 8-bit, PWM1(Duty) & Timer
- TMR3: 8-bit Timer
Built-in 3 levels Low Voltage Detector (LVDT) for Brown-out Reset (BOR)
Power-up Reset Timer (PWRT)
On chip Watchdog Timer (WDT) with internal oscillator for reliable operation.
Two I/O ports IOA, and IOB with independent direction control
- 13 Bi-direction I/O port (Programmable Pull-up enable in Input mode)
- One Input only port (IOB3/RSTB)
Four kinds of interrupt source: 3 Timers, 8 external interrupt sources: IOB0~IOB7, Internal watchdog timer
(i_WDT) wakeup, and A/D end of conversion
Wake-up from SLEEP:
- Port B (IOB0~IOB7) pin change wakeup
- WDT overflow
- i_WDT overflow
Power saving SLEEP mode
Programmable Code Protection
Selectable oscillator options:
- ERC: External Resistor/ Voltage Controlled Oscillator
- XT: Crystal/Resonator Oscillator
- HF: High Frequency Crystal/Resonator Oscillator
- LF: Low Frequency Crystal Oscillator
- IRC: Internal Resistor/Capacitor Oscillator
Wide-operating voltage range:
- EPROM : 2.2V to 5.5V
This datasheet contains n. Feeling Technology reserves the rights to modify the product specification without notice.
No liability is assumed as a rethis product. No rights under any patent accompany the sales of the product.
Web site: http://www.feeling-teccom.tw
Rev1.0 Nov 20, 2013
P.1/FM8P73B
EELING
FM8P73B
GENERAL DESCRIPTION
The FM8P73B is a low-cost, high speed, high noise immunity, EPROM-based 8-bit CMOS microcontrollers. It
employs a RISC architecture with 33 instructions. All instructions are single cycle except for program branches
which take two cycles. The easy to use and easy to remember instruction set reduces development time
significantly.
The FM8P73B consists of Power-on Reset (POR), Brown-out Reset (BOR), Power-up Reset Timer (PWRT),
Watchdog Timer, EPROM, SRAM, tri-state I/O port, I/O pull-high control, Power saving SLEEP mode, 3 real time
programmable clock/counter, Interrupt, Wake-up from SLEEP mode, and Code Protection for EPROM products.
There are five oscillator configurations to be chosen from, including the power-saving LF (Low Frequency)
oscillator and cost saving internal RC oscillator.
The FM8P73B address 1K×14 of program memory.
The FM8P73B can directly or indirectly address its register files and data memory. All special function registers
including the program counter are mapped in the data memory.
The FM8P73B provides total 11 channel 10bit AD converter with ±2LSB resolution.
BLOCK DIAGRAM
Oscillator
Circuit
6-level
STACK
Program
Counter
Watchdog
Timer
FSR
SRAM
Instruction
Decoder
EPROM
PORTA
ALU
Timer 1 ~ 3
Accumulator
PORTB
Interrupt
Control
A/D
Converter
PWM
Controller
Web site: http://www.feeling-teccom.tw
Rev1.0 Nov 20, 2013
P.2/FM8P73B
EELING
FM8P73B
PIN CONNECTION
PDIP16, SOP16
VDD
IOB5/INT5/OSCI
IOB4/INT4/OSCO
IOB3/INT3/RSTB
IOA0/ADC0/PWM1P
IOA1/ADC1/PWM1N
IOB6/ADC9/INT6
IOA4/ADC4
1
2
3
4
5
6
7
8
16 VSS
15 IOB0/INT0/ADC6
14 IOB1/INT1/ADC7/PWM1P_OPT
13 IOB2/INT2/ADC8/TMCKI
12 IOA3/ADC3
FM8P73BA
11 IOA2/ADC2
10 IOB7/ADC10/INT7
9
IOA5/ADC5
PDIP14, SOP14
VDD
IOB5/INT5/OSCI
1
2
3
4
5
6
7
14 VSS
13 IOB0/INT0/ADC6
12 IOB1/INT1/ADC7/PWM1P_OPT
11 IOB2/INT2/ADC8/TMCKI
10 IOA3/ADC3
IOB4/INT4/OSCO
IOB3/INT3/RSTB
IOA0/ADC0/PWM1P
IOA1/ADC1/PWM1N
IOB6/ADC9/INT6
FM8P73BB
9
8
IOA2/ADC2
IOB7/ADC10/INT7
PDIP18, SOP18 (With VR PIN)
VR
1
2
3
4
5
6
7
8
9
18 NC
VDD
17 VSS
IOB5/INT5/OSCI
IOB4/INT4/OSCO
IOB3/INT3/RSTB
IOA0/ADC0/PWM1P
IOA1/ADC1/PWM1N
IOB6/ADC9/INT6
IOA4/ADC4
16 IOB0/INT0/ADC6
15 IOB1/INT1/ADC7/PWM1P_OPT
14 IOB2/INT2/ADC8/TMCKI
13 IOA3/ADC3
FM8P73BC
12 IOA2/ADC2
11 IOB7/ADC10/INT7
10 IOA5/ADC5
PDIP16, SOP16 (With VR PIN)
VR
VDD
1
2
3
4
5
6
7
8
16 NC
15 VSS
IOB5/INT5/OSCI
IOB4/INT4/OSCO
IOB3/INT3/RSTB
IOA0/ADC0/PWM1P
IOA1/ADC1/PWM1N
IOB6/ADC9/INT6
14 IOB0/INT0/ADC6
13 IOB1/INT1/ADC7/PWM1P_OPT
12 IOB2/INT2/ADC8/TMCKI
11 IOA3/ADC3
FM8P73BD
10 IOA2/ADC2
9
IOB7/ADC10/INT7
Web site: http://www.feeling-teccom.tw
Rev1.0 Nov 20, 2013
P.3/FM8P73B
EELING
FM8P73B
PIN DESCRIPTIONS
Name
I/O
Description
Bi-direction I/O pin
Software controlled pull-high
IOA0 ~ IOA5
I/O A/D converter input
IOA0 is PWM1P output (by option, default)
IOA1 is PWM1N output (by option)
Bi-direction I/O pin with system wake-up/pin change interrupt function
Software controlled pull-high
IOB0 ~ IOB2
I/O A/D converter input
IOB1 is PWM1P output(by option)
IOB2 is External CLK input for Timer
Input pin only with system wake-up/pin change interrupt function; voltage on this
IOB3/RSTB
IOB4/OSCO
IOB5/OSCI
IOB6 ~ IOB7
I
pin must not exceed VDD.
System clear (RESET) input. This pin is an active low RESET to the device
Bi-direction I/O port with system wake-up/pin change interrupt function
I/O Software controlled pull-high
Oscillator output (HF, XT, LF, ERC mode)
Bi-direction I/O port with system wake-up/pin change interrupt function (IRC mode)
I/O Software controlled pull-high
Oscillator input (HF, XT, LF, ERC mode)
Bi-direction I/O pin with system wake-up/pin change interrupt function
I/O Software controlled pull-high
A/D converter input
VR
-
-
-
ADC module reference input, voltage on this pin must not exceed VDD.
VDD
VSS
Positive supply
Ground
Legend: I=input, O=output, I/O=input/output
Note: Please refer to 2.2 for detail IO type description
Web site: http://www.feeling-teccom.tw
Rev1.0 Nov 20, 2013
P.4/FM8P73B
EELING
FM8P73B
1.0 MEMORY ORGANIZATION
FM8P73B memory is organized into program memory and data memory.
1.1 Program Memory Organization
The FM8P73B has a 10-bit Program Counter capable of addressing a 1K×14 program memory space.
The RESET vector for the FM8P73B is at 3FFh.
The H/W interrupt vector is at 3FEh.
User can use “CALL/GOTO” instructions to program user's code within entire program area.
Figure 1.1: Program Memory Map and STACK
PC<9:0>
Stack 1
Stack 2
Stack 3
Stack 4
Stack 5
Stack 6
3FFh
Reset Vector
3FEh H/W Interrupt Vector
:
:
000h
FM8P73B
Web site: http://www.feeling-teccom.tw
Rev1.0 Nov 20, 2013
P.5/FM8P73B
EELING
FM8P73B
1.2 Data Memory Organization
Data memory is composed of 27 bytes Special Function Registers and 64 bytes General Purpose Registers.
The data memory can be accessed either directly or indirectly through the FSR register.
Table 1.1: Registers File Map for FM8P73B
Address
Description
00h
:
:
Special Purpose
Register
24h
30h
:
:
General Purpose
Register
6Fh
Table 1.2: Special Purpose Registers Map
Address
System
Name
B7
B6
B5
B4
B3
B2
B1
B0
C
00h (r/w)
02h (r/w)
03h (r/w)
04h (r/w)
INDF
PCL
Uses contents of FSR to address data memory (not a physical register)
Low order 8 bits of PC
̅̅̅̅
̅̅̅̅
PD
STATUS
FSR
-
-
PS
TO
Z
DC
0
Indirect data memory address pointer
IO PAD & CONTROL
05h (r/w)
06h (r/w)
07h (r/w)
08h (r/w)
IOSTA
PORTA
IOSTB
PORTB
-
-
-
-
IOSTA5 IOSTA4 IOSTA3 IOSTA2 IOSTA1 IOSTA0
IOA5
IOA4
IOA3
-
IOA2
IOA1
IOA0
IOSTB7 IOSTB6 IOSTB5 IOSTB4
IOSTB2 IOSTB1 IOSTB0
IOB7
IOB6
IOB5
IOB4
IOB3
IOB2
IOB1
IOB0
Timer1: 8-bit Timer & PWM1 Period
0Bh (r/w) T1CON T1EN
0Ch (r/w) PWM1CON T12MOD PWMS
T1LOAD T1SO1
T1SO0
-
T1EDG
PIR13
T1PS2
PIR12
T1PS1
PIR11
T1PS0
PIR10
POPS
0Dh (r/w)
14h (r/w)
T1LA
8-bit real-time timer Latch
SYNPWM SYNEN
PINV
DISN
-
-
-
DELS1
T2PS1
DELS0
T2PS0
Timer2: 8-bit Timer & PWM1 Duty
0Fh (r/w)
10h (r/w)
T2CON
T2LA
T2EN
T2LOAD T2SO1
T2SO0
T2EDG
T2PS2
8-bit real-time timer Latch
Timer3: 8-bit Timer
22h (r/w)
24h (r/w)
T3CON
T3EN
T3LOAD T3SO1
T3SO0
T3EDG
T3PS2
T3PS1
T3PS0
T3LA
8-bit real-time timer Latch
IRQ
15h (r/w)
16h (r/w)
ADC Control
17h (r/w)
18h (r/w)
19h (r/w)
1Ah (r)
INTEN
GIE
-
ADCIE
ADCIF
PBIE
PBIF
-
-
-
-
T3IE
T3IF
T2IE
T2IF
T1P1IE
T1P1IF
INTFLAG
ADCON1
ADCON2
ADCON3
ADDATL
ADDATH
ADCEN
-
-
-
-
-
-
CHSL3
-
CHSL2
-
CHSL1
CHSL0
-
CLKSL1 CLKSL0
-
-
-
-
ANISL3 ANISL2 ANISL1 ANISL0
D1
D9
D0
D8
-
-
-
-
-
-
1Bh (r)
D7
D6
D5
D4
D3
D2
Web site: http://www.feeling-teccom.tw
Rev1.0 Nov 20, 2013
P.6/FM8P73B
EELING
FM8P73B
Address
Others
Name
B7
B6
B5
B4
B3
B2
B1
B0
1Dh(r/w)
1Eh(r/w)
20h(r/w)
21h (r/w)
APHCON
BPHCON
INTPB
-
-
PHA5
PHB5
PHA4
PHB4
PHA3
-
PHA2
PHB2
PHA1
PHB1
PHA0
PHB0
PHB7
PHB6
PB7IEN PB6IEN PB5IEN PB4IEN PB3IEN PB2IEN PB1IEN PB0IEN
WDTCON
-
I_WDT I_TWDT EXCLK
-
WDTPS2 WDTPS1 WDTPS0
Legend: - = unimplemented, read as ‘0’.
Web site: http://www.feeling-teccom.tw
Rev1.0 Nov 20, 2013
P.7/FM8P73B
EELING
FM8P73B
2.0 FUNCTIONAL DESCRIPTIONS
2.1 Operational Registers
2.1.1
INDF (Indirect Addressing Register)
Address
00h (r/w)
Name
INDF
B7
B6
B5
B4
B3
B2
B1
B0
Uses contents of FSR to address data memory (not a physical register)
The INDF Register is not a physical register. Any instruction accessing the INDF register can actually access the
register pointed by FSR Register. Reading the INDF register itself indirectly (FSR=”0”) will read 00h. Writing to
the INDF register indirectly results in a no-operation (although status bits may be affected).
Example 2.1: INDIRECT ADDRESSING
Register file 30 contains the value 10h
Register file 31 contains the value 0Ah
Load the value 30 into the FSR Register
A read of the INDF Register will return the value of 10h
Increment the value of the FSR Register by one (@FSR=31h)
A read of the INDF register now will return the value of 0Ah.
Figure 2.1: Direct/Indirect Addressing for FM8P73B
Direct Addressing
From opcode
Indirect Addressing
From FSR register
7
0
0
7
0
6
0
00h
location select
addressing INDF register
location select
6Fh
Web site: http://www.feeling-teccom.tw
Rev1.0 Nov 20, 2013
P.8/FM8P73B
EELING
FM8P73B
2.1.2
PCL (Low Bytes of Program Counter) & Stack
Address
02h (r/w)
Name
PCL
B7
B6
B5
B4
B3
B2
B1
B0
Low order 8 bits of PC
FM8P73B device have a 10-bits wide Program Counter (PC) and six-level deep 10-bit hardware push/pop stack.
The low byte of PC is called the PCL register. This register is readable and writable.
As a program instruction is executed, the Program Counter will contain the address of the next program
instruction to be executed. The PC value is increased by one, every instruction cycle, unless an instruction
changes the PC.
Figure 2.2: Loading of PC in Different Situations
Situation 1: GOTO Instruction
PCH
PCL
9
8
7
0
PC
Opcode <9:0>
STACK<9:0>
Situation 2: CALL Instruction
PCH
PCL
9
8
7
0
PC
Opcode <9:0>
STACK<9:0>
Situation 3: RETIA, RETFIE, or RETURN Instruction
PCH
PCL
9
8
7
0
PC
Situation 4: Instruction with PCL as destination
PCH
PCL
9
8
0
7
-
0
PC
ALU result <7:0>
Or Opcode <7:0>
STATUS
-
PS
-
-
-
-
-
Note: PC<9:8> cannot be accessed.
Web site: http://www.feeling-teccom.tw
Rev1.0 Nov 20, 2013
P.9/FM8P73B
EELING
FM8P73B
2.1.3
STATUS (Status Register)
Address
03h (r/w)
Name
B7
-
B6
-
B5
PS
B4
B3
̅̅̅̅
PD
B2
Z
B1
B0
C
̅̅̅̅
STATUS
TO
DC
Legend: - = unimplemented, read as ‘0’.
This register contains the arithmetic status of the ALU, the RESET status.
If the STATUS Register is the destination for an instruction that affects the Z, DC or C bits, then the write to these
̅̅̅̅
̅̅̅̅
three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD
bits are not writable. Therefore, the result of an instruction with the STATUS Register as destination may be
different than intended. For example, CLRR STATUS will clear the upper three bits and set the Z bit. This leaves
the STATUS Register as 000u u1uu (where u = unchanged).
C : Carry/borrow bit.
ADDAR
= 1, Carry occurred.
= 0, No Carry occurred.
SUBAR
= 1, No borrow occurred.
= 0, Borrow occurred.
Note : A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRR,
RLR) instructions, this bit is loaded with either the high or low order bit of the source register.
DC : Half carry/half borrow bit
ADDAR
= 1, Carry from the 4th low order bit of the result occurred.
= 0, No Carry from the 4th low order bit of the result occurred.
SUBAR
= 1, No Borrow from the 4th low order bit of the result occurred.
= 0, Borrow from the 4th low order bit of the result occurred.
Z : Zero bit.
= 1, The result of a logic operation is zero.
= 0, The result of a logic operation is not zero.
̅̅̅̅
PD : Power down flag bit.
= 1, after power-up or by the CLRWDT instruction.
= 0, by the SLEEP instruction.
̅̅̅̅
TO : Watch-dog timer overflow flag bit.
= 1, after power-up or by the CLRWDT or SLEEP instruction
= 0, a watch-dog time overflow occurred
PS : ROM Page Select bit
= 1, 200h ~ 2FFh
= 0, 000h ~ 0FFh
Web site: http://www.feeling-teccom.tw
Rev1.0 Nov 20, 2013
P.10/FM8P73B
EELING
FM8P73B
2.1.4
FSR (Indirect Data Memory Address Pointer)
Address
04h (r/w)
Name
FSR
B7
0
B6
B5
B4
B3
B2
B1
B0
Indirect data memory address pointer
Bit6:Bit0 : Select registers address in the indirect addressing mode. See 2.1.1 for detail description.
Bit7 : Not used. Read as 0.
2.1.5
PORTA, PORTB, IOSTA and IOSTB (Port Data Registers and Port Direction Control Registers)
Address
Name
IOSTA
PORTA
IOSTB
PORTB
B7
B6
B5
B4
B3
B2
B1
B0
05h (r/w)
06h (r/w)
07h (r/w)
08h (r/w)
-
-
-
-
IOSTA5 IOSTA4 IOSTA3 IOSTA2 IOSTA1 IOSTA0
IOA5
IOA4
IOA3
-
IOA2
IOSTB2 IOSTB1 IOSTB0
IOB2 IOB1 IOB0
IOA1
IOA0
IOSTB7 IOSTB6 IOSTB5 IOSTB4
IOB7 IOB6 IOB5 IOB4
IOB3
Legend: - = unimplemented, read as ‘0’.
The registers (IOSTA and IOSTB) are used to define the input or output of each port.
= 1, Input.
= 0, Output.
Reading the port (PORTA and PORTB register) reads the status of the pins independent of the pin’s input/output
modes. Writing to these ports will write to the port data latch. Please refer to 2.2 for detail I/O Port description.
Note: IOB3 is read only.
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Rev1.0 Nov 20, 2013
P.11/FM8P73B
EELING
FM8P73B
2.1.6
Timer1: 8-bit Timer & PWM1 Period
The Timer1 is an 8-bit down-count timer which include latch register. Please refer to 2.3 for detail Timer
description.
The Timer1 can also be combined with Timer2 as PWM1 period and duty and controlled by the register
PWM1CON. Please refer to 2.4 for detail PWM description.
2.1.6.1 T1CON (Timer1 Control Register)
Address
Name
B7
B6
B5
B4
B3
B2
B1
B0
0Bh (r/w)
T1CON
T1EN
T1LOAD T1SO1
T1SO0
T1EDG
T1PS2
T1PS1
T1PS0
T1EN : TMR1 (PWM) Enable/Disable
= 1, TMR1 (PWM1) Enable.
= 0, TMR1 (PWM1) Disable.
T1LOAD : Enable/Disable Latch Buffer automatically load to counter register while writing to latch register
= 1, Enable TMR1 latch buffer automatically load to counter register while writing to latch register.
= 0, Disable TMR1 latch buffer automatically load to counter register while writing to latch register.
Note: This bit is only affected after latch register written. When the timer underflows, the latch register
data will automatically load into counter register.
T1SO1:T1SO0 : TMR1 clock source selection
T1SO1
T1SO0
TMR1 clock source
0
0
1
1
0
1
0
1
TMCKI(IOB2)
Internal instruction clock cycle
Fosc
Fosc*2
T1EDG : TMR1 clock edge selection. This bit works only when external clock source TMCKI (IOB2) selected.
= 1, TMR1 increased on falling edge of TMCKI pin.
= 0, TMR1 increased on rising edge of TMCKI pin.
T1PS2:T1PS0 : TMR1 Prescaler selection
T1PS2 : T1PS0
TMR1 Prescal rate
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
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Rev1.0 Nov 20, 2013
P.12/FM8P73B
EELING
FM8P73B
2.1.6.2 PWM1CON (PWM1 Control Register)
Address
Name
B7
B6
B5
B4
-
B3
B2
B1
B0
0Ch (r/w) PWM1CON T12MOD PWMS
Legend: - = unimplemented, read as ‘0’.
POPS
PIR13
PIR12
PIR11
PIR10
T12MOD : TMR1 operation mode select bit.
= 1, The TMR1 and TMR2 in PWM mode operation.
= 0, The TMR1 and TMR2 in Timer mode operation.
PWMS : Initial State of PWM1P output duty.
= 1, Set the initial state to L, change to H when TMR2 duty underflow.
= 0, Set the initial state to H, change to L when TMR2 duty underflow.
POPS : PWM Output Pin Select bit.
= 1, The PWM1P output from IOB1.
= 0, The PWM1P output from IOA0.
PIR13:PIR10 : Interrupt Event Rate of PWM1.
“1:N” means interrupt occurred after “N” PWM1 pulses.
PIR13 : PIR10
PWM1 Interrupt rate
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
1:1
1:2
1:3
1:4
|
|
1
1
1
1
1
1
0
1
1
1
0
1
1:14
1:15
1:16
2.1.6.3 T1LA (Timer1 Latch Register)
Address
Name
T1LA
B7
B6
B5
B4
B3
B2
B1
B0
0Dh (r/w)
8-bit real-time timer Latch
T1LA is a Timer1 pre-set latch buffer, see 2.3 for detail description.
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Rev1.0 Nov 20, 2013
P.13/FM8P73B
EELING
FM8P73B
2.1.6.4 SYNPWM (Sync PWM Control Register)
Address
14h (r/w)
Name
B7
B6
B5
B4
-
B3
-
B2
-
B1
B0
SYNPWM SYNEN
PINV
DISN
DELS1
DELS0
Legend: - = unimplemented, read as ‘0’.
SYNEN : Sync PWM mode enable/disable.
In PWM mode:
= 1, Sync PWM mode Enable (PWM1N output on IOA1, PWM1P output on IOA0 or IOB1 select by
POPS bit).
= 0, Sync PWM mode Disable, IOA1 is I/O.
In Timer mode:
Ignore
PINV : PWM_P invert bit.
In Sync PWM mode:
= 1, PWM1P is invert output.
= 0, PWM1P is normal output.
Note: This function is only available in pin IOA0.
else:
Ignore.
DISN : PWM1N enable/disable.
In Sync PWM mode:
= 1, IOA1 is normal I/O.
= 0, IOA1 is PWM1N output.
else:
Ignore
DELS1:DELS0 : Sync PWM Non overlap time (PWM1P & PWM1N) selection bits.
DELS1
DELS0
Non overlap time
0
0
1
1
0
1
0
1
1/2 cycle time
1 cycle time
3/2 cycle time
2 cycle time
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P.14/FM8P73B
EELING
FM8P73B
2.1.7
Timer2: 8-bit Timer & PWM1 Duty
The Timer2 is an 8-bit down-count timer which include latch register. Please refer to 2.3 for detail Timer
description.
2.1.7.1 T2CON (Timer2 Control Register)
Address
0Fh (r/w)
Name
B7
B6
B5
B4
B3
B2
B1
B0
T2CON
T2EN
T2LOAD T2SO1
T2SO0
T2EDG
T2PS2
T2PS1
T2PS0
T2EN : TMR2 Enable/Disable
= 1, TMR2 (PWM1) Enable.
= 0, TMR2 (PWM1) Disable.
Note: At PWM mode, Timer2 is controlled by T1EN.
T2LOAD : Enable/Disable Latch Buffer automatically load to counter register while writing to latch register
= 1, Enable TMR2 latch buffer automatically load to counter register while writing to latch register.
= 0, Disable TMR2 latch buffer automatically load to counter register while writing to latch register.
Note: This bit is only affected after latch register written. When the timer underflows, the latch register
data will automatically load into counter register.
T2SO1:T2SO0 : TMR2 clock source selection
T2SO1
T2SO0
TMR2 clock source
0
0
1
1
0
1
0
1
TMCKI(IOB2)
Internal instruction clock cycle
Fosc
Fosc*2
T2EDG : TMR2 clock edge selection. This bit works only when external clock source TMCKI (IOB2) selected.
= 0, TMR2 increased on rising edge of TMCKI pin.
= 1, TMR2 increased on falling edge of TMCKI pin.
T2PS2:T2PS0 : TMR2 Prescaler selection
T2PS2 : T2PS0
TMR2 Prescal rate
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
2.1.7.2 T2LA (Timer2 Latch Register)
Address
10h (r/w)
Name
T2LA
B7
B6
B5
B4
B3
B2
B1
B0
8-bit real-time timer Latch
T2LA is a Timer2 pre-set latch buffer, see 2.3 for detail description.
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P.15/FM8P73B
EELING
FM8P73B
2.1.8
Timer3: 8-bit Timer
The Timer3 is an 8-bit down-count timer which include latch register. Please refer to 2.3 for detail Timer
description.
2.1.8.1 T3CON (Timer3 Control Register)
Address
22h (r/w)
Name
B7
B6
B5
B4
B3
B2
B1
B0
T3CON
T3EN
T3LOAD T3SO1
T3SO0
T3EDG
T3PS2
T3PS1
T3PS0
T3EN : TMR3 Enable/Disable
= 1, TMR3 Enable.
= 0, TMR3 Disable.
T3LOAD : Enable/Disable Latch Buffer automatically load to counter register while writing to latch register
= 1, Enable TMR3 latch buffer automatically load to counter register while writing to latch register.
= 0, Disable TMR3 latch buffer automatically load to counter register while writing to latch register.
Note: This bit is only affected after latch register written. When the timer underflows, the latch register
data will automatically load into counter register.
T3SO1:T3SO0 : TMR3clock source selection
T3SO1
T3SO0
TMR3clock source
0
0
1
1
0
1
0
1
TMCKI(IOB2)
Internal instruction clock cycle
Fosc
No function, don’t use
T3EDG : TMR3 clock edge selection. This bit works only when external clock source TMCKI (IOB2) selected.
= 1, TMR3 increased on falling edge of TMCKI pin.
= 0, TMR3 increased on rising edge of TMCKI pin.
T3PS2:T3PS0 : TMR3 Prescaler selection
T3PS2 : T3PS0
TMR3 Prescal rate
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
2.1.8.2 T3LA (Timer3 Latch Register)
Address
24h (r/w)
Name
T3LA
B7
B6
B5
B4
B3
B2
B1
B0
8-bit real-time timer Latch
T3LA is a Timer3 pre-set latch buffer, see 2.3 for detail description.
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Rev1.0 Nov 20, 2013
P.16/FM8P73B
EELING
FM8P73B
2.1.9
INTEN (Interrupt Mask Register)
Address
15h (r/w)
Name
B7
B6
B5
B4
-
B3
-
B2
B1
B0
INTEN
GIE
ADCIE
PBIE
T3IE
T2IE
T1P1IE
Legend: - = unimplemented, read as ‘0’.
GIE : Global interrupt enable bit.
= 1, Enable all un-masked interrupts.
= 0, Disable all interrupts.
Note : When an interrupt event occurred with the GIE bit and its corresponding interrupt enable bits are set,
the GIE bit will be cleared by hardware to disable any further interrupts. The RETFIE instruction will
exit the interrupt routine and set the GIE bit to re-enable interrupt.
ADCIE : ADC conversion completed interrupt enable bit.
= 1, Enable interrupt.
= 0, Disable interrupt.
PBIE : PORTB interrupt enable
= 1, Enable interrupt.
= 0, Disable interrupt.
T3IE : Timer2 underflow interrupt enable bit.
= 1, Enable interrupt.
= 0, Disable interrupt.
T2IE : Timer2 underflow interrupt enable bit.
= 1, Enable interrupt.
= 0, Disable interrupt.
T1P1IE : Timer1 / PWM1 underflow interrupt enable bit.
= 1, Enable interrupt.
= 0, Disable interrupt.
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P.17/FM8P73B
EELING
FM8P73B
2.1.10 INTFLAG (Interrupt Status Register)
Address
16h (r/w)
Name
B7
-
B6
B5
B4
-
B3
-
B2
B1
B0
INTFLAG
ADCIF
PBIF
T3IF
T2IF
T1P1IF
Legend: - = unimplemented, read as ‘0’.
ADCIF : ADC Interrupt flag. Set when ADC conversion is completed, reset by software.
PBIF : Port B <7:0> Interrupt flag. Set when pin changed on selected I/O by register INTPB, and reset by
software.
T3IF : TMR3 interrupt flag. Set when TMR3 underflows, and reset by software.
T2IF : TMR2 interrupt flag. Set when TMR2 underflows, and reset by software.
T1P1IF : TMR1 interrupt or PWM1 interrupt flag. Set when TMR1 underflows or PWM1 pulse counts to selected
interrupt rate, and reset by software.
2.1.11 ADCON1 (AD converter Control Register1)
Address
17h (r/w)
Name
B7
B6
-
B5
-
B4
-
B3
B2
B1
B0
ADCON1
ADCEN
CHSL3
CHSL2
CHSL1
CHSL0
Legend: - = unimplemented, read as ‘0’.
ADCEN : ADC enable/disable setting
= 0, Disable.
= 1, Enable.
Note : This bit should be set by software and would be reset by hardware after the ADC end of
conversion.
CHSL3:CHSL0 : ADC input channel select
CHSL3 CHSL2 CHSL1 CHSL0
Input channel
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
Channel 0, IOA0 pin
Channel 1, IOA1 pin
Channel 2, IOA2 pin
Channel 3, IOA3 pin
Channel 4, IOA4 pin
Channel 5, IOA5 pin
Channel 6, IOB0 pin
Channel 7, IOB1 pin
Channel 8, IOB2 pin
Channel 9, IOB6 pin
Channel 10, IOB7 pin
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Rev1.0 Nov 20, 2013
P.18/FM8P73B
EELING
FM8P73B
2.1.12 ADCON2 (AD converter Control Register2)
Address
18h (r/w)
Name
B7
-
B6
-
B5
-
B4
-
B3
-
B2
-
B1
B0
ADCON2
CLKSL1 CLKSL0
Legend: - = unimplemented, read as ‘0’.
CLKSL1:CLKSL0 : ADC Conversion clock source select bits.
CKSL1
CKSL0
Conversion clock
0
0
1
1
0
1
0
1
System clock /2 (fastest result, lowest quality)
System clock /8
System clock /32
System clock /128 (slowest result, best quality)
Note : The conversion clocks decide the conversion rate and precision. If fast conversion clock is selected, that
will drop-off the precision. If want to get more accurate A/D data, use slow speed is recommended.
2.1.13 ADCON3 (AD converter Control Register3)
Address
19h (r/w)
Name
B7
-
B6
-
B5
-
B4
-
B3
B2
B1
B0
ADCON3
ANISL3 ANISL2 ANISL1 ANISL0
Legend: - = unimplemented, read as ‘0’.
ANISL3:ANISL0 : Analog input select bits.
ANISL3 ANISL2 ANISL1 ANISL0
Analog input selection
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
All the ports are digital input
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
Note : To minimize power consumption, all the I/O pins should be carefully managed before entering sleep mode.
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Rev1.0 Nov 20, 2013
P.19/FM8P73B
EELING
FM8P73B
2.1.14 ADDATL, ADDATH (AD conversion data high and low)
Address
1Ah (r)
1Bh (r)
Name
B7
D1
D9
B6
D0
D8
B5
-
B4
-
B3
-
B2
-
B1
-
B0
-
ADDATL
ADDATH
D7
D6
D5
D4
D3
D2
Legend: - = unimplemented, read as ‘0’.
The ADDATL and ADDATH registers is ADC conversion result. When ADC conversion is completed, the result is
loaded into ADDATL and ADDATH, the ADCEN bit will be cleared, and the ADCIF bit will be set (if ADCIE are set).
2.1.15 APHCON, BPHCON (Port A and Port B Pull-high Control)
Address
1Dh(r/w)
1Eh(r/w)
Name
B7
-
B6
-
B5
B4
B3
PHA3
-
B2
B1
B0
APHCON
BPHCON
PHA5
PHB5
PHA4
PHB4
PHA2
PHB2
PHA1
PHB1
PHA0
PHB0
PHB7
PHB6
Legend: - = unimplemented, read as ‘0’.
Those registers are used to setup pull-high resistor enable/disable of each IO pins.
= 1, Pull-high resistor enable.
= 0, Pull-high resistor disable.
2.1.16 INTPB (Port B Interrupt / Wakeup control)
Address
20h(r/w)
Name
INTPB
B7
B6
B5
B4
B3
B2
B1
B0
PB7IEN PB6IEN PB5IEN PB4IEN PB3IEN PB2IEN PB1IEN PB0IEN
This register is used to enable/disable the interrupt/wakeup function of Port B. Please refer to 2.7.1 for detail
description of External Interrupt and Wake up function.
= 1, Selected IO interrupt/wakeup enable.
= 0, Selected IO interrupt/wakeup disable.
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Rev1.0 Nov 20, 2013
P.20/FM8P73B
EELING
FM8P73B
2.1.17 WDTCON (Watchdog Timer Control Register)
Address
21h (r/w)
Name
B7
-
B6
B5
B4
B3
-
B2
B1
B0
WDTCON
I_WDT I_TWDT EXCLK
WDTPS2 WDTPS1 WDTPS0
Legend: - = unimplemented, read as ‘0’.
The FM8P73B builds in a watchdog timer with two different modes, normal watchdog reset and internal watchdog
wakeup. The watchdog timer is controlled by this register (WDTCON). Please refer to 2.5 for detail Watchdog
Timer description.
I_WDT : Internal Watchdog Wakeup mode selection.
= 1, Internal Watchdog Wakeup Enable.
= 0, Internal Watchdog Wakeup Disable.
I_TWDT : Watchdog Timer Stable time required when operating in I_WDT mode.
= 1, 1.25ms.
= 0, 2.5ms (default).
EXCLK : IOB2/TMCKI function selection
= 1, IOB2 is external clock input of timer.
= 0, IOB2 is normal I/O.
WDTPS2:WDTPS0 : Watchdog timer prescaler setting
WDTPS2 : WDTPS0
WDT prescaler rate
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
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Rev1.0 Nov 20, 2013
P.21/FM8P73B
EELING
FM8P73B
2.2 I/O Ports
There are totally 13 bi-directional tri-state I/O ports and one (IOB3) input only. All I/O pins (IOA<5:0>, IOB<7:0>)
have specified data direction control registers (IOSTA, IOSTB) which can configure these pins as output or input.
All the IO pins can also enable or disable a weak internal pull-high by setting APHCON and BPHCON. This weak
pull-high will be automatically turned off when the pin is configured as an output pin.
VR pin is reference voltage input pin of the ADC module, this pin does not have I/O function. The voltage on this
pin must not exceed VDD, otherwise it will cause the pin burned down.
Figure 2.3: Block Diagram of I/O Pins
IOA5 ~ IOA0:
DATA BUS
D
Q
IOST
Latch
WR IOST
EN
Q
Q
I/O PIN
D
DATA
Latch
WR PORT
RD PORT
EN
Q
Pull-high/ADC control is not shown in this figure
IOB7 ~ IOB4, IOB2 ~ IOB0:
DATA BUS
D
Q
IOST
Latch
WR IOST
EN
Q
Q
I/O PIN
D
DATA
Latch
WR PORT
RD PORT
EN
Q
D
Q
Q
Set PBIF
PBIENx
Latch
EN
Pull-high/ADC/OSC control is not shown in this figure
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P.22/FM8P73B
EELING
FM8P73B
IOB3:
DATA BUS
RD PORT
I/O PIN
Q
Q
D
Set PBIF
PB3IEN
Latch
EN
Voltage on this pin must not exceed VDD.
VR:
To ADC module
VR PIN
Voltage on this pin must not exceed VDD.
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Rev1.0 Nov 20, 2013
P.23/FM8P73B
EELING
FM8P73B
2.3 Timer/Event Counter (TMR1, TMR2, TMR3)
The FM8P73B contains three 8-bit down-count Timers. All these timers have auto reload function, TMR1/TMR2
can be combined to perform PWM function
Figure 2.4: Block Diagram of the Timer
WR TxLA
TMRx
Latch
TxSO<1:0>
0 0
TxLOAD
TMCKI (IOB2)
Instruction Cycle
(Fosc/2 or Fosc/4)
0 1
1 0
1 1
TxPS<2:0>
Prescaler
MUX
Fosc
TMRx
Counter
Set TxIF flag
on unerflow
Fosc*2
(Only Timer1 & 2)
2.3.1
Clock Source
There are 4 clock sources could be selected by each timer separately.
2.3.1.1 TMCKI (IOB2)
The event counter mode would be activated when the source of TMCKI (IOB2) used. At this mode, the rising/
falling edge of the event could also be selected separately.
2.3.1.2 Instruction cycle
In this mode, the timer will down-count on every instruction cycle (if prescaler is 1:1).
2.3.1.3 FOSC
In this mode, timer clock source defined by the FOSC bit in the configuration word.
2.3.1.4 FOSC *2
In this mode, the oscillator frequency is multiplied by 2, as the timer clock source. Oscillator modes defined by the
FOSC bit in the configuration word.
Note : 1. In this mode, the frequency multiplier minimum operating voltage limits, please refer to
electrical characteristics table VPWM item.
2. This mode only for Timer1 and Timer2.
2.3.2
Prescaler
Each timer contains a 3-bits prescaler which can scale the timer or counter from 1:1 to 1:128.
T1PS2 : T1PS0
TMR1 Prescal rate
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
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P.24/FM8P73B
EELING
FM8P73B
2.4 Pulse Width Modulation (PWM)
FM8P73B provides one PWM output shared with TMR1/2, TMR1 becomes the period of PWM1 and TMR2 will be
the duty of PWM1.
If the system frequency is 4MHz, the range of PWM period could be from 0.5us to 8,192ms.
2.4.1
Normal PWM mode
In this mode, it is a general purpose PWM mode. Please refer to the sample program and timing diagram below.
Note : When PWM duty or period needed to be changed, the auto-load control bit of the timer (TxLOAD) must be
cleared before new data writes to latch register. If this bit still set, the data written to latch register would
be load into counter register immediately and cause PWM output anomaly.
Example 2.2: PWM1 Setting (Normal mode)
Address
NA
Code
#include
<8P73B.ASH>
…
//Set PWM1 Period
MOVIA
n
0x61
n+1
n+2
n+3
n+4
n+5
MOVAR
T1CON
0x80
;Set source: 4MHz IRC (250nS) Prescaler 1:2
;Set PWM interrupt rate 1:1, output on IOA0
MOVIA
MOVAR
MOVIA
PWM1CON
0x0F
MOVAR
T1LA
;Set period (0x0F down count to 0x00)
;Period time = 250ns x 16 x 2 = 8uS
//Set PWM1 Duty
MOVIA
n+6
n+7
n+8
n+9
0x61
MOVAR
MOVIA
T2CON
0x07
;Set source 4MHz IRC (250nS) Prescaler 1:2
MOVAR
T2LA
;Set Duty (0x07 down count to 0x00)
;Duty time = 250ns x 8 x2 = 4uS
;Start PWM1
n+10
n+11
n+12
n+13
BSR
T1CON,T1EN_B
0x81
MOVIA
MOVAR
CLRR
INTEN
INTFLAG
;Enable global & PWM1 interrupt
;Clear interrupt flag
Note: The PWM duty (Timer2) must be smaller than PWM period (Timer1).
Figure 2.5: Normal PWM Output Waveform
0D 0C
01 00 0D 0C
0D 0C
TMR1 counter:
PWM Period
PWM Duty
PWM1P Output:
TMR2 counter:
0A 09
01 00
0A 09
01 00
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Rev1.0 Nov 20, 2013
P.25/FM8P73B
EELING
FM8P73B
2.4.2
Sync PWM mode
In Sync PWM mode, the PWM has two outputs. PWM1N Non overlap time can be adjusted from SYNPWM<1:0>,
please refer to the sample program and the timing diagram below.
Example 2.3: PWM1 Setting (Sync mode)
Address
NA
Code
#include
<8P73B.ASH>
…
//Set PWM1 Period
MOVIA
n
0x61
n+1
n+2
n+3
n+4
n+5
MOVAR
T1CON
0x80
;Set source: 4MHz IRC (250nS) Prescaler 1:2
;Set PWM interrupt rate 1:1, output on IOA0
MOVIA
MOVAR
MOVIA
PWM1CON
0x0F
MOVAR
T1LA
;Set period (0x0F down count to 0x00)
;Period time = 250ns x 16 x 2 = 8uS
//Set PWM1 Duty
MOVIA
n+6
n+7
n+8
n+9
0x61
MOVAR
MOVIA
T2CON
0x07
;Set source 4MHz IRC (250nS) Prescaler 1:2
MOVAR
T2LA
;Set Duty (0x07 down count to 0x00)
;Duty time = 250ns x 8 x2 = 4uS
//Set Sync PWM
MOVIA
n+10
n+11
0x82
MOVAR
SYNPWM
;Set PWM1P is normal, IOA1 is PWM1N output
;Non overlap time = 3/2 cycle time
;Start PWM1
n+12
n+13
n+14
n+15
BSR
T1CON,T1EN_B
0x81
INTEN
MOVIA
MOVAR
CLRR
;Enable global & PWM1 interrupt
;Clear interrupt flag
INTFLAG
Note: The PWM duty (Timer2) must be smaller than PWM period (Timer1).
Figure 2.6: Sync PWM Waveform
0D 0C
01 00
TMR1 counter :
PWM Period
PWM Duty
Sync PWM1P output :
Sync PWM1N output :
Non Overlap time
=3/2 cycle
0A 09
01 00
TMR2 counter :
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Rev1.0 Nov 20, 2013
P.26/FM8P73B
EELING
FM8P73B
2.5 Watch Dog Timer (WDT)
The Watchdog Timer (WDT) is a free running on-chip RC oscillator which does not require any external
components. So the WDT will still run even if the clock on the OSCI and OSCO pins is turned off, such as in
SLEEP mode.
The WDT has a typical time-out period of 20 ms (without prescaler). This period of this timer may be variant
slightly because of temperature, voltage, and process variation. If a longer time-out period is desired, a prescaler
with a division ratio of up to 1:128 can be assigned to the WDT controlled by the WDTCON register <2:0>. Thus,
the longest time-out period is approximately 2.56 seconds.
The CLRWDT instruction clears the WDT and prevents it from timing out and generating a device reset.
The SLEEP instruction also resets the WDT. This gives the maximum SLEEP time before a WDT Wake-up
Reset.
There are two type of watchdog timer mode could be selected by I_WDT (WDTCON <6>). When I_WDT bit
disable, normal watchdog timer reset is selected. During normal operation or in SLEEP mode, a WDT time-out
̅̅̅̅
will cause the device reset and the TO bit (STATUS<4>) will be cleared.
If I_WDT bit enabled, the internal watchdog timer wakeup will be used. The system wakeups from sleep, then
jumps into interrupt vector with external interrupt request PBIF (INTFLAG<5>) and continues from next instruction
instead of triggering a reset event. There is a stabilization time required for internal watchdog wakeup could be
selected by I_ TWDT (WDTCON<5>). The default value of this stabilization timer is 2.5ms.
Example 2.4: Internal Watchdog Wakeup
Address
NA
Code
#include
<8P73B.ASH>
…
n
MOVIA
MOVAR
CLRWDT
MOVIA
MOVAR
…
0xA0
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
INTEN
;Enable global & Port B interrupt
;Sleep: 2.56S + Wakeup:1.25mS
0x67
WDTCON
…
SLEEP
NOP
1. WDT Wakeup
…
2. Return from ISR
N/A
200
ISR:
;In this example, ISR define at 0x200
;User WDT Wakeup ISR code
…
200+n
200+n+1
200+n+2
MOVIA
MOVAR
RETFIE
0xDF
INTFLAG
;Clear PBIF flag(Note1)
0x3FE
0x3FF
GOTO
GOTO
ISR
START
Note : 1. BCR instruction is not recommended for Clear interrupt flag (INTFLAG register).
2. Interrupt save status code is not shown in this example.
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Example 2.5: Typical Watchdog Reset
Address
NA
Code
#include
<8P73B.ASH>
…
n
CLRWDT
MOVIA
MOVAR
…
n+1
n+2
n+3
n+4
n+5
n+6
0x07
WDTCON
;Sleep: 2.56S + Wakeup:20mS
…
SLEEP
NOP
…
WDT Reset
…
0x3FF
GOTO
START
2.6 Reset
FM8P73B device may be RESET in one of the following ways:
1. Power-on Reset (POR)
2. Brown-out Reset (BOR)
3. RSTB Pin Reset
4. WDT time-out Reset
Some registers are not affected in any RESET condition. Their status is unknown on Power-on Reset and
unchanged in any other RESET. Most other registers are reset to a “reset state” on Power-on Reset, RSTB or
WDT Reset.
A Power-on RESET pulse is generated on-chip when Vdd rise is detected. To use this feature, the user merely
ties the RSTB pin to Vdd.
On-chip Low Voltage Detector (LVDT) places the device into reset when Vdd is below a fixed voltage. This
ensures that the device does not continue program execution outside the valid operation Vdd range. Brown-out
RESET is typically used in AC line or heavy loads switched applications.
A RSTB or WDT Wake-up from SLEEP also results in a device RESET, and not a continuation of operation before
SLEEP.
̅̅̅̅
̅̅̅̅
The TO and PD bits (STATUS<4:3>) are set or cleared depending on the different reset conditions.
2.6.1
Power-up Reset Timer(PWRT)
The Power-up Reset Timer provides a nominal 20ms delay after Power-on Reset (POR), Brown-out Reset (BOR),
RSTB Reset or WDT time-out Reset. The device is kept in reset state as long as the PWRT is active.
The PWDT delay will vary from device to device due to Vdd, temperature, and process variation.
Figure 2.7: Reset Timing
Case1: LVDT ON, RSTB Disable
VDD
PWRT time-out
Internal Reset
VLVDT
VLVDT
TPWRT
Note: TPWRT = 20mS
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FM8P73B
Case2: LVDT OFF, RSTB Enable
VDD
VIH
RSTB
VIL
PWRT time-out
Internal Reset
TPWRT
Note: TPWRT = 20mS
Case3: LVDT OFF, RSTB Disable
VDD
VDDmin
PWRT time-out
Internal Reset
TPWRT
Note: TPWRT = 20mS
Figure 2.8: Simplified Block Diagram of on-chip Reset Circuit
WDT
WDT Time-out
Module
(WarmStart)
Synchronize
With
System Clock
I WDT
Enable
RSTB
Cold Start
Low Voltage
VDD
Detector
(LVD)
RESET
On-Chip
RC OSC
Power-up
Reset Timer
(PWRT)
CHIP RESET
Power-on
Reset
(POR)
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FM8P73B
Table 2.1: Reset Conditions for Operational Registers
Power-on Reset
Brown-out Reset
WDT Reset
RSTB Reset
Register
Address
ACC
INDF
N/A
00h
02h
03h
04h
05h
06h
07h
08h
0Bh
0Ch
0Dh
0Fh
10h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Dh
1Eh
20h
21h
22h
24h
30 ~ 6Fh
xxxx xxxx
xxxx xxxx
1111 1111
0001 1xxx
0xxx xxxx
0011 1111
00xx xxxx
1111 0111
xxxx xxxx
0000 0000
0000 0000
1111 1111
0000 0000
1111 1111
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0111
0000 0000
1111 1111
xxxx xxxx
uuuu uuuu
uuuu uuuu
1111 1111
000# #xxx
0uuu uuuu
0011 1111
00uu uuuu
1111 0111
uuuu uuuu
0000 0000
0000 0000
1111 1111
0000 0000
1111 1111
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0111
0000 0000
1111 1111
uuuu uuuu
PCL
STATUS
FSR
IOSTA
PORTA
IOSTB
PORTB
T1CON
PWM1CON
T1LA
T2CON
T2LA
SYNPWM
INTEN
INTFLAG
ADCON1
ADCON2
ADCON3
ADDATL
ADDATH
APHCON
BPHCON
INTPB
WDTCON
T3CON
T3LA
General Purpose Registers
Legend: u = unchanged, x = unknown, - = unimplemented,
# = refer to the following table for possible values.
̅̅̅̅ ̅̅̅̅
Table 2.2: TO / PDStatus after Reset or Wake-up
̅̅̅̅
̅̅̅̅
TO
PD
RESET was caused by
Power-on Reset / Brown-out reset
RSTB Reset during normal operation
RSTB Reset during SLEEP
1
u
1
0
0
1
u
0
1
0
WDT timer overflow from normal mode
WDT timer overflow from sleep mode
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2.7 Interrupt
The FM8P73B has three kinds of interrupt sources:
1. 8 External IOB<0:7> pin changed interrupt
2. 3 Timers underflow interrupt (or PWM interrupt)
3. ADC conversion completion interrupt
INTFLAG is the interrupt flag register that recodes the interrupt requests to the relative flags.
A global interrupt enable bit, GIE (INTEN<7>), enables (if set) all un-masked interrupts or disables (if cleared) all
interrupts. Individual interrupts can be enabled/ disabled through their corresponding enable bits in INTEN
register regardless of the status of the GIE bit.
When an interrupt event occur with the GIE bit and its corresponding interrupt enable bit are all set, the GIE bit
will be cleared by hardware to disable any further interrupts, and the next instruction will be fetched from address
3FEh. The interrupt flag bits must be cleared by software before re-enabling GIE bit to avoid recursive interrupts.
The RETFIE instruction exits the interrupt routine and set the GIE bit to re-enable interrupt.
The flag bit in INTFLAG register is set by interrupt event regardless of the status of its mask bit.
2.7.1
PORTB<0:7> External Interrupt and Wakeup Function
The external interrupt on PORTB<0:7> are selected by INTPB<0:7> and PBIE (INTEN<5>). When the device is
in normal mode and the specified IO status changed, the interrupt event will be triggered and the program will
jump to 3FEh.
When the device is in sleep mode, those interrupts can also be used as an external wakeup signal. The device
will restart system clock and the program will jump to 3FEh after startup timer timeout.
Example 2.6: External IOB0 pin change interrupt
Address
NA
Code
#include
<8P73B.ASH>
…
n
MOVIA
MOVAR
MOVIA
MOVAR
MOVIA
MOVAR
MOVR
MOVIA
MOVAR
…
0xFF
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
IOSTB
0xA0
;Set Port B as input
INTEN
0xDF
INTFALG
PORTB,R
0x01
;Enable global & Port B interrupt
;Clear PBIF flag(Note1)
;Update Port B pin status
INTPB
;Set IOB0 pin change
…
…
1. IOB0 pin change
2. Return from ISR
N/A
200
ISR:
;In this example, ISR define at 0x200
;User Port B pin change ISR code
…
200+n
200+n+1
200+n+2
MOVIA
MOVAR
RETFIE
0xDF
INTFLAG
;Clear PBIF flag(Note1)
3FE
3FF
GOTO
GOTO
ISR
START
Note : 1. BCR instruction is not recommended for Clear interrupt flag (INTFLAG register).
2. Interrupt save status code is not shown in this example.
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Example 2.7: External IOB0 pin change wakeup interrupt
Address
NA
Code
#include
<8P73B.ASH>
…
n
MOVIA
MOVAR
MOVIA
MOVAR
MOVIA
MOVAR
MOVR
MOVIA
MOVAR
SLEEP
NOP
0xFF
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
n+10
IOSTB
0xA0
;Set Port B as input
INTEN
0xDF
INTFALG
PORTB,R
0x01
;Enable global & Port B interrupt
;Clear PBIF flag(Note1)
;Update Port B pin status
INTPB
;Set IOB0 pin change wakeup
…
1. IOB0 pin change
2. Return from ISR
N/A
200
ISR:
;In this example, ISR define at 0x200
;User Port B pin change wakeup ISR code
…
200+n
200+n+1
200+n+2
MOVIA
MOVAR
RETFIE
0xDF
INTFLAG
;Clear PBIF flag(Note1)
3FE
3FF
GOTO
GOTO
ISR
START
Note : 1. BCR instruction is not recommended for Clear interrupt flag (INTFLAG register).
2. Interrupt save status code is not shown in this example.
2.7.2
Timer1~3 Interrupt Function
2.7.2.1 Timer1 (PWM1) interrupt
At Timer mode, an underflow (00h FFh) in the TMR1 counter will set the flag bit T1P1IF (INTFLAG<0>). This
interrupt can be disabled by clearing T1P1IE bit (INTEN<0>).
At PWM mode, the end of each PWM period cycle to generate an interrupt. The interrupt rate can be adjusted by
PIR13:10 (PWM1CON <3:0>).
Figure 2.9: PWM Interrupt Waveform (Normal PWM or Sync PWM mode)
PWM1 Output
T1P1IF (PIR1<3:0>=1:4)
T1P1IF (PIR1<3:0>=1:5)
2.7.2.2 Timer2 interrupt
At Timer mode, an underflow (00h FFh) in the TMR2 counter will set the flag bit T2IF (INTFLAG<1>). This
interrupt can be disabled by clearing T2IE bit (INTEN<1>).
At PWM mode, TMR2 is PWM1 duty cycle counter. Not generate an interrupt.
2.7.2.3 Timer3 interrupt
An underflow (00h FFh) in the TMR3 counter will set the flag bit T3IF (INTFLAG<2>). This interrupt can be
disabled by clearing T3IE bit (INTEN<2>).
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2.7.3
ADC conversion completion interrupt
When the A/D conversion is completed, the flag bit ADCIF (INTFLAG <6>) will be set. And the ADCIF bit can be
cleared by software.
This interrupt can be disabled by clearing ADCIE bit (INTEN<6>).
2.8 Analog to Digital Converter (ADC)
This analog to digital converter has 11 channels 10bits (8+2) resolution. The ADC is controlled by three control
register, ADCON1, ADCON2, and ADCON3.
Example 2.8: Analog to Digital Conversion (Channel0 AD conversion)
Address
NA
Code
#include
<8P73B.ASH>
…
n
BTRSC
GOTO
MOVIA
MOVAR
MOVIA
MOVAR
MOVIA
MOVAR
MOVIA
MOVAR
BSR
BTRSS
GOTO
MOVR
MOVAR
MOVR
MOVAR
…
ADCON1,ADCEN_B
n+1
n+2
$-1
0xBF
;Make Sure no ADC is processing
;Clear ADCIF flag(Note)
n+3
INTFLAG
0x00
ADCON1
0x03
n+4
n+5
;Select ADC Channel 0 (IOA0) conversion
;Set AD conversion rate: System clock / 128
n+6
n+7
n+8
ADCON2
0x01
n+9
ADCON3
ADCON1,ADCEN_B
INTFLAG,ADCIF_B
$-1
;Set AN0 analog input
;ADC conversion start
n+10
n+11
n+12
n+13
n+14
n+15
n+16
;Wait AD end of conversion
;Read ADC high byte data
ADDATH,A
…
ADDATL,A
…
;Read ADC low byte data
Note : BCR instruction is not recommended for Clear interrupt flag (INTFLAG register).
2.9 Oscillator Configurations
FM8P73B can be operated in five different combinations of oscillator modes. Users can program configuration
word (FOSC) to select the appropriate modes. The five different system clock modes are combination of the
following oscillators:
LF: Low Frequency Crystal Oscillator
XT: Crystal/Resonator Oscillator
HF: High Frequency Crystal/Resonator Oscillator
ERC: External Resistor/ Voltage Controlled Oscillator
IRC: Internal Resistor/Capacitor Oscillator
In LF, XT, or HF modes, a crystal or ceramic resonator in connected to the OSCI and OSCO pins to establish
oscillation. When in LF, XT, or HF modes, the devices can have an external clock source drive the OSCI pin.
The ERC device option offers additional cost savings for timing insensitive applications. The RC oscillator
frequency is a function of the supply voltage, the resistor (Rext) and capacitor (Cext), the operating temperature,
and the process parameter.
The IRC option offers largest cost savings for timing insensitive applications.
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Figure 2.10: HF, XT or LF Oscillator Modes (Crystal Operation or Ceramic Resonator)
FM8P73B
C1
OSCI
SLEEP
X`TAL
RS
R1
RF
OSCO
C2
Internal
Circuit
Figure 2.11: HF, XT or LF Oscillator Modes (External Clock Input Operation)
FM8P73B
OSCI
Clock from
External System
OSCO
Figure 2.12: ERC (External Resistor Controlled) Oscillator Mode
FM8P73B
Rext
OSCI
Internal
Circuit
Cext
/2, /4
OSCO
The typical oscillator frequency vs. external resistor is as following table
When Cext = 0.01uf (103)
5V
3V
Frequency
Rext
4.3M
210K
108K
56K
Frequency
32 KHz
Rext
3.6M
238K
116K
59K
32 KHz
500 KHz
1.0 MHz
2.0 MHz
4.0 MHz
8.0 MHz
12.0 MHz
500 KHz
1.0 MHz
2.0 MHz
4.0 MHz
8.0 MHz
12.0 MHz
30K
30K
16K
16K
11K
11K
Note: Values are provided for design reference only.
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FM8P73B
Figure 2.13: IRC Oscillator Mode (Internal R, Internal C Oscillator)
FM8P73B
IOB5
Internal
Circuit
C
IOB4
2.10 Configuration Words
Table 2.3: Configuration Words
Name
Description
Oscillator Selection Bit
IRC(4MHz) mode (default)
ERC mode
Fosc
HF crystal mode
XT crystal mode
LF crystal mode
Note: See Table 2.4 for detail description.
Watchdog Timer Enable Bit
WDT enabled (default)
WDT disabled
WDTEN
LVDT
Low Voltage Detector Selection Bit
LVDT Disable (default)
LVDT = 2.0V
LVDT = 2.3V
LVDT = 3.5V
IOB3/RSTB Pin Selection Bit
RSTB pin is selected (default)
IOB3 pin is selected
RSTBIN
PWRT
Power On Reset time Selection Bit
20ms is selected (default)
5ms is selected
Instruction Period Selection Bit
four oscillator periods (4T) (default)
two oscillator periods (2T)
IOB4/OSCO Pin Selection Bit
OSCO pin is selected (default)
IOB4 pin is selected
OSCD
OSCOUT
PROTECT
Code Protection Bit
NO, EPROM code protection off (default)
YES, EPROM code protection on
Table 2.4: Selection of IOB5/OSCI and IOB4/OSCO Pin
Mode of oscillation
IRC
IOB5/OSCI
Force to IOB5
Force to OSCI
Force to OSCI
IOB4/OSCO
Force to IOB4
ERC
IOB4/OSCO selected by OSCOUT bit
Force to OSCO
HF, XT, LF
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EELING
FM8P73B
3.0 INSTRUCTION SET
Mnemonic,
Operands
Status
Cycles
Description
Operation
0 R<b>
Affected
BCR
R, bit Clear bit in R
R, bit Set bit in R
1
1
-
-
-
-
-
BSR
1 R<b>
BTRSC
BTRSS
NOP
R, bit Test bit in R, Skip if Clear
R, bit Test bit in R, Skip if Set
No Operation
Skip if R<b> = 0
Skip if R<b> = 1
No operation
1/2(1)
1/2(1)
1
00h WDT,
00h WDT prescaler
00h WDT,
̅̅̅̅ ̅̅̅̅
CLRWDT
Clear Watchdog Timer
1
TO, PD
̅̅̅̅ ̅̅̅̅
SLEEP
Go into power-down mode
Return from subroutine
Return from interrupt, set GIE bit
Clear ACC
1
2
2
TO, PD
00h WDT prescaler
RETURN
RETFIE
Top of Stack PC
-
-
Top of Stack PC,
1 GIE
CLRA
CLRR
MOVAR
MOVR
DECR
00h ACC
00h R
1
1
1
1
1
Z
Z
-
R
R
Clear R
Move ACC to R
ACC R
R dest
R, d Move R
Z
Z
R, d Decrement R
R - 1 dest
R - 1 dest,
Skip if result = 0
DECRSZ
INCR
R, d Decrement R, Skip if 0
R, d Increment R
1/2(1)
1
-
Z
-
R + 1 dest
R + 1 dest,
Skip if result = 0
INCRSZ
R, d Increment R, Skip if 0
1/2(1)
ADDAR
SUBAR
ANDAR
IORAR
XORAR
COMR
R, d Add ACC and R
R + ACC dest
R - ACC dest
ACC and R dest
ACC or R dest
R xor ACC dest
1
1
1
1
1
1
C, DC, Z
R, d Subtract ACC from R
R, d AND ACC with R
C, DC, Z
Z
Z
Z
Z
R, d Inclusive OR ACC with R
R, d Exclusive OR ACC with R
R, d Complement R
ꢀ
R dest
R<7> C,
RLR
R, d Rotate left R through Carry
R<6:0> dest<7:1>,
C dest<0>
1
C
C dest<7>,
RRR
R, d Rotate right R through Carry
R, d Swap R
R<7:1> dest<6:0>,
R<0> C
1
1
C
-
R<3:0> dest<7:4>,
R<7:4> dest<3:0>
SWAPR
MOVIA
ANDIA
IORIA
I
I
I
I
Move Immediate to ACC
AND Immediate with ACC
OR Immediate with ACC
Exclusive OR Immediate to ACC
I ACC
1
1
1
1
-
ACC and I ACC
ACC or I ACC
ACC xor I ACC
Z
Z
Z
XORIA
I ACC,
RETIA
CALL
I
I
Return, place Immediate in ACC
Call subroutine
2
2
-
-
Top of Stack PC
PC + 1 Top of Stack,
I PC<10:0>
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FM8P73B
Mnemonic,
Operands
GOTO
Status
Cycles
Description
Operation
I PC<10:0>
Affected
I
Unconditional branch
2
-
Note: 1. 2 cycles for skip, else 1 cycle.
2. bit : Bit address within an 8-bit register R
R : Register address (00h to 6Fh)
I : Immediate data
ACC : Accumulator
d : Destination select;
=0 (store result in ACC)
=1 (store result in file register R)
dest : Destination
PC : Program Counter
WDT : Watchdog Timer Counter
GIE : Global interrupt enable bit
̅̅̅̅
TO : Time-out bit
̅̅̅̅
PD : Power-down bit
C : Carry bit
DC : Digital carry bit
Z : Zero bit
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FM8P73B
ADDAR
Add ACC and R
Syntax:
ADDAR R, d
Operands:
0
d
R
[0,1]
0x6F
Operation:
ACC + R dest
Status Affected:
Description:
C, DC, Z
Add the contents of the ACC register and register ‘R’. If ‘d’ is 0 the result is stored in the
ACC register. If ‘d’ is ‘1’ the result is stored back in register ‘R’.
1
Cycles:
ANDAR
Syntax:
AND ACC and R
ANDAR R, d
Operands:
0
d
R
[0,1]
0x6F
Operation:
ACC and R dest
Status Affected:
Description:
Z
The contents of the ACC register are AND’ed with register ‘R’. If ‘d’ is 0 the result is stored
in the ACC register. If ‘d’ is ‘1’ the result is stored back in register ‘R’.
1
Cycles:
ANDIA
AND Immediate with ACC
Syntax:
ANDIA I
Operands:
Operation:
Status Affected:
Description:
0
I
0xFF
ACC AND I ACC
Z
The contents of the ACC register are AND’ed with the 8-bit immediate ‘I’. The result is
placed in the ACC register.
1
Cycles:
BCR
Clear Bit in R
Syntax:
Operands:
BCR R, b
0
0
R
b
0x6F
7
Operation:
Status Affected:
Description:
Cycles:
0 R<b>
None
Clear bit ‘b’ in register ‘R’.
1
BSR
Set Bit in R
Syntax:
Operands:
BSR R, b
0
0
R
b
0x6F
7
Operation:
Status Affected:
Description:
Cycles:
1 R<b>
None
Set bit ‘b’ in register ‘R’.
1
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FM8P73B
BTRSC
Test Bit in R, Skip if Clear
Syntax:
BTRSC R, b
Operands:
0
0
R
b
0x6F
7
Operation:
Skip if R<b> = 0
Status Affected:
Description:
None
If bit ‘b’ in register ‘R’ is 0 then the next instruction is skipped.
If bit ‘b’ is 0 then next instruction fetched during the current instruction execution is
discarded, and a NOP is executed instead making this a 2-cycle instruction.
1/2
Cycles:
BTRSS
Test Bit in R, Skip if Set
Syntax:
BTRSS R, b
Operands:
0
0
R
b
0x6F
7
Operation:
Skip if R<b> = 1
Status Affected:
Description:
None
If bit ‘b’ in register ‘R’ is ‘1’ then the next instruction is skipped.
If bit ‘b’ is ‘1’, then the next instruction fetched during the current instruction execution, is
discarded and a NOP is executed instead, making this a 2-cycle instruction.
1/2
Cycles:
CALL
Subroutine Call
Syntax:
CALL I
Operands:
Operation:
0
I
0x3FF
PC + 1 Top of Stack,
I PC<9:0>
Status Affected:
Description:
None
Subroutine call. First, return address (PC+1) is pushed onto the stack. The 10-bit
immediate address is loaded into PC bits <9:0>.
2
Cycles:
CLRA
Clear ACC
Syntax:
CLRA
Operands:
Operation:
None
00h ACC;
1 Z
Status Affected:
Description:
Cycles:
Z
The ACC register is cleared. Zero bit (Z) is set.
1
CLRR
Clear R
Syntax:
CLRR R
Operands:
Operation:
0
R
0x6F
00h R;
1 Z
Status Affected:
Description:
Cycles:
Z
The contents of register ‘R’ are cleared and the Z bit is set.
1
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FM8P73B
CLRWDT
Clear Watchdog Timer
Syntax:
CLRWDT
Operands:
Operation:
None
00h WDT;
̅̅̅̅
1 TO;
̅̅̅̅
1 PD
̅̅̅̅ ̅̅̅̅
Status Affected:
Description:
Cycles:
TO,PD
̅̅̅̅
̅̅̅̅
The CLRWDT instruction resets the WDT. The status bitsTO and PD will be set.
1
COMR
Complement R
Syntax:
COMR R, d
Operands:
0
d
R
[0,1]
0x6F
ꢀ
Operation:
R dest
Status Affected:
Description:
Z
The contents of register ‘R’ are complemented. If ‘d’ is 0 the result is stored in the ACC
register. If ‘d’ is 1 the result is stored back in register ‘R’.
1
Cycles:
DECR
Decrement R
Syntax:
Operands:
DECR R, d
0
d
R
[0,1]
0x6F
Operation:
R - 1 dest
Status Affected:
Description:
Z
Decrement of register ‘R’. If ‘d’ is 0 the result is stored in the ACC register. If ‘d’ is 1 the
result is stored back in register ‘R’.
1
Cycles:
DECRSZ
Syntax:
Decrement R, Skip if 0
DECRSZ R, d
Operands:
0
d
R
[0,1]
0x6F
Operation:
R - 1 dest; skip if result =0
Status Affected:
Description:
None
The contents of register ‘R’ are decrement. If ‘d’ is 0 the result is placed in the ACC register.
If ‘d’ is 1 the result is stored back in register ’R’.
If the result is 0, the next instruction, which is already fetched, is discarded and a NOP is
executed instead and making it a two-cycle instruction.
1/2
Cycles:
GOTO
Unconditional Branch
Syntax:
GOTO I
Operands:
Operation:
Status Affected:
Description:
Cycles:
0
I
0x3FF
I PC<9:0>
None
GOTO is an unconditional branch. The 10-bit immediate value is loaded into PC bits <9:0>.
2
Web site: http://www.feeling-teccom.tw
Rev1.0 Nov 20, 2013
P.40/FM8P73B
EELING
FM8P73B
INCR
Increment R
Syntax:
INCR R, d
Operands:
0
d
R
[0,1]
0x6F
Operation:
R + 1 dest
Status Affected:
Description:
Z
The contents of register ‘R’ are increment. If ‘d’ is 0 the result is placed in the ACC register.
If ‘d’ is 1 the result is stored back in register ‘R’.
1
Cycles:
INCRSZ
Syntax:
Increment R, Skip if 0
INCRSZ R, d
Operands:
0
d
R
[0,1]
0x6F
Operation:
R + 1 dest, skip if result = 0
Status Affected:
Description:
None
The contents of register ‘R’ are increment. If ‘d’ is 0 the result is placed in the ACC register.
If ‘d’ is the result is stored back in register ‘R’.
If the result is 0, then the next instruction, which is already fetched, is discarded and a NOP
is executed instead and making it a two-cycle instruction.
1/2
Cycles:
IORAR
OR ACC with R
Syntax:
IORAR R, d
Operands:
0
d
R
[0,1]
0x6F
Operation:
ACC or R dest
Status Affected:
Description:
Z
Inclusive OR the ACC register with register ‘R’. If ‘d’ is 0 the result is placed in the ACC
register. If ‘d’ is 1 the result is placed back in register ‘R’.
1
Cycles:
IORIA
OR Immediate with ACC
Syntax:
IORIA I
Operands:
Operation:
Status Affected:
Description:
0
I
0xFF
ACC or I ACC
Z
The contents of the ACC register are OR’ed with the 8-bit immediate ‘I’. The result is placed
in the ACC register.
1
Cycles:
MOVAR
Move ACC to R
Syntax:
MOVAR R
Operands:
Operation:
Status Affected:
Description:
Cycles:
0
R
0x6F
ACC R
None
Move data from the ACC register to register ‘R’.
1
Web site: http://www.feeling-teccom.tw
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P.41/FM8P73B
EELING
FM8P73B
MOVIA
Move Immediate to ACC
Syntax:
MOVIA I
Operands:
Operation:
Status Affected:
Description:
Cycles:
0
I
0xFF
I ACC
None
The 8-bit immediate ‘I’ is loaded into the ACC register. The don’t cares will assemble as 0s.
1
MOVR
Move R
Syntax:
MOVR R, d
Operands:
0
d
R
[0,1]
0x6F
Operation:
R dest
Status Affected:
Description:
Z
The contents of register ‘R’ is moved to destination ‘d’. If ‘d’ is 0, destination is the ACC
register. If ‘d’ is 1, the destination is file register ‘R’. ‘d’ is 1 is useful to test a file register
since status flag Z is affected.
1
Cycles:
NOP
No Operation
NOP
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
None
No operation
None
No operation.
1
RETFIE
Return from Interrupt, Set ‘GIE’ Bit
Syntax:
RETFIE
Operands:
Operation:
None
Top of Stack PC
1 GIE
Status Affected:
Description:
None
The program counter is loaded from the top of the stack (the return address). The ‘GIE’ bit
is set to 1. This is a two-cycle instruction.
2
Cycles:
RETIA
Return with Immediate in ACC
Syntax:
RETIA I
Operands:
Operation:
0
I
0xFF
I ACC;
Top of Stack PC
Status Affected:
Description:
None
The ACC register is loaded with the 8-bit immediate ‘I’. The program counter is loaded from
the top of the stack (the return address). This is a two-cycle instruction.
2
Cycles:
Web site: http://www.feeling-teccom.tw
Rev1.0 Nov 20, 2013
P.42/FM8P73B
EELING
FM8P73B
RETURN
Return from Subroutine
Syntax:
RETURN
Operands:
None
Operation:
Status Affected:
Description:
Top of Stack PC
None
The program counter is loaded from the top of the stack (the return address). This is a two-
cycle instruction.
2
Cycles:
RLR
Rotate Left R through Carry
Syntax:
Operands:
RLR R, d
0
d
R
[0,1]
0x6F
Operation:
R<7> C;
R<6:0> dest<7:1>;
C dest<0>
Status Affected:
Description:
C
The contents of register ‘R’ are rotated left one bit to the left through the Carry Flag. If ‘d’ is
0 the result is placed in the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’.
1
Cycles:
RRR
Rotate Right R through Carry
Syntax:
Operands:
RRR R, d
0
d
R
[0,1]
0x6F
Operation:
C dest<7>;
R<7:1> dest<6:0>;
R<0> C
Status Affected:
Description:
C
The contents of register ‘R’ are rotated one bit to the right through the Carry Flag. If ‘d’ is 0
the result is placed in the ACC register. If ‘d’ is 1 the result is placed back in register ‘R’.
1
Cycles:
SLEEP
Enter SLEEP Mode
SLEEP
Syntax:
Operands:
Operation:
None
00h WDT;
̅̅̅̅
1 TO;
̅̅̅̅
0 PD
̅̅̅̅ ̅̅̅̅
Status Affected:
Description:
TO, PD
̅̅̅̅
̅̅̅̅
Time-out status bit (TO) is set. The power-down status bit (PD) is cleared. The WDT is
cleared.
The processor is put into SLEEP mode.
1
Cycles:
Web site: http://www.feeling-teccom.tw
Rev1.0 Nov 20, 2013
P.43/FM8P73B
EELING
FM8P73B
SUBAR
Subtract ACC from R
Syntax:
SUBAR R, d
Operands:
0
d
R
[0,1]
0x6F
Operation:
R - ACC dest
Status Affected:
Description:
C, DC, Z
Subtract (2’s complement method) the ACC register from register ‘R’. If ‘d’ is 0 the result is
stored in the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’.
1
Cycles:
SWAPR
Syntax:
Swap nibbles in R
SWAPR R, d
Operands:
0
d
R
[0,1]
0x6F
Operation:
R<3:0> dest<7:4>;
R<7:4> dest<3:0>
Status Affected:
Description:
None
The upper and lower nibbles of register ‘R’ are exchanged. If ‘d’ is 0 the result is placed in
ACC register. If ‘d’ is 1 the result in placed in register ‘R’.
1
Cycles:
XORAR
Syntax:
Exclusive OR ACC with R
XORAR R, d
Operands:
0x6F
d0R[0,1]
Operation:
ACC xor R dest
Status Affected:
Description:
Z
Exclusive OR the contents of the ACC register with register ’R’. If ‘d’ is 0 the result is stored
in the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’.
1
Cycles:
XORIA
Exclusive OR Immediate with ACC
Syntax:
XORIA I
Operands:
Operation:
Status Affected:
Description:
0
I
0xFF
ACC xor I ACC
Z
The contents of the ACC register are XOR’ed with the 8-bit immediate ‘I’. The result is
placed in the ACC register.
1
Cycles:
Web site: http://www.feeling-teccom.tw
Rev1.0 Nov 20, 2013
P.44/FM8P73B
EELING
FM8P73B
4.0 ABSOLUTE MAXIMUM RATINGS
Ambient Operating Temperature
Store Temperature
-40℃ to +85℃
-65℃ to +150℃
0V to +6.0V
DC Supply Voltage (Vdd)
Input Voltage with respect to Ground (Vss)
-0.3V to (Vdd + 0.3)V
5.0 OPERATING CONDITIONS
DC Supply Voltage
+2.2V to +5.5V
Operating Temperature
-40℃ to +85℃
Web site: http://www.feeling-teccom.tw
Rev1.0 Nov 20, 2013
P.45/FM8P73B
EELING
FM8P73B
6.0 ELECTRICAL CHARACTERISTICS
6.1 ELECTRICAL CHARACTERISTICS of FM8P73B
Ta=25℃
Under Operating Conditions, at four clock instruction cycles and WDT & LVDT are disabled
Sym
Description
Conditions
HF mode, Vdd=5V, Fcpu=Fosc/2
HF mode, Vdd=3V, Fcpu=Fosc/2
XT mode, Vdd=5V, Fcpu=Fosc/2
XT mode, Vdd=3V, Fcpu=Fosc/2
LF mode, Vdd=5V, Fcpu=Fosc/2
LF mode, Vdd=3V, Fcpu=Fosc/2
ERC mode, Vdd=5V, Fcpu=Fosc/2
ERC mode, Vdd=3V, Fcpu=Fosc/2
HV mode, Vdd=5V
Min.
Typ.
Max.
20
Unit
FHF
X’tal oscillation range
MHz
15
10
FXT
FLF
X’tal oscillation range
X’tal oscillation range
MHz
KHZ
MHz
%
10
4000
1000
15
FERC RC oscillation range
7
-3
-3
+3
FIRC
IRC Calibration range
Input high voltage
LV mode, Vdd=3V
+15
With schmitter
VIH
I/O ports
0.7Vdd
0.8Vdd
Vdd
Vdd
V
V
RSTB pin
With schmitter
VIL
Input low voltage
I/O ports
Vss
Vss
0.2Vdd
RSTB pin
0.2Vdd
Vin = 5V, Vdd=5V
1
1
IIL
Input Leakage Current
IO Drive Current
uA
Vin = 0V, Vdd=5V
VOH =4.5V, Vdd = 5V
VOH =4V, Vdd = 5V
7.5
IOH
mA
14.5
13.5
VOL =0.5V, Vdd = 5V
IOL
IO Sink Current
Pull-high resister
WDT current
mA
KΩ
uA
VOL =0.75V, Vdd = 5V
Input pin at Vss, vdd=5V
Input pin at Vss, vdd=3V
Vdd=5V
18.5
140
280
11
70
210
420
RPH
IWDT
140
Vdd=3V
2
Vdd=3V
22
TWDT WDT period
mS
Vdd=5V
19
LVDT = 3.5V, vdd=5V
LVDT = 2.3V, vdd=5V
LVDT = 2.3V, vdd=3V
LVDT = 2.0V, vdd=5V
LVDT = 2.0V, vdd=3V
LVDT = 3.5V
2.5
3
ILVDT
LVDT current
0.6
2.5
0.5
3.6
2.4
2.1
uA
V
3.4
2.2
1.9
0
3.8
2.6
2.3
Vdd
10
VLVDT LVDT voltage
LVDT = 2.3V
LVDT = 2.0V
VAD
RAD
A/D input Voltage
Resolution
V
Bits
A/D Differential Non-
Linear
DNL
INL
2
5
LSB
LSB
A/D Integral Non-
Linear
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Rev1.0 Nov 20, 2013
P.46/FM8P73B
EELING
FM8P73B
Sym
IADC
TAD
Description
A/D Operation Current
A/D clock period
Conditions
Min.
8
Typ.
500
100
Max.
Unit
Vdd = 5V, Fcpu=Fosc/4
Vdd = 3V, Fcpu=Fosc/4
uA
us
TADC A/D Conversion Time
TADCS A/D Sampling Time
20
8
TAD
TAD
Sleep mode, Vdd=5V, WDT enable,
LVDT off
11
Sleep mode, Vdd=5V, WDT disable,
LVDT off
1
1
ISB
Power down current
uA
Sleep mode, Vdd=3V, WDT enable,
LVDT off
2
Sleep mode, Vdd=3V, WDT disable,
LVDT off
IDD1
IDD2
IDD3
IDD4
Operating current
Operating current
Operating current
Operating current
IRC mode, vdd=5V, 4 clock instruction
IRC mode, vdd=5V, 2 clock instruction
IRC mode, vdd=3V, 4 clock instruction
IRC mode, vdd=3V, 2 clock instruction
0.95
1.4
mA
mA
mA
mA
0.5
0.7
HF mode, vdd=5V, 4 clock instruction
20MHz
IDD5
IDD6
IDD7
Operating current
Operating current
Operating current
mA
mA
mA
4
HF mode, vdd=5V, 2 clock instruction
20MHz
5
HF mode, vdd=3V, 4 clock instruction
20MHZ
1.6
XT mode, Vdd=5V, 4 clock instruction
IDD8
Operating current
Operating current
10MHz
2.3
1.2
mA
mA
4MHz
XT mode, Vdd=5V, 2 clock instruction
IDD9
10MHz
3.5
1.6
4MHz
XT mode, Vdd=3V, 4 clock instruction
IDD10 Operating current
10MHz
1
mA
mA
4MHz
0.5
XT mode, Vdd=3V, 2 clock instruction
IDD11
Operating current
Operating current
10MHz
1.4
0.7
4MHz
LF mode, Vdd=5V, 4 clock instruction
IDD
uA
uA
uA
uA
32KHz
32
36
8
LF mode, Vdd=5V, 2 clock instruction
IDD12 Operating current
IDD13 Operating current
IDD14 Operating current
32KHz
LF mode, Vdd=3V, 4 clock instruction
32KHz
LF mode, Vdd=3V, 2 clock instruction
32KHz
10
HF mode, Clock source = FOSC x2
16MHz
8MHz
4MHz
4.3
2.5
2.0
VPWM Operating voltage
V
Web site: http://www.feeling-teccom.tw
Rev1.0 Nov 20, 2013
P.47/FM8P73B
EELING
FM8P73B
6.2 ELECTRICAL CHARACTERISTICS Charts of FM8P73B
6.2.1
Internal 4MHz RC vs. Temperature
6.00%
4.00%
2.00%
0.00%
Avg-5V
Avg-3V
-40 -30 -20 -10
0
10 20 25 30 40 50 60 70 80 90 100 110 120 125
-2.00%
-4.00%
-6.00%
-8.00%
-10.00%
Temperature
Note: Curves are for design reference only.
6.2.2
Internal 4MHz RC vs. Supply Voltage (Ta=25℃)
10.00%
8.00%
6.00%
4.00%
2.00%
0.00%
4M HV
4M LV
2
2.2 2.4 2.6 2.8
3
3.2 3.4 3.6 3.8
Voltage
4
4.2 4.4 4.6 4.8
5
5.2 5.4 5.6 5.8
6
-2.00%
-4.00%
CAUTION: Less than 2.8V will exceed 3% limit.
Note: Curves are for design reference only.
6.2.3
Low Voltage Detect (LVDT=2.1V) vs. Temperature
3.00
2.50
2.00
1.50
1.00
0.50
0.00
Avg-2.1V
-40 -30 -20 -10
0
10 20 25 30 40 50 60 70 80 90 100 110 120 125
Temperature
CAUTION: The LVDT 2.1V option can only support temperature range between -40~50℃
Note: Curves are for design reference only.
Web site: http://www.feeling-teccom.tw
Rev1.0 Nov 20, 2013
P.48/FM8P73B
EELING
FM8P73B
6.2.4
Low Voltage Detect (LVDT=2.3V) vs. Temperature
3.00
Avg-2.3V
2.50
2.00
1.50
1.00
0.50
0.00
-40 -30 -20 -10
0
10 20 25 30 40 50 60 70 80 90 100 110 120 125
Temperature
Note: Curves are for design reference only.
6.2.5
Low Voltage Detect (LVDT=3.5V) vs. Temperature
4.50
4.00
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0.00
Avg-3.5V
-40 -30 -20 -10
0
10 20 25 30 40 50 60 70 80 90 100 110 120 125
Temperature
Note: Curves are for design reference only.
6.2.6 WDT 20mS Reset time vs. Temperature
45.00
40.00
35.00
30.00
25.00
20.00
15.00
10.00
5.00
Avg-5V
Avg-3V
0.00
-40 -30 -20 -10
0
10 20 25 30 40 50 60 70 80 90 100 110 120 125
Temperature
Note: Curves are for design reference only.
Web site: http://www.feeling-teccom.tw
Rev1.0 Nov 20, 2013
P.49/FM8P73B
EELING
FM8P73B
6.2.7 WDT 20mS Reset time vs. Supply Voltage (Ta=25℃)
30.00
25.00
20.00
15.00
10.00
5.00
Avg-20mS
0.00
2
2.2 2.4 2.6 2.8
3
3.2 3.4 3.6 3.8
Voltage
4
4.2 4.4 4.6 4.8
5
5.2 5.4 5.6 5.8
6
Note: Curves are for design reference only.
Web site: http://www.feeling-teccom.tw
Rev1.0 Nov 20, 2013
P.50/FM8P73B
EELING
FM8P73B
7.0 PACKAGE DIMENSION
7.1 14-PIN PDIP 300mil
D
14
8
7
1
0.100typ.
0.018typ.
0.060typ.
Dimension In Inches
Symbols
Min
-
Nom
-
Max
0.210
-
A
A1
A2
D
0.015
0.125
0.735
-
0.130
0.750
0.300 BSC.
0.250
0.130
0.355
7°
0.135
0.775
E
E1
L
0.245
0.115
0.335
0°
0.255
0.150
0.375
15°
eB
θ°
Web site: http://www.feeling-teccom.tw
Rev1.0 Nov 20, 2013
P.51/FM8P73B
EELING
FM8P73B
7.2 14-PIN SOP 150mil
14
8
o
5
4
x
5
1
0
.
0
1
7
“
A
C
D
e
0.004max
B
GAUGE PLANE
SEATING PLANE
o
£
L
DETAIL : A
Dimension In Inches
Symbols
Min
Nom
0.064
-
Max
0.068
0.010
0.020
0.0098
0.344
0.157
-
A
A1
B
0.058
0.004
0.013
0.016
0.008
0.341
0.154
0.050
0.236
0.025
-
C
D
E
0.0075
0.336
0.150
-
e
H
L
0.228
0.015
0°
0.244
0.050
8°
θ°
Web site: http://www.feeling-teccom.tw
Rev1.0 Nov 20, 2013
P.52/FM8P73B
EELING
FM8P73B
7.3 16-PIN PDIP 300mil
Dimension In Inches
Symbols
Min
-
Nom
-
Max
0.210
-
A
A1
A2
D
0.015
0.125
0.735
-
0.130
0.755
0.300 BSC
0.250
0.130
0.355
7°
0.135
0.775
E
E1
L
0.245
0.115
0.335
0°
0.255
0.150
0.375
15°
eB
θ°
Web site: http://www.feeling-teccom.tw
Rev1.0 Nov 20, 2013
P.53/FM8P73B
EELING
FM8P73B
7.4 16-PIN SOP 150mil
Dimension In Inches
Symbols
Min
Max
0.069
0.010
0.065
0.394
0.157
0.244
0.050
8°
A
A1
A2
D
0.053
0.004
0.049
0.386
0.150
0.228
0.016
0°
E
H
L
θ°
Web site: http://www.feeling-teccom.tw
Rev1.0 Nov 20, 2013
P.54/FM8P73B
EELING
FM8P73B
7.5 18-PIN PDIP 300mil
D
C
TOP E-PIN INDENT £ 0.079
BOTTOM E-PIN INDENT £ 0.118
0.727
e
B
B1
D1
Dimension In Inches
Symbols
Min
Nom
-
Max
0.180
-
A
A1
A2
B
-
0.005
-
-
0.130
0.018
0.060
0.010
0.904
0.022
-
0.140
0.022
0.070
0.013
0.910
0.027
0.325
0.262
-
0.014
0.050
0.008
0.894
0.017
0.300
0.252
-
B1
C
D
D1
E
E1
e
0.256
0.100
-
L
0.125
-
Web site: http://www.feeling-teccom.tw
Rev1.0 Nov 20, 2013
P.55/FM8P73B
EELING
FM8P73B
7.6 18-PIN SOP 300mil
View “
A
D
View “
A
7o(4x)
e
B
£
L
Dimension In Inches
Symbols
Min
0.093
0.04
-
Nom
0.098
-
Max
0.104
0.012
-
A
A1
A2
B
0.091
0.016
0.009
-
0.013
0.007
0.447
0.291
-
0.020
0.011
0.463
0.299
-
C
D
E
0.295
0.050
0.406
0.032
-
e
H
0.394
0.015
0°
0.419
0.050
8°
L
θ°
Web site: http://www.feeling-teccom.tw
Rev1.0 Nov 20, 2013
P.56/FM8P73B
EELING
FM8P73B
8.0 PACKAGE IR Re-flow Soldering Curve
250 5℃
10 1 sec
150 10℃
90 30 sec
2 ~ 5℃/ sec
2 ~ 5℃/ sec
Time
9.0 ORDERING INFORMATION
OTP Type MCU
FM8P73BAP
FM8P73BAD
FM8P73BBP
FM8P73BBD
FM8P73BCP
FM8P73BCD
FM8P73BDP
FM8P73BDD
Package Type
Pin Count
Package Size
PDIP
SOP
PDIP
SOP
PDIP
SOP
PDIP
SOP
16
16
14
14
18
18
16
16
300 mil
150 mil
300 mil
150 mil
300 mil
300 mil
300 mil
150 mil
Web site: http://www.feeling-teccom.tw
Rev1.0 Nov 20, 2013
P.57/FM8P73B
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