FM8PE53MD [FEELING]
OTP-Based 8-Bit Microcontroller;
| 型号： | FM8PE53MD |
| 厂家： | 
Feeling Technology |
| 描述： | OTP-Based 8-Bit Microcontroller 微控制器 |
| 文件： | 总52页 (文件大小：2389K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EELING
FM8PE53M
OTP-Based 8-Bit Microconer
Devices Included in this Data Sheet:
FM8PE53M: OTP device
FEATURES
1K Word on chip OTP
49x8 bits on chip general purpose registers (SRAM)
8-bit wide data path
5-level deep hardware stack
Only 42 single word instructions
All instructions are single cycle except for program branches which are two-cycle
All OTP area GOTO instruction
All OTP area subroutine CALL instruction
Direct, indirect addressing modes for data accessing
8-bit real time clock/counter (Timer0) with 8-bit programmable pre-scaler
Internal Power-on Reset (POR)
Built-in Low Voltage Detector (LVD) for Brown-out Reset (BOR)
Power-up Reset Timer (PWRT) and Oscillator Start-up Timer(OST)
On chip Watchdog Timer (WDT) with internal oscillator for reliable operation and soft-ware watch-dog
enable/disable control
Two I/O ports IOA and IOB with independent direction control
Soft-ware I/O pull-high/pull-down or open-drain control
One internal interrupt source: Timer0 overflow; Two external interrupt source: INT pin, Port B input change
Wake-up from SLEEP by INT pin or Port B input change
Power saving SLEEP mode
Built-in 8MHZ, 4MHZ, 1MHZ, and 455KHZ internal RC oscillator
Programmable Code Protection
Selectable oscillator options:
- ERC: External Resistor/Capacitor Oscillator
- HF: High Frequency Crystal/Resonator Oscillator
- XT: Crystal/Resonator Oscillator
- LF: Low Frequency Crystal Oscillator
- IRC: Internal Resistor/Capacitor Oscillator
- ERIC: External Resistor/Internal Capacitor Oscillator
Operating voltage range: 2.0V to 5.5V
This datasheet contains on. Feeling Technology reserves the rights to modify the product specification without notice.
No liability is assumed as a rethis product. No rights under any patent accompany the sales of the product.
Web site: http://www.feeling-teom.tw
Rev 1.00.003 Mar 02, 2017
Page 1 of 52, FM8PE53M
EELING
FM8PE53M
GENERAL DESCRIPTION
The FM8PE53M is a low-cost, high speed, high noise immunity, OTP-based 8-bit CMOS microcontrollers. It
employs a RISC architecture with only 42 instructions. All instructions are single cycle except for program branches
which take two cycles. The easy to use and easy to remember instruction set reduces development time
significantly.
The FM8PE53M consists of Power-on Reset (POR), Brown-out Reset (BOR), Power-up Reset Timer (PWRT),
Oscillator Start-up Timer(OST), Watchdog Timer, OTP, SRAM, tristate I/O port, I/O pull-high/open-drain/pull-down
control, Power saving SLEEP mode, real time programmable clock/counter, Interrupt, Wake-up from SLEEP mode,
and Code Protection for OTP products. There are three oscillator configurations to choose from, including the
external clock input, external resistor RC oscillator and internal RC oscillator.
The FM8PE53M address 1K of program memory.
The FM8PE53M can directly or indirectly address its register files and data memory. All special function registers
including the program counter are mapped in the data memory.
BLOCK DIAGRAM
DATA BUS
Oscillator
Circuit
5-level
STACK
Control
Interrupt
Watchdog
Timer
Program
Counter
FSR
SRAM
PORTA
PORTB
Instruction
Decoder
ALU
OTP-ROM
Interrupt
Control
8-bit Timer0
Accumulator
Web site: http://www.feeling-techcom.tw
Rev 1.00.003 Mar 02, 2017
Page 2 of 52, FM8PE53M
EELING
FM8PE53M
PIN CONNECTION
PDIP, SOP
IOA0
IOB7
1
2
3
4
5
6
7
14 IOA1
13 IOA2
12 IOA3
11 VSS
IOB6
FM8PE53M
VDD
IOB5/OSCI
IOB4/OSCO
IOB3/RSTB
10 IOB0/INT
9
8
IOB1
IOB2/T0CKI
PIN DESCRIPTIONS
Name
I/O
I/O
Description
IOA0 ~ IOA3 as bi-direction I/O pin.
Software controlled pull-down.
IOA0 ~ IOA3
Bi-direction I/O pin with system wake-up function.
IOB0/INT
IOB1
I/O Software controlled pull-high/open-drain/pull-down.
External interrupt input.
Bi-direction I/O pin with system wake-up function.
I/O
Software controlled pull-high/open-drain/pull-down.
Bi-direction I/O pin with system wake-up function.
I/O Software controlled pull-high/open-drain/pull-down.
External clock input to Timer0.
IOB2/T0CKI
Input pin or open-drain output pin with system wake-up function.
System clear (RESET) input. Active low RESET to the device. Weak pull-high always
on if configured as RSTB.
Voltage on this pin must not exceed VDD, See IOB3 diagram for detail description.
Bi-direction I/O pin with system wake-up function (RCOUT optional in IRC/ERIC,
ERC mode).
IOB3/RSTB
IOB4/OSCO
I/O
I/O Software controlled pull-high/open-drain.
Oscillator crystal output (HF, XT, LF mode).
Outputs with the instruction cycle rate (RCOUT optional in IRC/ERIC, ERC mode).
Bi-direction I/O pin with system wake-up function (IRC mode).
Software controlled pull-high/open-drain.
Oscillator crystal input (HF, XT, LF mode).
IOB5/OSCI
I/O
External clock source input (ERIC, ERC mode).
Bi-direction I/O pin with system wake-up function.
Software controlled pull-high/open-drain.
IOB6 ~ IOB7
I/O
VDD
VSS
-
-
Positive supply.
Ground.
Legend: I=input, O=output, I/O=input/output
Web site: http://www.feeling-techcom.tw
Rev 1.00.003 Mar 02, 2017
Page 3 of 52, FM8PE53M
EELING
FM8PE53M
1.0 MEMORY ORGANIZATION
FM8PE53M memory is organized into program memory and data memory.
1.1 Program Memory Organization
The FM8PE53M has a 10-bit Program Counter capable of addressing a 1K program memory space.
The RESET vector for the FM8PE53M is at 0x3FF.
The H/W interrupt vector is at 0x008. And the S/W interrupt vector is at 0x002.
FM8PE53M supports all OTP area CALL/GOTO instructions without page.
Figure 1.1: Program Memory Map and STACK
0x3FF
Reset Vector
Stack 0~5
:
:
Program Counter
0x008 H/W Interrupt Vector
0x002 S/W Interrupt Vector
0x000
Web site: http://www.feeling-techcom.tw
Rev 1.00.003 Mar 02, 2017
Page 4 of 52, FM8PE53M
EELING
FM8PE53M
1.2 Data Memory Organization
Data memory is composed of Special Function Registers and General Purpose Registers.
The General-Purpose Registers are accessed either directly or indirectly through the FSR register.
The Special Function Registers are registers used by the CPU and peripheral functions to control the operation of
the device.
Table 1.1: Registers File Map for FM8PE53M
Address
0x00
Description
INDF
0x01
TMR0
0x02
PCL
N/A
OPTION
0x03
STATUS
0x04
FSR
0x05
0x06
PORTA
PORTB
0x05
0x06
IOSTA
IOSTB
0x07
General Purpose Register
0x08
PCON
0x09
WUCON
0x0A
PCHBUF
0x0B
PDCON
0x0C
0x0D
ODCON
PHCON
0x0E
INTEN
0x0F
INTFLAG
0x10 ~ 0x3F
General Purpose Registers
Table 1.2: The Registers Controlled by OPTION or IOST Instructions
Address
N/A (w)
0x05 (w)
0x06 (w)
Name
OPTION
IOSTA
IOSTB
B7
*
B6
B5
B4
B3
B2
B1
B0
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Port A I/O Control Register
Port B I/O Control Register
Table 1.3: Operational Registers Map
Address
Name
INDF
TMR0
PCL
STATUS
FSR
PORTA
PORTB
SRAM
B7
B6
B5
B4
B3
B2
B1
B0
C
0x00 (r/w)
0x01 (r/w)
0x02 (r/w)
0x03 (r/w)
0x04 (r/w)
0x05 (r/w)
0x06 (r/w)
0x07 (r/w)
0x08 (r/w)
0x09 (r/w)
0x0A (r/w)
0x0B (r/w)
0x0C (r/w)
0x0D (r/w)
0x0E (r/w)
Uses contents of FSR to address data memory (not a physical register)
8-bit real-time clock/counter
Low order 8 bits of PC
̅̅̅̅
TO
̅̅̅̅
PD
RST
*
Z
DC
*
Indirect data memory address pointer
IOA3
IOB3
IOA2
IOB2
IOA1
IOB1
IOA0
IOB0
IOB7
IOB6
IOB5
IOB4
General Purpose Register
PCON
WDTE
WUB7
-
EIS
WUB6
-
/PDB2
ODB6
/PHB6
*
LVDTE
WUB5
-
/PDB1
ODB5
/PHB5
*
*
WUB4
-
/PDB0
ODB4
/PHB4
*
*
WUB3
-
*
WUB2
-
/PDA2
ODB2
/PHB2
INTIE
INTIF
*
WUB1
*
WUB0
WUCON
PCHBUF
PDCON
ODCON
PHCON
INTEN
2 MSBs Buffer of PC
/PDA3
/PDA1
ODB1
/PHB1
PBIE
PBIF
/PDA0
ODB0
/PHB0
T0IE
T0IF
ODB7
/PHB7
GIE
*
-
0x0F (r/w) INTFLAG
-
-
-
-
Legend: - = unimplemented, read as ‘0’, * = unimplemented, read as ‘1’.
Web site: http://www.feeling-techcom.tw
Rev 1.00.003 Mar 02, 2017
Page 5 of 52, FM8PE53M
EELING
FM8PE53M
2.0 FUNCTIONAL DESCRIPTIONS
2.1 Operational Registers
2.1.1
INDF (Indirect Addressing Register)
Read/Write-POR
R/W-x
B7
R/W-x
B6
R/W-x
B5
R/W-x
B4
R/W-x
B3
R/W-x
B2
R/W-x
B1
R/W-x
B0
Address
0x00
Name
INDF
Uses contents of FSR to address data memory (not a physical register)
Legend: x = unknown, more bits’ default state, please refer to Table 2.2.
The INDF Register is not a physical register. Any instruction accessing the INDF register can actually access the
register pointed by FSR Register. Reading the INDF register itself indirectly (FSR=”0x00”) will read 0x00. Writing to
the INDF register indirectly results in a no-operation (although status bits may be affected).
The bits 5-0 of FSR register are used to select up to 64 registers (address: 0x00 ~ 0x3F).
Example 2.1: INDIRECT ADDRESSING
Register file 0x38 contains the value 0x10
Register file 0x39 contains the value 0x0A
Load the value 0x38 into the FSR Register
A read of the INDF Register will return the value of 0x10
Increment the value of the FSR Register by one (@FSR=0x39)
A read of the INDF register now will return the value of 0x0A.
Figure 2.1: Direct/Indirect Addressing
Direct Addressing
From opcode
Indirect Addressing
From FSR register 0
5
0
5
0x00
location select
addressing INDF register
location select
0x3F
Web site: http://www.feeling-techcom.tw
Rev 1.00.003 Mar 02, 2017
Page 6 of 52, FM8PE53M
EELING
FM8PE53M
2.1.2
TMR0 (Time Clock/Counter register)
Read/Write-POR
R/W-x
B7
R/W-x
B6
R/W-x
B5
R/W-x
B4
R/W-x
B3
R/W-x
B2
R/W-x
B1
R/W-x
B0
Address
0x01
Name
TMR0
8-bit real-time clock/counter
Note: more bits’ default state, please refer to Table 2.2.
The Timer0 is a 8-bit timer/counter. The clock source of Timer0 can come from the instruction cycle clock or by an
external clock source (T0CKI pin) defined by T0CS bit (OPTION<5>). If T0CKI pin is selected, the Timer0 is
increased by T0CKI signal rising/falling edge (selected by T0SE bit (OPTION<4>)).
The pre-scaler is assigned to Timer0 by clearing the PSA bit (OPTION<3>). In this case, the pre-scaler will be
cleared when TMR0 register is written with a value.
2.1.3
PCL (Low Bytes of Program Counter) & Stack
Read/Write-POR
R/W-1
B7
R/W-1
B6
R/W-1
B5
R/W-1
B4
R/W-1
B3
R/W-1
B2
R/W-1
B1
R/W-1
B0
Address
0x02
Name
PCL
Low order 8 bits of PC
Note: more bits’ default state, please refer to Table 2.2.
FM8PE53M device has a 10-bit wide Program Counter (PC) and five-level deep 10-bit hardware push/pop stack.
The low byte of PC is called the PCL register. This register is readable and writable. The high byte of PC is called
the PCH register. This register contains the PC<9:8> bits and is not directly readable or writable. All updates to the
PCH register go through the PCHBUF register. As a program instruction is executed, the Program Counter will
contain the address of the next program instruction to be executed. The PC value is increased by one, every
instruction cycle, unless an instruction changes the PC.
For a GOTO instruction, the PC<9:0> is provided by the GOTO instruction word. The PCL register is mapped to
PC<7:0>, and the PCHBUF register is not updated.
For a CALL instruction, the PC<9:0> is provided by the CALL instruction word. The next PC will be loaded (PUSHed)
onto the top of STACK. The PCL register is mapped to PC<7:0>, and the PCHBUF register is not updated.
For a RETIA, RETFIE, or RETURN instruction, the PC are updated (POPed) from the top of STACK. The PCL
register is mapped to PC<7:0>, and the PCHBUF register is not updated.
For any instruction where the PCL is the destination, the PC<7:0> is provided by the instruction word or ALU result.
However, the PC<9:8> will come from the PCHBUF<1:0> bits (PCHBUF PCH).
PCHBUF register is never updated with the contents of PCH.
Web site: http://www.feeling-techcom.tw
Rev 1.00.003 Mar 02, 2017
Page 7 of 52, FM8PE53M
EELING
FM8PE53M
Figure 2.2: Loading of PC in Different Situations
Situation 1: GOTO Instruction
PCH
PCL
9
8
-
7
-
0
PC
Opcode <9:0>
-
-
-
-
PCHBUF
Situation 2: CALL Instruction
STACK<9:0>
Opcode <9:0>
PCH
PCL
9
8
7
-
0
PC
-
-
-
-
-
PCHBUF
Situation 3: RETIA, RETFIE, or RETURN Instruction
PCH PCL
STACK<9:0>
9
8
7
0
PC
-
-
-
-
-
-
PCHBUF
Situation 4: Instruction with PCL as destination
PCH PCL
8
9
7
0
PC
ALU result <7:0>
Or Opcode <7:0>
PCHBUF<1:0>
-
-
-
-
-
-
PCHBUF
Note: PCHBUF is used only for instruction with PCL as destination for FM8PE53M.
Web site: http://www.feeling-techcom.tw
Rev 1.00.003 Mar 02, 2017
Page 8 of 52, FM8PE53M
EELING
FM8PE53M
2.1.4
STATUS (Status Register)
Read/Write-POR
R/W-0
B7
R/W-0
B6
R/W-0
B5
R-#
B4
̅̅̅̅
TO
R-#
B3
̅̅̅̅
PD
R/W-x
B2
R/W-x
B1
R/W-x
B0
Address
0x03
Name
STATUS
RST
Z
DC
C
Legend: x = unknown, # refer Table 2.3 for detail description, more bits’ default state, please refer to Table 2.2.
This register contains the arithmetic status of the ALU, the RESET status.
If the STATUS Register is the destination for an instruction that affects the Z, DC or C bits, then the write to these
̅̅̅̅
̅̅̅̅
three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits
are not writable. Therefore, the result of an instruction with the STATUS Register as destination may be different
than intended. For example, CLRR STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS
Register as 000u u1uu (where u = unchanged).
C:Carry/borrow bit.
ADDAR, ADDIA, ADCAR
= 0, No Carry occurred.
= 1, Carry occurred.
SUBAR, SUBIA, SBCAR
= 0, Borrow occurred.
= 1, No borrow occurred.
Note:A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRR, RLR)
instructions, this bit is loaded with either the high or low order bit of the source register.
DC:Half carry/half borrow bit
ADDAR, ADDIA, ADCAR
= 0, No Carry from the 4th low order bit of the result occurred.
= 1, Carry from the 4th low order bit of the result occurred.
SUBAR, SUBIA, SBCAR
= 0, Borrow from the 4th low order bit of the result occurred.
= 1, No Borrow from the 4th low order bit of the result occurred.
Z:Zero bit.
= 0, The result of a logic operation is not zero.
= 1, The result of a logic operation is zero.
̅̅̅̅
PD:Power down flag bit.
= 0, by the SLEEP instruction.
= 1, after power-up or by the CLRWDT instruction.
̅̅̅̅
TO:Time overflow flag bit.
= 0, a watch-dog time overflow occurred.
= 1, after power-up or by the CLRWDT or SLEEP instruction.
Bit6:Bit5:General purpose read/write bit.
RST:Bit for wake-up type.
= 0, Wake-up from other reset types.
= 1, Wake-up from SLEEP on Port B input change.
Web site: http://www.feeling-techcom.tw
Rev 1.00.003 Mar 02, 2017
Page 9 of 52, FM8PE53M
EELING
FM8PE53M
2.1.5
FSR (Indirect Data Memory Address Pointer)
Read/Write-POR
*
B7
*
*
B6
*
R/W-x
B5
R/W-x
B4
R/W-x
B3
R/W-x
B2
R/W-x
B1
R/W-x
B0
Address
0x04
Name
FSR
Indirect data memory address pointer
Legend: * = unimplemented, read as ‘1’, more bits’ default state, please refer to Table 2.2.
Bit5:Bit0:Select registers address in the indirect addressing mode. See 2.1.1 for detail description.
2.1.6
PORTA, PORTB (Port Data Registers)
Read/Write-POR
R/W-x
B7
R/W-x
B6
R/W-x
B5
R/W-x
B4
R/W-x
B3
R/W-x
B2
R/W-x
B1
R/W-x
B0
Address
0x05
Name
PORTA
IOA3
IOA2
IOA1
IOA0
Read/Write-POR
R/W-x
B7
R/W-x
B6
R/W-x
B5
R/W-x
B4
R/W-x
B3
R/W-x
B2
R/W-x
B1
R/W-x
B0
Address
0x06
Name
PORTB
IOB7
IOB6
IOB5
IOB4
IOB3
IOB2
IOB1
IOB0
Note: more bits’ default state, please refer to Table 2.2.
Reading the port (PORTA, PORTB register) reads the status of the pins independent of the pin’s input/output modes.
Writing to these ports will write to the port data latch.
PORTA is a 4-bit port data Register. Only the low order 4 bits are used (PORTA<3:0>). Bits 7-4 are general purpose
read/write bits.
IOA3:IOA0:PORTA I/O pin.
= 0, Port pin is low level.
= 1, Port pin is high level.
IOB7:IOB0:PORTB I/O pin.
= 0, Port pin is low level.
= 1, Port pin is high level.
Note: IOB3 is open-drain output only if IOSTB3 = 0. See 2.1.17 for detail description.
2.1.7
PCON (Power Control Register)
Read/Write-POR
R/W-1
B7
R/W-0
B6
R/W-1
B5
*
B4
*
*
B3
*
*
B2
*
*
B1
*
*
B0
*
Address
0x08
Name
PCON
WDTE
EIS
LVDTE
Legend: * = unimplemented, read as ‘1’, more bits’ default state, please refer to Table 2.2.
LVDTE:LVDT (low voltage detector) enable bit.
= 0, Disable LVDT.
= 1, Enable LVDT.
EIS:Define the function of IOB0/INT pin.
= 0,IOB0 (bi-directional I/O pin) is selected. The path of INT is masked.
= 1,INT (external interrupt pin) is selected. In this case, the I/O control bit of IOB0 must be set to “1”. The path
of Port B input change of IOB0 pin is masked by hardware, the status of INT pin can also be read by way
of reading PORTB.
Web site: http://www.feeling-techcom.tw
Rev 1.00.003 Mar 02, 2017
Page 10 of 52, FM8PE53M
EELING
FM8PE53M
WDTE:WDT (watch-dog timer) enable bit.
= 0, Disable WDT.
= 1, Enable WDT.
2.1.8
WUCON (Port B Input Change Interrupt/Wake-up Control Register)
Read/Write-POR
R/W-0
B7
R/W-0
B6
R/W-0
B5
R/W-0
B4
R/W-0
B3
R/W-0
B2
R/W-0
B1
R/W-0
B0
Address
0x09
Name
WUCON
WUB7
WUB6
WUB5
WUB4
WUB3
WUB2
WUB1
WUB0
Note: more bits’ default state, please refer to Table 2.2.
WUB0:= 0, Disable the input change interrupt/wake-up function of IOB0 pin.
= 1, Enable the input change interrupt/wake-up function of IOB0 pin.
WUB1:= 0, Disable the input change interrupt/wake-up function of IOB1 pin.
= 1, Enable the input change interrupt/wake-up function of IOB1 pin.
WUB2:= 0, Disable the input change interrupt/wake-up function of IOB2 pin.
= 1, Enable the input change interrupt/wake-up function of IOB2 pin.
WUB3:= 0, Disable the input change interrupt/wake-up function of IOB3 pin.
= 1, Enable the input change interrupt/wake-up function of IOB3 pin.
WUB4:= 0, Disable the input change interrupt/wake-up function of IOB4 pin.
= 1, Enable the input change interrupt/wake-up function of IOB4 pin.
WUB5:= 0, Disable the input change interrupt/wake-up function of IOB5 pin.
= 1, Enable the input change interrupt/wake-up function of IOB5 pin.
WUB6:= 0, Disable the input change interrupt/wake-up function of IOB6 pin.
= 1, Enable the input change interrupt/wake-up function of IOB6 pin.
WUB7:= 0, Disable the input change interrupt/wake-up function of IOB7 pin.
= 1, Enable the input change interrupt/wake-up function of IOB7 pin.
2.1.9
PCHBUF (High Byte Buffer of Program Counter)
Read/Write-POR
-
B7
-
-
B6
-
-
B5
-
-
B4
-
-
B3
-
-
B2
-
R/W-1
B1
R/W-1
B0
Address
0x0A
Name
PCHBUF
2 MSBs Buffer of PC
Legend: - = unimplemented, read as ‘0’, more bits’ default state, please refer to Table 2.2.
Bit1:Bit0:See 2.1.3 for detail description.
Web site: http://www.feeling-techcom.tw
Rev 1.00.003 Mar 02, 2017
Page 11 of 52, FM8PE53M
EELING
FM8PE53M
2.1.10 PDCON (Pull-down Control Register)
Read/Write-POR
R/W-1
B7
R/W-1
B6
R/W-1
B5
R/W-1
B4
R/W-1
B3
R/W-1
B2
R/W-1
B1
R/W-1
B0
Address
0x0B
Name
PDCON
/PDB2
/PDB1
/PDB0
/PDA3
/PDA2
/PDA1
/PDA0
Note: more bits’ default state, please refer to Table 2.2.
/PDA0:= 0, Enable the internal pull-down of IOA0 pin.
= 1, Disable the internal pull-down of IOA0 pin.
/PDA1:= 0, Enable the internal pull-down of IOA1 pin.
= 1, Disable the internal pull-down of IOA1 pin.
/PDA2:= 0, Enable the internal pull-down of IOA2 pin.
= 1, Disable the internal pull-down of IOA2 pin.
/PDA3:= 0, Enable the internal pull-down of IOA3 pin.
= 1, Disable the internal pull-down of IOA3 pin.
/PDB0:= 0, Enable the internal pull-down of IOB0 pin.
= 1, Disable the internal pull-down of IOB0 pin.
/PDB1:= 0, Enable the internal pull-down of IOB1 pin.
= 1, Disable the internal pull-down of IOB1 pin.
/PDB2:= 0, Enable the internal pull-down of IOB2 pin.
= 1, Disable the internal pull-down of IOB2 pin.
Bit7:General purpose read/write bit.
2.1.11 ODCON (Open-drain Control Register)
Read/Write-POR
R/W-0
B7
R/W-0
B6
R/W-0
B5
R/W-0
B4
R/W-0
B3
R/W-0
B2
R/W-0
B1
R/W-0
B0
Address
0x0C
Name
ODCON
ODB7
ODB6
ODB5
ODB4
ODB2
ODB1
ODB0
Note: more bits’ default state, please refer to Table 2.2.
ODB0:= 0, Disable the internal open-drain of IOB0 pin.
= 1, Enable the internal open-drain of IOB0 pin.
ODB1:= 0, Disable the internal open-drain of IOB1 pin.
= 1, Enable the internal open-drain of IOB1 pin.
ODB2:= 0, Disable the internal open-drain of IOB2 pin.
= 1, Enable the internal open-drain of IOB2 pin.
Bit3:General purpose read/write bit.
ODB4:= 0, Disable the internal open-drain of IOB4 pin.
= 1, Enable the internal open-drain of IOB4 pin.
ODB5:= 0, Disable the internal open-drain of IOB5 pin.
= 1, Enable the internal open-drain of IOB5 pin.
Web site: http://www.feeling-techcom.tw
Rev 1.00.003 Mar 02, 2017
Page 12 of 52, FM8PE53M
EELING
FM8PE53M
ODB6:= 0, Disable the internal open-drain of IOB6 pin.
= 1, Enable the internal open-drain of IOB6 pin.
ODB7:= 0, Disable the internal open-drain of IOB7 pin.
= 1, Enable the internal open-drain of IOB7 pin.
2.1.12 PHCON (Pull-high Control Register)
Read/Write-POR
R/W-1
B7
R/W-1
B6
R/W-1
B5
R/W-1
B4
R/W-1
B3
R/W-1
B2
R/W-1
B1
R/W-1
B0
Address
0x0D
Name
PHCON
/PHB7
/PHB6
/PHB5
/PHB4
/PHB2
/PHB1
/PHB0
Note: more bits’ default state, please refer to Table 2.2.
/PHB0:= 0, Enable the internal pull-high of IOB0 pin.
= 1, Disable the internal pull-high of IOB0 pin.
/PHB1:= 0, Enable the internal pull-high of IOB1 pin.
= 1, Disable the internal pull-high of IOB1 pin.
/PHB2:= 0, Enable the internal pull-high of IOB2 pin.
= 1, Disable the internal pull-high of IOB2 pin.
Bit3:General purpose read/write bit.
/PHB4:= 0, Enable the internal pull-high of IOB4 pin.
= 1, Disable the internal pull-high of IOB4 pin.
/PHB5:= 0, Enable the internal pull-high of IOB5 pin.
= 1, Disable the internal pull-high of IOB5 pin.
/PHB6:= 0, Enable the internal pull-high of IOB6 pin.
= 1, Disable the internal pull-high of IOB6 pin.
/PHB7:= 0, Enable the internal pull-high of IOB7 pin.
= 1, Disable the internal pull-high of IOB7 pin.
Web site: http://www.feeling-techcom.tw
Rev 1.00.003 Mar 02, 2017
Page 13 of 52, FM8PE53M
EELING
FM8PE53M
2.1.13 INTEN (Interrupt Mask Register)
Read/Write-POR
R/W-0
B7
*
B6
*
*
B5
*
*
B4
*
*
B3
*
R/W-0
B2
R/W-0
B1
R/W-0
B0
Address
0x0E
Name
INTEN
GIE
INTIE
PBIE
T0IE
Legend: * = unimplemented, read as ‘1’, more bits’ default state, please refer to Table 2.2.
T0IE:Timer0 overflow interrupt enable bit.
= 0, Disable the Timer0 overflow interrupt.
= 1, Enable the Timer0 overflow interrupt.
PBIE:Port B input change interrupt enable bit.
= 0, Disable the Port B input change interrupt.
= 1, Enable the Port B input change interrupt.
INTIE:External INT pin interrupt enable bit.
= 0, Disable the External INT pin interrupt.
= 1, Enable the External INT pin interrupt.
GIE:Global interrupt enable bit.
= 0, Disable all interrupts. For wake-up from SLEEP mode through an interrupt event, the device will continue
execution at the instruction after the SLEEP instruction.
= 1, Enable all un-masked interrupts. For wake-up from SLEEP mode through an interrupt event, the device
will branch to the interrupt address (0x008).
Note:When an interrupt event occurs with the GIE bit and its corresponding interrupt enable bit are all set, the
GIE bit will be cleared by hardware to disable any further interrupts. The RETFIE instruction will exit the
interrupt routine and set the GIE bit to re-enable interrupt.
2.1.14 INTFLAG (Interrupt Status Register)
Read/Write-POR
-
B7
-
-
B6
-
-
B5
-
-
B4
-
-
B3
-
R/W-0
B2
R/W-0
B1
R/W-0
B0
Address
0x0F
Name
INTFLAG
INTIF
PBIF
T0IF
Legend: - = unimplemented, read as ‘0’, more bits’ default state, please refer to Table 2.2.
T0IF:Timer0 overflow interrupt flag. Set when Timer0 overflows, reset by software.
PBIF:Port B input change interrupt flag. Set when Port B input changes, reset by software.
INTIF:External INT pin interrupt flag. Set by rising/falling (selected by INTEDG bit (OPTION<6>)) edge on INT pin,
reset by software.
2.1.15 ACC (Accumulator)
Read/Write-POR
R/W-x
B7
R/W-x
B6
R/W-x
B5
R/W-x
B4
R/W-x
B3
R/W-x
B2
R/W-x
B1
R/W-x
B0
Address
N/A
Name
ACC
Accumulator
Legend: x = unknown, more bits’ default state, please refer to Table 2.2.
Accumulator is an internal data transfer, or instruction operand holding. It cannot be addressed.
Web site: http://www.feeling-techcom.tw
Rev 1.00.003 Mar 02, 2017
Page 14 of 52, FM8PE53M
EELING
FM8PE53M
2.1.16 OPTION Register
Read/Write-POR
W-1
B7
*
W-0
B6
W-1
B5
W-1
B4
W-1
B3
W-1
B2
W-1
B1
W-1
B0
Address
N/A
Name
OPTION
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Accessed by OPTION instruction.
Legend: * = unimplemented, more bits’ default state, please refer to Table 2.2.
By executing the OPTION instruction, the contents of the ACC Register will be transferred to the OPTION Register.
The OPTION Register is a 7-bit wide, write-only register which contains various control bits to configure the
Timer0/WDT pre-scaler, Timer0, and the external INT interrupt.
The OPTION Register are “write-only” and are set all “1”s except INTEDG bit.
PS2:PS0:Pre-scaler rate selects bits.
PS2:PS0
Timer0 Rate
1:2
WDT Rate
1:1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:4
1:2
1:8
1:4
1:16
1:8
1:32
1:16
1:32
1:64
1:128
1:64
1:128
1:256
PSA:Pre-scaler assign bit.
= 0, TMR0 (Timer0).
= 1, WDT (watch-dog timer).
T0SE:TMR0 source edge select bit.
= 0, Rising edge on T0CKI pin.
= 1, Falling edge on T0CKI pin.
T0CS:TMR0 clock source select bit.
= 0, internal instruction clock cycle.
= 1, External T0CKI pin. Pin IOB2/T0CKI is forced to be an input even if IOST IOB2 = “0”.
INTEDG:Interrupt edge select bit.
= 0, interrupt on falling edge of INT pin.
= 1, interrupt on rising edge of INT pin.
Web site: http://www.feeling-techcom.tw
Rev 1.00.003 Mar 02, 2017
Page 15 of 52, FM8PE53M
EELING
FM8PE53M
2.1.17 IOSTA, IOSTB (Port I/O Control Registers)
Read/Write-POR
-
B7
-
-
B6
-
-
B5
-
-
B4
-
W-1
B3
W-1
B2
W-1
B1
W-1
B0
Address
0x05
Name
IOSTA
IOSTA3 IOSTA2 IOSTA1 IOSTA0
Read/Write-POR
W-1
B7
W-1
B6
W-1
B5
W-1
B4
W-1
B3
W-1
B2
W-1
B1
W-1
B0
Address
0x06
Name
IOSTB
IOSTB7 IOSTB6 IOSTB5 IOSTB4 IOSTB3 IOSTB2 IOSTB1 IOSTB0
Accessed by IOST instruction.
Note: more bits’ default state, please refer to Table 2.2.
The Port I/O Control Registers are loaded with the contents of the ACC Register by executing the IOST R
(0x05~0x06) instruction.
The IOST Registers are “write-only” and are set (output drivers disabled) upon RESET.
IOSTA3:IOSTA0:PORTA I/O control bit.
= 0, PORTA pin configured as an output.
= 1, PORTA pin configured as an input (tri-stated).
IOSTB7:IOSTB0:PORTB I/O control bit.
= 0, PORTB pin configured as an output.
= 1, PORTB pin configured as an input (tri-stated).
Note:1.IOB3 is open-drain output only if IOSTB3 = 0.
2.The IOB3 open-drain function will be fixed to “Disable” by H/W if the configuration
bit IOB3OD= Disable, even if bit IOSTB3 = 0.
Web site: http://www.feeling-techcom.tw
Rev 1.00.003 Mar 02, 2017
Page 16 of 52, FM8PE53M
EELING
FM8PE53M
2.2 I/O Ports
Port A and port B are bi-directional tristate I/O ports. Port A is a 4-pin I/O port. Port B is an 8-pin I/O port. Please
note that IOB3 is an input or open-drain output pin.
All I/O pins have data direction control registers (IOSTA, IOSTB) which can configure these pins as output or input.
The exceptions are IOB2 which may be controlled by the T0CS bit (OPTION<5>).
IOB<5:4> and IOB<2:0> have its corresponding pull-high control bits (PHCON register) to enable the weak internal
pull-high. The weak pull-high is automatically turned off when the pin is configured as an output pin.
IOA<3:0> and IOB<2:0> have its corresponding pull-down control bits (PDCON register) to enable the weak internal
pull-down. The weak pull-down is automatically turned off when the pin is configured as an output pin.
IOB<7:4> and IOB<2:0> have its corresponding open-drain control bits (ODCON register) to enable the open-drain
output when these pins are configured to be an output pin.
IOB<7:0> also provides the input change interrupt/wake-up function. Each pin has its corresponding input change
interrupt/wake-up enable bits (WUCON) to select the input change interrupt/wake-up source.
The IOB0 is also an external interrupt input signal by setting the EIS bit (PCON<6>). In this case, IOB0 input change
interrupt/wake-up function will be disabled by hardware even if it is enabled by software.
The CONFIGURATION words can set several I/Os to alternate functions. When acting as alternate functions the
pins will read as “0” during port read.
Figure 2.3: Block Diagram of I/O Pins
IOA3 ~ IOA0:
DATA BUS
D
Q
IOST
Latch
IOST R
EN
Q
Q
I/O PIN
D
DATA
Latch
WR PORT
RD PORT
EN
Q
Pull-down is not shown in the figure
Web site: http://www.feeling-techcom.tw
Rev 1.00.003 Mar 02, 2017
Page 17 of 52, FM8PE53M
EELING
FM8PE53M
IOB0/INT:
DATA BUS
D
Q
IOST
Latch
IOST R
EN
Q
Q
I/O PIN
D
DATA
Latch
WR PORT
EN
Q
D
RD PORT
Set PBIF
Q
Q
Latch
WUB0
EIS
EN
INT
INTEDG
EIS
Pull-high/pull-down and open-drain are not shown in the figure
IOB3:
DATA BUS
D
Q
IOST
Latch
IOST R
EN
Q
Q
I/O PIN
D
DATA
Latch
WR PORT
RD PORT
EN
Q
D
RSTBIN
Q
Q
Set PBIF
WUB3
Latch
EN
Voltage on this pin must not exceed VDD
.
Web site: http://www.feeling-techcom.tw
Rev 1.00.003 Mar 02, 2017
Page 18 of 52, FM8PE53M
EELING
FM8PE53M
IOB7 ~ IOB4, IOB2 ~ IOB1:
DATA BUS
D
Q
IOST
Latch
IOST R
EN
Q
Q
I/O PIN
D
DATA
Latch
WR PORT
RD PORT
EN
Q
D
Q
Q
Set PBIF
WUBn
Latch
EN
Pull-high/pull-down and open-drain are not shown in the figure
Web site: http://www.feeling-techcom.tw
Rev 1.00.003 Mar 02, 2017
Page 19 of 52, FM8PE53M
EELING
FM8PE53M
2.3 Timer0/WDT & Pre-scler
2.3.1
Timer0
The Timer0 is an 8-bit timer/counter. The clock source of Timer0 can come from the internal clock or by an external
clock source (T0CKI pin).
2.3.1.1 Using Timer0 with an Internal Clock: Timer mode
Timer mode is selected by clearing the T0CS bit (OPTION<5>). In timer mode, the timer0 register (TMR0) will
increment every instruction cycle (without pre-scaler). If TMR0 register is written, the increment is inhibited for the
following two cycles.
2.3.1.2 Using Timer0 with an External Clock: Counter mode
Counter mode is selected by setting the T0CS bit (OPTION<5>). In this mode, Timer0 will increment either on
every rising or falling edge of pin T0CKl. The incrementing edge is determined by the source edge select bit T0SE
(OPTION<4>).
The external clock requirement is due to internal phase clock (TOSC) synchronization. Also, there is a delay in the
actual incrementing of Timer0 after synchronization.
When no pre-scaler is used, the external clock input is the same as the pre-scaler output. The synchronization of
T0CKI with the internal phase clocks is accomplished by sampling the pre-scaler output on the T2 and T4 cycles of
the internal phase clocks. Therefore, it is necessary for T0CKI to be high for at least 2 TOSC and low for at least 2
TOSC
.
When a pre-scaler is used, the external clock input is divided by the asynchronous pre-scaler. For the external
clock to meet the sampling requirement, the ripple counter must be taken into account. Therefore, it is necessary
for T0CKI to have a period of at least 4 TOSC divided by the pre-scaler value.
2.3.2
Watchdog Timer (WDT)
The Watchdog Timer (WDT) is a free running on-chip RC oscillator which does not require any external components.
So the WDT will still run even if the clock on the OSCI and OSCO pins is turned off, such as in SLEEP mode.
̅̅̅̅
During normal operation or in SLEEP mode, a WDT time-out will cause the device reset and the TO bit (STATUS<4>)
will be cleared.
The WDT can be disabled by clearing the control bit WDTE (PCON<7>) to “0”.
The WDT has a nominal time-out period of 18ms, 4.5ms, 288ms or 72ms selected by SUT bit of configuration word
(without pre-scaler). If a longer time-out period is desired, a pre-scaler with a division ratio of up to 1:128 can be
assigned to the WDT controlled by the OPTION register. Thus, the longest time-out period is approximately 36.8
seconds.
The CLRWDT instruction clears the WDT and the pre-scaler, if assigned to the WDT, and prevents it from timing
out and generating a device reset.
The SLEEP instruction resets the WDT and the pre-scaler, if assigned to the WDT. This gives the maximum SLEEP
time before a WDT Wake-up Reset.
2.3.3
Pre-scaler
An 8-bit counter (down counter) is available as a pre-scaler for the Timer0, or as a post-scaler for the Watchdog
Timer (WDT). Note that the pre-scaler may be used by either the Timer0 module or the WDT, but not both. Thus,
a pre-scaler assignment for the Timer0 means that there is no pre-scaler for the WDT, and vice-versa.
The PSA bit (OPTION<3>) determines pre-scaler assignment. The PS<2:0> bits (OPTION<2:0>) determine pre-
scaler ratio.
When the pre-scaler is assigned to the Timer0 module, all instructions writing to the TMR0 register will clear the
pre-scaler. When it is assigned to WDT, a CLRWDT instruction will clear the pre-scaler along with the WDT.
The pre-scaler is neither readable nor writable. On a RESET, the pre-scaler contains all ‘1’s.
To avoid an unintended device reset, CLRWDT or CLRR TMR0 instructions must be executed when changing the
Web site: http://www.feeling-techcom.tw
Rev 1.00.003 Mar 02, 2017
Page 20 of 52, FM8PE53M
EELING
FM8PE53M
pre-scaler assignment from Timer0 to the WDT, and vice-versa.
Figure 2.4: Block Diagram of the Timer0/WDT Pre-scaler
Instruction Cycle
(Fosc/2, Fosc/4)
8
0
1
Data Bus
Sync
TMR0
T0SE
2 Cycles
Register
Set T0IF flag
on overflow
1
0
T0CKI (IOB2)
T0CS
PSA
0
1
8-Bit
WDT Time-out
Prescaler
1
0
Watchdog
Timer
PSA
PSA
PS2:PS0
2.4 Interrupts
The FM8PE53M has up to three sources of interrupt:
1. External interrupt INT pin.
2. TMR0 overflow interrupt.
3. Port B input change interrupt (pins IOB7:IOB0).
INTFLAG is the interrupt flag register that recodes the interrupt requests in the relative flags.
A global interrupt enable bit, GIE (INTEN<7>), enables (if set) all un-masked interrupts or disables (if cleared) all
interrupts. Individual interrupts can be enabled/disabled through their corresponding enable bits in INTEN register
regardless of the status of the GIE bit.
When an interrupt event occurs with the GIE bit and its corresponding interrupt enable bit are all set, the GIE bit will
be cleared by hardware to disable any further interrupts, and the next instruction will be fetched from address 0x008.
The interrupt flag bits must be cleared by software before re-enabling GIE bit to avoid recursive interrupts.
The RETFIE instruction exits the interrupt routine and set the GIE bit to re-enable interrupt.
The flag bit (except PBIF bit) in INTFLAG register is set by interrupt event regardless of the status of its mask bit.
Reading the INTFLAG register will be the logic AND of INTFLAG and INTEN.
When an interrupt is generated by the INT instruction, the next instruction will be fetched from address 0x002.
2.4.1
External INT Interrupt
External interrupt on INT pin is rising or falling edge triggered selected by INTEDG (OPTION<6>).
When a valid edge appears on the INT pin the flag bit INTIF (INTFLAG<2>) is set. This interrupt can be disabled
by clearing INTIE bit (INTEN<2>).
The INT pin interrupt can wake-up the system from SLEEP condition, if bit INTIE was set before going to SLEEP. If
GIE bit was set, the program will execute interrupt service routine after wake-up; or if GIE bit was cleared, the
program will execute next PC after wake-up.
2.4.2
Timer0 Interrupt
An overflow (0xFF 0x00) in the TMR0 register will set the flag bit T0IF (INTFLAG<0>). This interrupt can be
disabled by clearing T0IE bit (INTEN<0>).
2.4.3
Port B Input Change Interrupt
An input change on IOB<7:0> set flag bit PBIF (INTFLAG<1>). This interrupt can be disabled by clearing PBIE bit
(INTEN<1>).
Web site: http://www.feeling-techcom.tw
Rev 1.00.003 Mar 02, 2017
Page 21 of 52, FM8PE53M
EELING
FM8PE53M
Before the port B input change interrupt is enabled, reading PORTB (any instruction accessed to PORTB, including
read/write instructions) is necessary. Any pin which corresponding WUBn bit (WUCON<5:0>) is cleared to “0” or
configured as output or IOB0 pin configured as INT pin will be excluded from this function.
The port B input change interrupt also can wake-up the system from SLEEP condition, if bit PBIE was set before
going to SLEEP. And GIE bit also decides whether or not the processor branches to the interrupt vector following
wake-up. If GIE bit was set, the program will execute interrupt service routine after wake-up; or if GIE bit was cleared,
the program will execute next PC after wake-up.
2.5 Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP instruction.
̅̅̅̅
̅̅̅̅
When SLEEP instruction is executed, the PD bit (STATUS<3>) is cleared, the TO bit is set, the watchdog timer will
be cleared and keeps running, and the oscillator driver is turned off.
All I/O pins maintain the status they had before the SLEEP instruction was executed.
2.5.1
Wake-up from SLEEP Mode
The device can wake-up from SLEEP mode through one of the following events:
1. RSTB reset.
2. WDT time-out reset (if enabled).
3. Interrupt from IOB0/INT pin, or PORTB change interrupt.
External RSTB reset and WDT time-out reset will cause a device reset. The PD and TO bits can be used to
̅̅̅̅
̅̅̅̅
̅̅̅̅
determine the cause of device reset. The PD bit is set on power-up and is cleared when SLEEP instruction is
̅̅̅̅
executed. The TO bit is cleared if a WDT time-out occurred.
For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set. Wake-up
is regardless of the GIE bit. If GIE bit is cleared, the device will continue execution at the instruction after the SLEEP
instruction. If the GIE bit is set, the device will branch to the interrupt address (0x008).
In HF, XT or LF oscillation mode, the system wake-up delay time is 18/4.5/288/72ms (selected by SUT bit of
configuration word).
And in IRC or ERIC oscillation mode, the system wake-up delay time is 140us.
2.6 Reset
FM8PE53M devices may be RESET in one of the following ways:
1. Power-on Reset (POR)
2. Brown-out Reset (BOR)
3. RSTB Pin Reset
4. WDT time-out Reset
Some registers are not affected in any RESET condition. Their status is unknown on Power-on Reset and
unchanged in any other RESET. Most other registers are reset to a “reset state” on Power-on Reset, RSTB or WDT
Reset.
A Power-on RESET pulse is generated on-chip when VDD rise is detected. To use this feature, the user merely ties
the RSTB pin to VDD
.
On-chip Low Voltage Detector (LVD) places the device into reset when VDD is below a fixed voltage. This ensures
that the device does not continue program execution outside the valid operation VDD range. Brown-out RESET is
typically used in AC line or heavy loads switched applications.
A RSTB or WDT Wake-up from SLEEP also results in a device RESET, and not a continuation of operation before
SLEEP.
̅̅̅̅
̅̅̅̅
The TO and PD bits (STATUS<4:3>) are set or cleared depending on the different reset conditions.
2.6.1
Power-up Reset Timer (PWRT)
The Power-up Reset Timer provides a nominal 18/4.5/288/72ms (selected by SUT bit of configuration word) (or
140us, varies based on oscillator selection and reset condition) delay after Power-on Reset (POR), Brown-out Reset
Web site: http://www.feeling-techcom.tw
Rev 1.00.003 Mar 02, 2017
Page 22 of 52, FM8PE53M
EELING
FM8PE53M
(BOR), RSTB Reset or WDT time-out Reset. The device is kept in reset state as long as the PWRT is active.
The PWDT delay will vary from device to device due to VDD, temperature, and process variation.
Table 2.1: PWRT Period
Power-on Reset
Brown-out Reset
RSTB Reset
WDT time-out Reset
Oscillator Mode
IRC & ERC & ERIC 18/4.5/288/72ms or 140us
HF & XT & LF 18/4.5/288/72ms
140us
18/4.5/288/72ms
2.6.2
Oscillator Start-up Timer (OST)
The OST timer provides a 64-oscillator cycle delay (from OSCI input) after the PWRT delay (18/4.5/288/72ms or
140us) is over. This delay ensures that the oscillator has started and stabilized. The device is kept in reset state
as long as the OST is active.
This counter only starts incrementing after the amplitude of the OSCI signal reaches the oscillator input thresholds.
2.6.3
Reset Sequence
When Power-on Reset (POR), Brown-out Reset (BOR), RSTB Reset or WDT time-out Reset is detected, the reset
sequence is as follows:
1. The reset latch is set and the PWRT & OST are cleared.
2. When the internal POR, BOR, RSTB Reset or WDT time-out Reset pulse is finished, then the PWRT begins
counting.
3. After the PWRT time-out, the OST is activated.
4. And after the OST delay is over, the reset latch will be cleared and thus end the on-chip reset signal.
In HF, XT or LF oscillation mode, the totally system reset delay time is 18/4.5/288/72ms plus 64 oscillator cycle time.
And in IRC/ERIC or ERC oscillation mode, the totally system reset delay time is 18/4.5/288/72ms or 140us after
Power-on Reset (POR), Brown-out Reset (BOR), or 140us after RSTB Reset or WDT time-out Reset.
Figure 2.5: Simplified Block Diagram of on-chip Reset Circuit
WDT
Time-out
WDT
Module
RSTB
Vdd
S
R
Q
Q
Reset
Latch
Low Voltage
Detector
(LVD)
BOR
CHIP RESET
Power-on
Reset
POR
(POR)
RESET
RESET
On-Chip
RC OSC
Power-up
Reset Timer
(PWRT)
Oscillator
Start-up Timer
(OST)
OSCI
Web site: http://www.feeling-techcom.tw
Rev 1.00.003 Mar 02, 2017
Page 23 of 52, FM8PE53M
EELING
FM8PE53M
Table 2.2: Reset Conditions for All Registers
Power-on Reset
Brown-out Reset
RSTB Reset
WDT Reset
Register
Address
ACC
N/A
N/A
xxxx xxxx
*011 1111
---- 1111
1111 1111
xxxx xxxx
xxxx xxxx
1111 1111
0001 1xxx
**xx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
101* ****
0000 0000
---- --11
1111 1111
0000 0000
1111 1111
0*** *000
---- -000
xxxx xxxx
uuuu uuuu
*011 1111
---- 1111
1111 1111
uuuu uuuu
uuuu uuuu
1111 1111
000# #uuu
**uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
101* ****
0000 0000
---- --11
1111 1111
0000 0000
1111 1111
0*** *000
---- -000
uuuu uuuu
OPTION
IOSTA
0x05
IOSTB
0x06
INDF
0x00
TMR0
0x01
PCL
0x02
STATUS
0x03
FSR
0x04
PORTA
0x05
PORTB
0x06
General Purpose Register
0x07
PCON
0x08
WUCON
0x09
PCHBUF
0x0A
PDCON
0x0B
ODCON
PHCON
0x0C
0x0D
INTEN
0x0E
INTFLAG
0x0F
General Purpose Registers
0x10 ~ 0x3F
Legend:u = unchanged, x = unknown, - = unimplemented, read as ‘0’; * = unimplemented, read as ‘1’; # = refer to
the following table for possible values.
̅̅̅̅ ̅̅̅̅
Table 2.3: RST / TO / PD Status after Reset or Wake-up
̅̅̅̅
̅̅̅̅
RST
0
TO
PD
RESET was caused by
Power-on Reset.
1
1
u
1
0
0
1
1
1
u
0
1
0
0
0
Brown-out reset.
0
RSTB Reset during normal operation.
RSTB Reset during SLEEP.
0
0
WDT Reset during normal operation.
WDT Wake-up during SLEEP.
Wake-up on pin change during SLEEP.
0
1
Legend: u = unchanged
̅̅̅̅ ̅̅̅̅
Table 2.4: Events AffectingTO / PDStatus Bits
̅̅̅̅
̅̅̅̅
PD
Event
TO
Power-on.
1
0
1
1
1
u
0
1
WDT Time-Out.
SLEEP instruction.
CLRWDT instruction.
Legend: u = unchanged.
Web site: http://www.feeling-techcom.tw
Rev 1.00.003 Mar 02, 2017
Page 24 of 52, FM8PE53M
EELING
FM8PE53M
2.7 Hexadecimal Convert to Decimal (HCD)
Decimal format is another number format for FM8PE53M. When the content of the data memory has been assigned
as decimal format, it is necessary to convert the results to decimal format after the execution of ALU instructions.
When the decimal converting, operation is processing, all of the operand data (including the contents of the data
memory (RAM), accumulator (ACC), immediate data, and look-up table) should be in the decimal format, or the
results of conversion will be incorrect.
Instruction DAA can convert the ACC data from hexadecimal to decimal format after any addition operation and
restored to ACC.
The conversion operation is illustrated in example 2.2.
Example 2.2: DAA CONVERSION
Code
#include
<8PE53M.ASH>
…
MOVIA
MOVAR
MOVIA
ADDAR
0x90
;Set immediate data = decimal format number “90” (ACC 0x90)
;Load immediate data “90” to data memory address 0x30
;Set immediate data = decimal format number “10” (ACC 0x10)
;Contents of the data memory address 0x30 and ACC are binary-added
;the result loads to the ACC (ACC 0xA0, C 0)
0x30
0x10
0x30,A
DAA
…
;Convert the content of ACC to decimal format, and restored to ACC
;The result in the ACC is “00” and the carry bit C is “1”. This represents the
;decimal number “100”
Instruction DAS can convert the ACC data from hexadecimal to decimal format after any subtraction operation and
restored to ACC.
The conversion operation is illustrated in example 2.3.
Example 2.3: DAS CONVERSION
Code
#include
<8PE53M.ASH>
…
MOVIA
MOVAR
MOVIA
SUBAR
0x10
;Set immediate data = decimal format number “10” (ACC 0x10)
;Load immediate data “90” to data memory address 0x30
;Set immediate data = decimal format number “20” (ACC 0x20)
;Contents of the data memory address 0x30 and ACC are binary-subtracted
;the result loads to the ACC (ACC 0xF0, C 0)
0x30
0x20
0x30,A
DAS
…
;Convert the content of ACC to decimal format, and restored to ACC
;The result in the ACC is “90” and the carry bit C is “0”. This represents the
;decimal number “ -10”
Web site: http://www.feeling-techcom.tw
Rev 1.00.003 Mar 02, 2017
Page 25 of 52, FM8PE53M
EELING
FM8PE53M
2.8 Oscillator Configurations
FM8PE53M can be operated in six different oscillator modes. Users can program FOSC configuration bit to select
the appropriate modes:
ERC: External Resistor/Capacitor Oscillator
HF: High Frequency Crystal/Resonator Oscillator
XT: Crystal/Resonator Oscillator
LF: Low Frequency Crystal Oscillator
IRC: Internal Resistor/Capacitor Oscillator
ERIC: External Resistor/Internal Capacitor Oscillator
In LF, XT, or HF modes, a crystal or ceramic resonator in connected to the OSCI and OSCO pins to establish
oscillation. When in LF, XT, or HF modes, the devices can have an external clock source drive the OSCI pin.
The ERC device option offers additional cost savings for timing insensitive applications. The RC oscillator frequency
is a function of the resistor (REXT) and capacitor (CEXT), the operating temperature, and the process parameter.
The IRC/ERIC device option offers largest cost savings for timing insensitive applications. These devices offer 4
different internal RC oscillator frequency, 8MHZ, 4MHZ, 1MHZ, and 455KHZ, which is selected by configuration bit
(FOSC). Or user can change the oscillator frequency with external resistor. The ERIC oscillator frequency is a function
of the resistor (REXT), the operating temperature, and the process parameter.
Figure 2.6: HF, XT or LF Oscillator Modes (Crystal Operation or Ceramic Resonator)
FM8PE53M
C1
OSCI
R1
OSCO
VDD
SLEEP
X`TAL
RS
RF
0.1uF
VSS
C2
Internal
Circuit
Figure 2.7: HF, XT or LF Oscillator Modes (External Clock Input Operation)
FM8PE53M
OSCI
VDD
Clock from
External System
0.1uF
VSS
OSCO
Figure 2.8: ERC Oscillator Mode (External RC Oscillator)
FM8PE53M
Rext
OSCI
VDD
Internal
Circuit
0.1uF
Cext
VSS
/2, /4
OSCO
Web site: http://www.feeling-techcom.tw
Rev 1.00.003 Mar 02, 2017
Page 26 of 52, FM8PE53M
EELING
FM8PE53M
Figure 2.9: ERIC Oscillator Mode (External R, Internal C Oscillator)
FM8PE53M
Rext
OSCI
VDD
Internal
Circuit
Cext
(300pF~0.1uF)
C
0.1uF
VSS
/2, /4
OSCO
The typical oscillator frequency vs. external resistor is as following table
When CEXT = 0.01uf (103)
Frequency
455KHZ
1MHZ
REXT @ 3V
958.7K
REXT @ 5V
1.45M
691.2K
933.2K
322.6K
167.7K
4MHZ
280.2K
8MHZ
158.1K
Note: Values are provided for design reference only.
Figure 2.10: IRC Oscillator Mode (Internal R, Internal C Oscillator)
FM8PE53M
OSCI
C
VDD
Internal
Circuit
0.1uF
VSS
/2, /4
OSCO
Web site: http://www.feeling-techcom.tw
Rev 1.00.003 Mar 02, 2017
Page 27 of 52, FM8PE53M
EELING
FM8PE53M
2.9 Configuration Words
Table 2.5: Configuration Words
Name
Description
Oscillator Selection Bit
ERC mode (external R & C) (default)
IOB4/OSCO pin controlled by OSCOUT configuration bit
HF mode
XT mode
LF mode
4MHZ IRC mode (internal R & C)
IOB4/OSCO pin controlled by OSCOUT configuration bit
8MHZ IRC mode (internal R & C)
FOSC
IOB4/OSCO pin controlled by OSCOUT configuration bit
1MHZ IRC mode (internal R & C)
IOB4/OSCO pin controlled by OSCOUT configuration bit
455KHZ IRC mode (internal R & C)
IOB4/OSCO pin controlled by OSCOUT configuration bit
ERIC mode (external R & internal C)
IOB4/OSCO pin controlled by OSCOUT configuration bit
Note: See Table 2.6 for detail description.
Low Voltage Detector Selection Bit
Enable, LVDT voltage = 3.6V
Enable, LVDT voltage = 2.6V
Enable, LVDT voltage = 2.4V
Enable, LVDT voltage = 2.2V
Enable, LVDT voltage = 2.0V
Enable, LVDT voltage = 2.0V, controlled by SLEEP
Enable, LVDT voltage = 1.8V
Disable (default)
LVDT
PWRT & WDT Time Period Selection Bit (The value must be a multiple of pre-scaler rate)
PWRT = WDT pre-scaler rate = 18ms (default)
PWRT = WDT pre-scaler rate = 4.5ms
PWRT = WDT pre-scaler rate = 288ms
SUT
PWRT = WDT pre-scaler rate = 72ms
PWRT = 140us, WDT pre-scaler rate = 18ms
PWRT = 140us, WDT pre-scaler rate = 4.5ms
PWRT = 140us, WDT pre-scaler rate = 288ms
PWRT = 140us, WDT pre-scaler rate = 72ms
IOB4/OSCO Pin Selection Bit for IRC/ERIC Mode
OSCO pin is selected (default)
IOB4 pin is selected
OSCOUT
RSTBIN
WDTEN
PROTECT
OSCD
IOB3/RSTB Pin Selection Bit
IOB3 pin is selected (default)
RSTB pin is selected
Watchdog Timer Enable Bit
WDT enabled (default)
WDT disabled
Code Protection Bit
OTP code protection off (default)
OTP code protection on
Instruction Period Selection Bit
Four oscillator periods (default)
Two oscillator periods
Web site: http://www.feeling-techcom.tw
Rev 1.00.003 Mar 02, 2017
Page 28 of 52, FM8PE53M
EELING
FM8PE53M
Name
Description
Read Port Control Bit for Output Pins
From registers (default)
From pins
RDPORT
SCHMITT
IOB3OD
I/O Pin Input Buffer Control Bit
With Schmitt-trigger (default)
Without Schmitt-trigger
IOB3 Pin Open-Drain Output Enable Bit
Enable open-drain function (IOB3 pin is Bi-direction) (default)
Disable open-drain function (IOB3 pin is Only input)
Table 2.6: Selection of IOB5/OSCI and IOB4/OSCO Pins
Mode of oscillation
IRC
IOB5/OSCI
Force to IOB5
Force to OSCI
Force to OSCI
IOB4/OSCO
IOB4/OSCO selected by OSCOUT bit
IOB4/OSCO selected by OSCOUT bit
Force to OSCO
ERC, ERIC
HF, XT, LF
Web site: http://www.feeling-techcom.tw
Rev 1.00.003 Mar 02, 2017
Page 29 of 52, FM8PE53M
EELING
FM8PE53M
3.0 INSTRUCTION SET
Mnemonic,
Operands
Status
Affected
Description
Operation
Cycles
BCR
R, bit Clear bit in R
R, bit Set bit in R
0 R<b>
1
1
1/2(1)
1/2(1)
1
-
-
-
-
-
BSR
1 R<b>
BTRSC
BTRSS
NOP
R, bit Test bit in R, Skip if Clear
R, bit Test bit in R, Skip if Set
No Operation
Skip if R<b> = 0
Skip if R<b> = 1
No operation
0x00 WDT,
0x00 WDT pre-scaler
0x00 WDT,
̅̅̅̅ ̅̅̅̅
CLRWDT
Clear Watchdog Timer
1
TO, PD
̅̅̅̅ ̅̅̅̅
SLEEP
OPTION
DAA
Go into power-down mode
Load OPTION register
1
1
1
TO, PD
0x00 WDT pre-scaler
ACC OPTION
-
Adjust ACC’s data format from HEX to DEC
after any addition operation
ACC(hex) ACC (Dec)
C
Adjust ACC’s data format from HEX to DEC
after any subtraction operation
DAS
ACC(hex) ACC (Dec)
Top of Stack PC
1
2
2
-
-
-
RETURN
RETFIE
Return from subroutine
Top of Stack PC,
1 GIE
Return from interrupt, set GIE bit
PC + 1 Top of Stack
0x002 PC
INT
S/W interrupt
2
-
IOST
R
Load IOST register
Clear ACC
ACC IOST register
0x00 ACC
0x00 R
1
1
1
1
1
1
-
CLRA
CLRR
MOVAR
MOVR
DECR
Z
Z
-
R
R
Clear R
Move ACC to R
ACC R
R, d Move R
R dest
Z
Z
R, d Decrement R
R - 1 dest
R - 1 dest,
Skip if result = 0
DECRSZ
INCR
R, d Decrement R, Skip if 0
R, d Increment R
1/2(1)
1
-
Z
-
R + 1 dest
R + 1 dest,
Skip if result = 0
INCRSZ
R, d Increment R, Skip if 0
1/2(1)
ADDAR
SUBAR
ADCAR
SBCAR
ANDAR
IORAR
XORAR
COMR
R, d Add ACC and R
R + ACC dest
R - ACC dest
1
1
1
1
1
1
1
1
C, DC, Z
R, d Subtract ACC from R
R, d Add ACC and R with Carry
R, d Subtract ACC from R with Carry
R, d AND ACC with R
C, DC, Z
R + ACC + C dest
C, DC, Z
̅̅̅̅̅̅̅
R + ACC + C dest
C, DC, Z
ACC and R dest
ACC or R dest
R xor ACC dest
Z
Z
Z
Z
R, d Inclusive OR ACC with R
R, d Exclusive OR ACC with R
R, d Complement R
ꢀ
R dest
R<7> C,
RLR
R, d Rotate left R through Carry
R<6:0> dest<7:1>,
C dest<0>
1
C
C dest<7>,
RRR
R, d Rotate right R through Carry
R, d Swap R
R<7:1> dest<6:0>,
R<0> C
1
1
C
-
R<3:0> dest<7:4>,
R<7:4> dest<3:0>
SWAPR
Web site: http://www.feeling-techcom.tw
Rev 1.00.003 Mar 02, 2017
Page 30 of 52, FM8PE53M
EELING
FM8PE53M
Mnemonic,
Operands
Status
Description
Operation
Cycles
Affected
MOVIA
I
I
I
I
I
I
Move Immediate to ACC
I ACC
1
1
1
1
1
1
-
ADDIA
SUBIA
ANDIA
IORIA
Add ACC and Immediate
Subtract ACC from Immediate
AND Immediate with ACC
OR Immediate with ACC
I + ACC ACC
I - ACC ACC
ACC and I ACC
ACC or I ACC
ACC xor I ACC
C, DC, Z
C, DC, Z
Z
Z
Z
XORIA
Exclusive OR Immediate to ACC
I ACC,
RETIA
I
Return, place Immediate in ACC
2
-
Top of Stack PC
PC + 1 Top of Stack,
I PC
CALL
I
I
Call subroutine
2
2
-
-
GOTO
Unconditional branch
I PC
Note: 1. 2 cycles for skip, else 1 cycle.
2. bit:Bit address within an 8-bit register R
R:Register address (0x00 to 0x3F)
I:Immediate data
ACC:Accumulator
d:Destination select;
=0 (store result in ACC)
=1 (store result in file register R)
dest:Destination
PC:Program Counter
PCH:High Byte register of Program Counter
WDT:Watchdog Timer Counter
GIE:Global interrupt enable bit
̅̅̅̅
TO:Time-out bit
̅̅̅̅
PD:Power-down bit
C:Carry bit
DC:Half carry bit
Z:Zero bit
Web site: http://www.feeling-techcom.tw
Rev 1.00.003 Mar 02, 2017
Page 31 of 52, FM8PE53M
EELING
FM8PE53M
ADCAR
Add ACC and R with Carry
Syntax:
ADCAR R, d
Operands:
0x00≤R≤0x3F
d∈[0,1]
Operation:
Status Affected:
Description:
R + ACC + C dest
C, DC, Z
Add the contents of the ACC register and register ‘R’ with Carry. If ‘d’ is 0 the result is stored
in the ACC register. If ‘d’ is ‘1’ the result is stored back in register ‘R’.
1
Cycles:
ADDAR
Syntax:
Add ACC and R
ADDAR R, d
Operands:
0x00≤R≤0x3F
d∈[0,1]
Operation:
ACC + R dest
Status Affected:
Description:
C, DC, Z
Add the contents of the ACC register and register ‘R’. If ‘d’ is 0 the result is stored in the ACC
register. If ‘d’ is ‘1’ the result is stored back in register ‘R’.
1
Cycles:
ADDIA
Add ACC and Immediate
Syntax:
ADDIA I
Operands:
Operation:
Status Affected:
Description:
0x00≤I≤0xFF
ACC + I ACC
C, DC, Z
Add the contents of the ACC register with the 8-bit immediate ‘I’. The result is placed in the
ACC register.
1
Cycles:
ANDAR
Syntax:
AND ACC and R
ANDAR R, d
Operands:
0x00≤R≤0x3F
d∈[0,1]
Operation:
ACC and R dest
Status Affected:
Description:
Z
The contents of the ACC register are AND’ed with register ‘R’. If ‘d’ is 0 the result is stored in
the ACC register. If ‘d’ is ‘1’ the result is stored back in register ‘R’.
1
Cycles:
ANDIA
AND Immediate with ACC
Syntax:
ANDIA I
Operands:
Operation:
Status Affected:
Description:
0x00≤I≤0xFF
ACC AND I ACC
Z
The contents of the ACC register are AND’ed with the 8-bit immediate ‘I’. The result is placed
in the ACC register.
1
Cycles:
Web site: http://www.feeling-techcom.tw
Rev 1.00.003 Mar 02, 2017
Page 32 of 52, FM8PE53M
EELING
FM8PE53M
BCR
Clear Bit in R
Syntax:
BCR R, b
Operands:
0x00≤R≤0x3F
0x0≤b≤0x7
Operation:
Status Affected:
Description:
Cycles:
0 R<b>
None
Clear bit ‘b’ in register ‘R’.
1
BSR
Set Bit in R
BSR R, b
0x00≤R≤0x3F
0x0≤b≤0x7
1 R<b>
None
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
Set bit ‘b’ in register ‘R’.
1
BTRSC
Test Bit in R, Skip if Clear
Syntax:
BTRSC R, b
Operands:
0x00≤R≤0x3F
0x0≤b≤0x7
Operation:
Skip if R<b> = 0
Status Affected:
Description:
None
If bit ‘b’ in register ‘R’ is 0 then the next instruction is skipped.
If bit ‘b’ is 0 then next instruction fetched during the current instruction execution is discarded,
and a NOP is executed instead making this a 2-cycle instruction.
1/2
Cycles:
BTRSS
Test Bit in R, Skip if Set
Syntax:
BTRSS R, b
Operands:
0x00≤R≤0x3F
0x0≤b≤0x7
Operation:
Skip if R<b> = 1
Status Affected:
Description:
None
If bit ‘b’ in register ‘R’ is ‘1’ then the next instruction is skipped.
If bit ‘b’ is ‘1’, then the next instruction fetched during the current instruction execution, is
discarded and a NOP is executed instead, making this a 2-cycle instruction.
1/2
Cycles:
CALL
Subroutine Call
Syntax:
CALL I
Operands:
Operation:
0x000≤I≤0x3FF
PC + 1 Top of Stack,
I PC<9:0>
Status Affected:
Description:
None
Subroutine call. First, return address (PC+1) is pushed onto the stack. The 10-bit immediate
address is loaded into PC bits <9:0>.
2
Cycles:
Web site: http://www.feeling-techcom.tw
Rev 1.00.003 Mar 02, 2017
Page 33 of 52, FM8PE53M
EELING
FM8PE53M
CLRA
Clear ACC
Syntax:
CLRA
Operands:
Operation:
None
0x00 ACC;
1 Z
Status Affected:
Description:
Cycles:
Z
The ACC register is cleared. Zero bit (Z) is set.
1
CLRR
Clear R
Syntax:
CLRR R
Operands:
Operation:
0x00≤R≤0x3F
0x00 R;
1 Z
Status Affected:
Description:
Cycles:
Z
The contents of register ‘R’ are cleared and the Z bit is set.
1
CLRWDT
Syntax:
Clear Watchdog Timer
CLRWDT
Operands:
Operation:
None
0x00 WDT;
0x00 WDT pre-scaler (if assigned);
̅̅̅̅
1 TO;
̅̅̅̅
1 PD
̅̅̅̅ ̅̅̅̅
Status Affected:
Description:
TO, PD
The CLRWDT instruction resets the WDT. It also resets the pre-scaler, if the pre-scaler is
̅̅̅̅
̅̅̅̅
assigned to the WDT and not Timer0. Status bits TO and PD are set.
1
Cycles:
COMR
Complement R
COMR R, d
0x00≤R≤0x3F
d∈[0,1]
Syntax:
Operands:
ꢀ
Operation:
R dest
Status Affected:
Description:
Z
The contents of register ‘R’ are complemented. If ‘d’ is 0 the result is stored in the ACC
register. If ‘d’ is 1 the result is stored back in register ‘R’.
1
Cycles:
DAA
Adjust ACC’s data format from HEX to DEC
Syntax:
DAA
Operands:
Operation:
Status Affected:
Description:
None
ACC(hex) ACC(dec)
C
Convert the ACC data from hexadecimal to decimal format after any addition operation and
restored to ACC.
1
Cycles:
Web site: http://www.feeling-techcom.tw
Rev 1.00.003 Mar 02, 2017
Page 34 of 52, FM8PE53M
EELING
FM8PE53M
DAS
Adjust ACC’s data format from HEX to DEC
Syntax:
DAS
Operands:
Operation:
Status Affected:
Description:
None
ACC(hex) ACC(dec)
None
Convert the ACC data from hexadecimal to decimal format after any subtraction operation
and restored to ACC.
1
Cycles:
DECR
Decrement R
Syntax:
Operands:
DECR R, d
0x00≤R≤0x3F
d∈[0,1]
Operation:
R - 1 dest
Status Affected:
Description:
Z
Decrement of register ‘R’. If ‘d’ is 0 the result is stored in the ACC register. If ‘d’ is 1 the result
is stored back in register ‘R’.
1
Cycles:
DECRSZ
Syntax:
Decrement R, Skip if 0
DECRSZ R, d
Operands:
0x00≤R≤0x3F
d∈[0,1]
Operation:
R - 1 dest; skip if result =0
Status Affected:
Description:
None
The contents of register ‘R’ are decrement. If ‘d’ is 0 the result is placed in the ACC register.
If ‘d’ is 1 the result is stored back in register ’R’.
If the result is 0, the next instruction, which is already fetched, is discarded and a NOP is
executed instead and making it a 2-cycle instruction.
1/2
Cycles:
GOTO
Unconditional Branch
Syntax:
GOTO I
Operands:
Operation:
Status Affected:
Description:
Cycles:
0x000≤I≤0x3FF
I PC<9:0>
None
GOTO is an unconditional branch. The 10-bit immediate value is loaded into PC bits <9:0>.
2
INCR
Increment R
Syntax:
Operands:
INCR R, d
0x00≤R≤0x3F
d∈[0,1]
Operation:
R + 1 dest
Status Affected:
Description:
Z
The contents of register ‘R’ are increment. If ‘d’ is 0 the result is placed in the ACC register.
If ‘d’ is 1 the result is stored back in register ‘R’.
1
Cycles:
Web site: http://www.feeling-techcom.tw
Rev 1.00.003 Mar 02, 2017
Page 35 of 52, FM8PE53M
EELING
FM8PE53M
INCRSZ
Increment R, Skip if 0
Syntax:
INCRSZ R, d
Operands:
0x00≤R≤0x3F
d∈[0,1]
Operation:
R + 1 dest, skip if result = 0
Status Affected:
Description:
None
The contents of register ‘R’ are increment. If ‘d’ is 0 the result is placed in the ACC register.
If ‘d’ is the result is stored back in register ‘R’.
If the result is 0, then the next instruction, which is already fetched, is discarded and a NOP
is executed instead and making it a 2-cycle instruction.
1/2
Cycles:
INT
S/W Interrupt
Syntax:
Operands:
Operation:
INT
None
PC + 1 Top of Stack,
0x002 PC
Status Affected:
Description:
None
Interrupt subroutine call. First, return address (PC+1) is pushed onto the stack. The address
0x002 is loaded into PC bits <9:0>.
2
Cycles:
IORAR
OR ACC with R
Syntax:
IORAR R, d
Operands:
0x00≤R≤0x3F
d∈[0,1]
Operation:
ACC or R dest
Status Affected:
Description:
Z
Inclusive OR the ACC register with register ‘R’. If ‘d’ is 0 the result is placed in the ACC
register. If ‘d’ is 1 the result is placed back in register ‘R’.
1
Cycles:
IORIA
OR Immediate with ACC
Syntax:
IORIA I
Operands:
Operation:
Status Affected:
Description:
0x00≤I≤0x3F
ACC or I ACC
Z
The contents of the ACC register are OR’ed with the 8-bit immediate ‘I’. The result is placed
in the ACC register.
1
Cycles:
IOST
Load IOST Register
Syntax:
IOST R
Operands:
Operation:
Status Affected:
Description:
Cycles:
R = 0x06
ACC IOST register R
None
IOST register ‘R’ (R= 0x06) is loaded with the contents of the ACC register.
1
Web site: http://www.feeling-techcom.tw
Rev 1.00.003 Mar 02, 2017
Page 36 of 52, FM8PE53M
EELING
FM8PE53M
MOVAR
Move ACC to R
Syntax:
MOVAR R
Operands:
Operation:
Status Affected:
Description:
Cycles:
0x00≤R≤0x3F
ACC R
None
Move data from the ACC register to register ‘R’.
1
MOVIA
Move Immediate to ACC
MOVIA I
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
0x00≤I≤0xFF
I ACC
None
The 8-bit immediate ‘I’ is loaded into the ACC register. The don’t cares will assemble as 0s.
1
MOVR
Move R
Syntax:
MOVR R, d
Operands:
0x00≤R≤0x3F
d∈[0,1]
Operation:
R dest
Status Affected:
Description:
Z
The contents of register ‘R’ is moved to destination ‘d’. If ‘d’ is 0, destination is the ACC
register. If ‘d’ is 1, the destination is file register ‘R’. ‘d’ is 1 is useful to test a file register since
status flag Z is affected.
1
Cycles:
NOP
No Operation
NOP
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
None
No operation
None
No operation.
1
OPTION
Load OPTION Register
Syntax:
OPTION
Operands:
Operation:
Status Affected:
Description:
Cycles:
None
ACC OPTION
None
The content of the ACC register is loaded into the OPTION register.
1
RETFIE
Return from Interrupt, Set ‘GIE’ Bit
Syntax:
RETFIE
Operands:
Operation:
None
Top of Stack PC
1 GIE
Status Affected:
Description:
None
The program counter is loaded from the top of the stack (the return address). The ‘GIE’ bit is
set to 1. This is a 2-cycle instruction.
2
Cycles:
Web site: http://www.feeling-techcom.tw
Rev 1.00.003 Mar 02, 2017
Page 37 of 52, FM8PE53M
EELING
FM8PE53M
RETIA
Return with Immediate in ACC
Syntax:
RETIA I
Operands:
Operation:
0x00≤I≤0xFF
I ACC;
Top of Stack PC
None
Status Affected:
Description:
The ACC register is loaded with the 8-bit immediate ‘I’. The program counter is loaded from
the top of the stack (the return address). This is a 2-cycle instruction.
2
Cycles:
RETURN
Return from Subroutine
Syntax:
RETURN
Operands:
Operation:
Status Affected:
Description:
None
Top of Stack PC
None
The program counter is loaded from the top of the stack (the return address). This is a 2-
cycle instruction.
2
Cycles:
RLR
Rotate Left R through Carry
Syntax:
Operands:
RLR R, d
0x00≤R≤0x3F
d∈[0,1]
Operation:
R<7> C;
R<6:0> dest<7:1>;
C dest<0>
Status Affected:
Description:
C
The contents of register ‘R’ are rotated left one bit to the left through the Carry Flag. If ‘d’ is 0
the result is placed in the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’.
1
Cycles:
RRR
Rotate Right R through Carry
Syntax:
Operands:
RRR R, d
0x00≤R≤0x3F
d∈[0,1]
Operation:
C dest<7>;
R<7:1> dest<6:0>;
R<0> C
Status Affected:
Description:
C
The contents of register ‘R’ are rotated one bit to the right through the Carry Flag. If ‘d’ is 0
the result is placed in the ACC register. If ‘d’ is 1 the result is placed back in register ‘R’.
1
Cycles:
Web site: http://www.feeling-techcom.tw
Rev 1.00.003 Mar 02, 2017
Page 38 of 52, FM8PE53M
EELING
FM8PE53M
SLEEP
Enter SLEEP Mode
Syntax:
SLEEP
Operands:
Operation:
None
0x00 WDT;
0x00 WDT pre-scaler;
̅̅̅̅
1 TO;
̅̅̅̅
0 PD
̅̅̅̅ ̅̅̅̅
Status Affected:
Description:
TO, PD
̅̅̅̅
̅̅̅̅
Time-out status bit (TO) is set. The power-down status bit (PD) is cleared. The WDT is cleared.
The processor is put into SLEEP mode.
1
Cycles:
SBCAR
Syntax:
Subtract ACC from R with Carry
SBCAR R, d
Operands:
0x00≤R≤0x3F
d∈[0,1]
̅̅̅̅̅̅̅
Operation:
R + ACC + C dest
Status Affected:
Description:
C, DC, Z
Add the 2’s complement data of the ACC register from register ‘R’ with Carry. If ‘d’ is 0 the
result is stored in the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’.
1
Cycles:
SUBAR
Syntax:
Subtract ACC from R
SUBAR R, d
Operands:
0x00≤R≤0x3F
d∈[0,1]
Operation:
R - ACC dest
Status Affected:
Description:
C, DC, Z
Subtract (2’s complement method) the ACC register from register ‘R’. If ‘d’ is 0 the result is
stored in the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’.
1
Cycles:
SUBIA
Subtract ACC from Immediate
Syntax:
SUBIA I
Operands:
Operation:
Status Affected:
Description:
0x00≤I≤0xFF
I - ACC ACC
C, DC, Z
Subtract (2’s complement method) the ACC register from the 8-bit immediate ‘I’. The result
is placed in the ACC register.
1
Cycles:
SWAPR
Syntax:
Swap nibbles in R
SWAPR R, d
Operands:
0x00≤R≤0x3F
d∈[0,1]
Operation:
R<3:0> dest<7:4>;
R<7:4> dest<3:0>
Status Affected:
Description:
None
The upper and lower nibbles of register ‘R’ are exchanged. If ‘d’ is 0 the result is placed in
ACC register. If ‘d’ is 1 the result in placed in register ‘R’.
1
Cycles:
Web site: http://www.feeling-techcom.tw
Rev 1.00.003 Mar 02, 2017
Page 39 of 52, FM8PE53M
EELING
FM8PE53M
XORAR
Exclusive OR ACC with R
Syntax:
XORAR R, d
Operands:
0x00≤R≤0x3F
d∈[0,1]
Operation:
Status Affected:
Description:
ACC xor R dest
Z
Exclusive OR the contents of the ACC register with register ’R’. If ‘d’ is 0 the result is stored
in the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’.
1
Cycles:
XORIA
Exclusive OR Immediate with ACC
Syntax:
XORIA I
Operands:
Operation:
Status Affected:
Description:
0x00≤I≤0xFF
ACC xor I ACC
Z
The contents of the ACC register are XOR’ed with the 8-bit immediate ‘I’. The result is placed
in the ACC register.
1
Cycles:
Web site: http://www.feeling-techcom.tw
Rev 1.00.003 Mar 02, 2017
Page 40 of 52, FM8PE53M
EELING
FM8PE53M
4.0 ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Conditions
-
Min.
0
Typ.
-
Max.
70
Unit
°C
Ambient Operating
Temperature
Store Temperature
DC Supply Voltage
Input Voltage with respect to
Ground
-
-
-65
0
-
-
150
6.0
°C
V
VDD
-
-0.3
-
VDD+0.3
V
HBM (Human Body Mode)
MM (Machine Mode)
Soldering, 10 Sec
-
-
-
2.0
200
-
-
-
KV
V
ESD Susceptibility
Lead Temperature
250
°C
4.1 PACKAGE IR Re-flow Soldering Curve
250 5
10 1 sec
150 10
90 30 sec
2 ~ 5 / sec
2 ~ 5 / sec
Time
5.0 RECOMMENDED OPERATING CONDITIONS
Symbol
VDD
Parameter
DC Supply Voltage
Operating Temperature
Conditions
Min.
2.0
0
Typ.
Max.
5.5
Unit
V
-
-
-
-
70
°C
Web site: http://www.feeling-techcom.tw
Rev 1.00.003 Mar 02, 2017
Page 41 of 52, FM8PE53M
EELING
FM8PE53M
6.0 ELECTRICAL CHARACTERISTICS
6.1 AC Characteristics
Ta=25°C
Test Conditions
Conditions
Symbol
FHF
Description
HF Oscillation range
XT Oscillation range
LF oscillation range
ERC Oscillation range
ERIC Oscillation range
Min.
Typ.
Max.
Unit
MHZ
MHZ
KHZ
MHZ
MHZ
KHZ
MHZ
MHZ
MHZ
VDD
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
4
4
-
20
20
20
20
32
32
10
18
8
HF mode
-
0.455
0.455
32
-
FXT
XT mode
-
-
FLF
LF mode
32
-
DC
DC
DC
DC
-3%
-3%
-3%
-3%
-3%
-3%
-3%
-3%
-
-
FERC
FERIC
ERC mode
-
-
ERIC mode
-
16
+3%
+3%
+3%
+3%
+3%
+3%
+3%
+3%
-
455
455
1
455KHZ IRC mode
1MHZ IRC mode
4MHZ IRC mode
8MHZ IRC mode
1
FIRC
Internal RC Oscillation range
4
4
8
8
5.72
4.36
23.08
17.6
92.9
70.54
368.37
280.78
WDT=4.5mS,
Pre-scaler rate=1:1
WDT=18mS,
Pre-scaler rate=1:1
WDT=72mS,
Pre-scaler rate=1:1
WDT=288mS,
-
-
-
-
-
-
TWDT
WDT period time
mS
-
-
-
-
-
-
Pre-scaler rate=1:1
-
-
Note:1. In the ERIC mode, to maintain the accuracy of the internal RC oscillator frequency, a 300pF ~ 0.1uF
decoupling capacitor should be connected between OSCI and VSS and located as close to the device as
possible.
2. At any time, a 0.1μF decoupling capacitor should be connected between VDD and VSS and device as
close as possible.
6.2 DC Characteristics
Ta=25°C
Under Operating Conditions, at two clock instruction cycles and WDT & LVDT are disable, I/O output float.
Test Conditions
Symbol
Description
Min.
Typ.
Max.
Unit
V
VDD
3V
5V
3V
5V
3V
5V
3V
5V
Conditions
-
1.41
-
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
Input high voltage, I/O Ports
With Schmitt-trigger
2.2
VIH1
-
-
-
-
-
-
1.36
1.98
1.26
1.74
1.2
Input high voltage, RSTB,
T0CKI Pins
With Schmitt-trigger
Input high voltage, I/O Ports
Without Schmitt-trigger
Without Schmitt-trigger
VIH2
V
Input high voltage, RSTB,
T0CKI Pins
1.69
Web site: http://www.feeling-techcom.tw
Rev 1.00.003 Mar 02, 2017
Page 42 of 52, FM8PE53M
EELING
FM8PE53M
Test Conditions
Symbol
VIL1
Description
Min.
Typ.
Max.
Unit
VDD
3V
5V
3V
5V
3V
5V
3V
5V
-
Conditions
VSS
0.98
-
-
Input low voltage with
Schmitt-trigger, I/O Ports
Input low voltage, RSTB,
T0CKI Pins
With Schmitt-trigger
VSS
0.9
V
VSS
0.96
1.21
1.12
1.51
1.12
1.56
3.6
-
With Schmitt-trigger
VSS
-
VSS
-
Input low voltage, I/O Ports
Without Schmitt-trigger
Without Schmitt-trigger
VSS
-
VIL2
V
V
VSS
-
Input low voltage, RSTB,
T0CKI Pins
VSS
-
LVDT=3.6V
LVDT=2.6V
LVDT=2.4V
LVDT=2.2V
LVDT=2.0V
LVDT=1.8V
3.06
4.14
-
2.21
2.6
2.99
-
2.04
2.4
2.76
VLVDT
LVDT voltage
-
1.87
2.2
2.53
-
1.7
2.0
2.3
-
1.6
1.8
2.07
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
-
1.5
-
1.67
4.37
9.46
23.17
9.33
22.79
22.69
74.07
12.58
42.24
1.13
0.42
1.42
0.46
1.53
0.49
1.68
0.52
1.76
0.58
1.92
0.53
3.67
<1
-
-
IOH
I/O Ports Drive current
VOH=0.9VDD
mA
mA
-
I/O Ports Sink current
(Without IOB3 Pin)
VOL=0.1VDD
10
-
-
IOL
-
IOB3 Pin Sink current
I/O Ports Pull-high current
Pull-low current
VOL=0.1VDD
-
-
-
-
IPH
IPL
Input pin at VSS
Input pin at VDD
uA
uA
63
-
93
-
30
-
60
-
5V LVDT=3.6V
3V
-
-
LVDT=2.6V
5V
-
-
3V
-
-
LVDT=2.4V
5V
-
-
ILVDT
LVDT current
3V
-
-
uA
LVDT=2.2V
5V
-
-
3V
-
-
LVDT=2.0V
5V
-
-
3V
-
-
LVDT=1.8V
5V
-
-
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
-
-
Sleep mode, Pre-scaler
rate=1:256
IWDT
ISB
WDT current
uA
uA
1
-
7
-
Sleep mode (Power down)
current
-
-
<1
0.6
1
-
-
IDD1
IDD2
IDD3
IDD4
Operating current
Operating current
Operating current
Operating current
IRC 8MHZ, 2T
IRC 4MHZ, 2T
IRC 1MHZ, 2T
IRC 455KHZ, 2T
mA
mA
mA
mA
1.15
0.33
0.63
0.12
0.25
0.08
0.19
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Web site: http://www.feeling-techcom.tw
Rev 1.00.003 Mar 02, 2017
Page 43 of 52, FM8PE53M
EELING
FM8PE53M
6.3 ELECTRICAL CHARACTERISTICS Typical charts of FM8PE56M
6.3.1
IRC 4MHZ vs. Temperature
1.00%
Avg-5V
Avg-3V
0.50%
0.00%
-10
0
10
20
25
30
30
30
40
40
40
50
50
50
60
60
60
70
70
70
80
-0.50%
-1.00%
Temperature
Note: Curves are for design reference only.
6.3.2
IRC 8MHZ vs. Temperature
1.00%
Avg-5V
Avg-3V
0.50%
0.00%
-10
0
10
20
25
80
-0.50%
-1.00%
Temperature
Note: Curves are for design reference only.
6.3.3
IRC 1MHZ vs. Temperature
1.00%
Avg-5V
Avg-3V
0.50%
0.00%
-10
0
10
20
25
80
-0.50%
-1.00%
Temperature
Note: Curves are for design reference only.
Web site: http://www.feeling-techcom.tw
Rev 1.00.003 Mar 02, 2017
Page 44 of 52, FM8PE53M
EELING
FM8PE53M
6.3.4
IRC 455KHZ vs. Temperature
2.00%
Avg-5V
Avg-3V
1.00%
0.00%
-10
0
10
20
25
30
40
50
60
70
80
-1.00%
-2.00%
Temperature
Note: Curves are for design reference only.
6.3.5
IRC 4 MHZ vs. Supply Voltage (Ta=25°C)
2.00%
1.00%
0.00%
1.8
2
2.2 2.4 2.6 2.8
3
3.2 3.4 3.6 3.8
4
4.2 4.4 4.6 4.8
5
5.2 5.4 5.6 5.8
6
-1.00%
-2.00%
-3.00%
-4.00%
4M HV
4M LV
Voltage
Note: Curves are for design reference only.
6.3.6
IRC 8 MHZ vs. Supply Voltage (Ta=25°C)
4.00%
2.00%
0.00%
1.8
2
2.2 2.4 2.6 2.8
3
3.2 3.4 3.6 3.8
4
4.2 4.4 4.6 4.8
5
5.2 5.4 5.6 5.8
8M HV
6
-2.00%
-4.00%
-6.00%
-8.00%
-10.00%
8M LV
Voltage
Note: Curves are for design reference only.
Web site: http://www.feeling-techcom.tw
Rev 1.00.003 Mar 02, 2017
Page 45 of 52, FM8PE53M
EELING
FM8PE53M
6.3.7
IRC 1 MHZ vs. Supply Voltage (Ta=25°C)
3.00%
2.00%
1.00%
0.00%
1.8
2
2.2 2.4 2.6 2.8
3
3.2 3.4 3.6 3.8
Voltage
4
4.2 4.4 4.6 4.8
5
5.2 5.4 5.6 5.8
1M HV
6
-1.00%
-2.00%
-3.00%
1M LV
Note: Curves are for design reference only.
6.3.8
IRC 455 KHZ vs. Supply Voltage (Ta=25°C)
3.00%
2.00%
1.00%
0.00%
1.8
2
2.2 2.4 2.6 2.8
3
3.2 3.4 3.6 3.8
Voltage
4
4.2 4.4 4.6 4.8
5
5.2 5.4 5.6 5.8
6
-1.00%
-2.00%
-3.00%
455K HV
455K LV
Note: Curves are for design reference only.
6.3.9
Low Voltage Detect (LVDT=2.0V) vs. Temperature
2.50
Avg-2.0V
2.00
1.50
1.00
0.50
0.00
-10
0
10
20
25
30
40
50
60
70
80
Temperature
Note: Curves are for design reference only.
Web site: http://www.feeling-techcom.tw
Rev 1.00.003 Mar 02, 2017
Page 46 of 52, FM8PE53M
EELING
FM8PE53M
6.3.10 Low Voltage Detect (LVDT=3.6V) vs. Temperature
4.00
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0.00
Avg-3.6V
-10
0
10
20
25
30
40
40
40
50
50
50
60
60
60
70
70
70
80
Temperature
Note: Curves are for design reference only.
6.3.11 Low Voltage Detect (LVDT=1.8V) vs. Temperature
2.00
Avg-1.8V
1.50
1.00
0.50
0.00
-10
0
10
20
25
30
80
Temperature
Note: Curves are for design reference only.
6.3.12 Low Voltage Detect (LVDT=2.2V) vs. Temperature
2.50
Avg-2.2V
2.00
1.50
1.00
0.50
0.00
-10
0
10
20
25
30
80
Temperature
Note: Curves are for design reference only.
Web site: http://www.feeling-techcom.tw
Rev 1.00.003 Mar 02, 2017
Page 47 of 52, FM8PE53M
EELING
FM8PE53M
6.3.13 Low Voltage Detect (LVDT=2.4V) vs. Temperature
3.00
2.50
2.00
1.50
1.00
0.50
0.00
Avg-2.4V
-10
0
10
20
25
30
40
50
60
70
80
Temperature
Note: Curves are for design reference only.
6.3.14 Low Voltage Detect (LVDT=2.6V) vs. Temperature
3.00
2.50
2.00
1.50
1.00
0.50
0.00
Avg-2.6V
-10
0
10
20
25
30
40
50
60
70
80
Temperature
Note: Curves are for design reference only.
6.3.15 WDT 4.5mS, 18mS, 72mS and 288mS Reset time vs. Temperature
40.00%
30.00%
20.00%
10.00%
0.00%
-10
0
10
20
25
30
40
50
60
70
80
-10.00%
-20.00%
-30.00%
Avg-5V
Avg-3V
Temperature
Note: Curves are for design reference only.
Web site: http://www.feeling-techcom.tw
Rev 1.00.003 Mar 02, 2017
Page 48 of 52, FM8PE53M
EELING
FM8PE53M
6.3.16 WDT 4.5mS, 18mS, 72mS and 288mS Reset time vs. Supply Voltage (Ta=25°C)
140.00%
120.00%
100.00%
80.00%
60.00%
40.00%
20.00%
0.00%
WDT-Avg
1.8
2
2.2 2.4 2.6 2.8
3
3.2 3.4 3.6 3.8
Voltage
4
4.2 4.4 4.6 4.8
5
5.2 5.4 5.6 5.8
6
-20.00%
Note: Curves are for design reference only.
Web site: http://www.feeling-techcom.tw
Rev 1.00.003 Mar 02, 2017
Page 49 of 52, FM8PE53M
EELING
FM8PE53M
7.0 PACKAGE DIMENSION
7.1 14-PIN PDIP
D
SEATING PLANE
0.018typ.
0.060typ.
0.100typ.
Dimension In Inches
Symbols
Min
Nom
-
Max
0.210
-
A
A1
A2
D
-
0.015
0.125
0.735
-
0.130
0.750
0.300 BSC.
0.250
0.130
0.355
7°
0.135
0.775
E
E1
L
0.245
0.115
0.335
0°
0.255
0.150
0.375
15°
eB
θ°
Web site: http://www.feeling-techcom.tw
Rev 1.00.003 Mar 02, 2017
Page 50 of 52, FM8PE53M
EELING
FM8PE53M
7.2 14-PIN SOP 150mil
View "A"
C
D
View "A"
GAUGE PLANE
SEATING PLANE
b
θo
L
0.10
e
Dimension In MM
Symbols
Min
Nom
Max
1.75
0.25
-
A
A1
A2
b
-
-
0.10
1.25
0.31
0.10
-
-
-
0.51
0.25
C
-
D
8.65BSC
6.00BSC
3.90BSC
1.27BSC
-
E
E1
e
L
0.40
0.25
0o
1.27
0.50
8o
H
θ
-
Web site: http://www.feeling-techcom.tw
Rev 1.00.003 Mar 02, 2017
Page 51 of 52, FM8PE53M
EELING
FM8PE53M
8.0 ORDERING INFORMATION
OTP Type MCU
FM8PE53MP
Package Type Pin Count Package Size
MOQ
MSL Sample Stock
PDIP
SOP
14
14
300mil
150mil
3,000EA/Tube
3
3
Available
Available
3,000EA/Tube
3,000EA/Reel
FM8PE53MD
Web site: http://www.feeling-techcom.tw
Rev 1.00.003 Mar 02, 2017
Page 52 of 52, FM8PE53M
相关型号：
©2020 ICPDF网 联系我们和版权申明