FM8PE68BBG [FEELING]
OTP-Based 8-Bit Microcontroller with LCD Driver;
| 型号： | FM8PE68BBG |
| 厂家： | 
Feeling Technology |
| 描述： | OTP-Based 8-Bit Microcontroller with LCD Driver CD 微控制器 |
| 文件： | 总81页 (文件大小：3611K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EELING
OTP-Based 8-Bit Microcontroller wCD Driver
FM8PE68B
Devices Included in this Data Sheet:
FM8PE68BA/BB: 64-pin OTP device
FM8PE68BC: 44-pin OTP device
FEATURES
Only 49 single word instructions.
4K Word on chip OTP.
All OTP area GOTO/FGOTO instruction.
All OTP area subroutine CALL/FCALL instruction.
Totally 272 x 8 bits on chip general purpose registers (SRAM):
- 144 bytes general purpose register.
- 128 bytes on-chip data RAM.
8-level deep hardware stack.
Direct, indirect addressing modes for data accessing.
One 8-bit real time clock/counter (Timer0) with 8-bit programmable pre-scaler.
Four sets of 8-bit auto reload counter/timer can be used as IROUT/PWM generator or interrupt sources:
- Counter 1: independent counter.
- Counter 2: High Pulse Width Timer, and Low Pulse Width Timer shared with IR function.
One IROUT/PWM generator.
LCD driver with 4(common) x 32(segment) pixels; 1/3, 1/2 bias and 1/4, 1/3, 1/2 duty selection.
3 channels of 15-bit resolution Resistor to Frequency Converter (RFC) output.
Internal Power-on Reset (POR).
Built-in Low Voltage Detector (LVD) for Brown-out Reset (BOR).
Power-up Reset Timer (PWRT) and Oscillator Start-up Timer(OST).
On chip Watchdog Timer (WDT) with internal oscillator and soft-ware watch-dog enable/disable control.
Four I/O ports PORTA, PORTB, PORTC and PORTD with independent direction control.
Two output only ports PORTE and PORTF.
Soft-ware I/O pull-high/pull-down or open-drain control.
Seven internal interrupt source: Timer0, Counter1, Counter2, High-pulse width timer, Low-pulse width timer, RFC
and Fs divider; Three external interrupt source: INT0 pin, INT1 pin and Port B / Port D input status change.
Wake-up from SLEEP/IDLE by Port B/Port D input change.
Operation modes:
- Normal mode: CPU operate on high frequency main-oscillator.
- Green mode: CPU operate on low frequency sub-oscillator.
- Idle mode: CPU idle, LCD display remains working.
- Sleep mode: whole chip stop working.
Dual clock Operation: main-oscillator and sub-oscillator.
Selectable main-oscillator options:
- ERIC: External Resistor/Internal Capacitor Oscillator.
- XT: Crystal/Resonator Oscillator.
- LF: Low Frequency Crystal/Resonator Oscillator.
- PLL: Phase lock loop.
Selectable sub-oscillator options:
- ERIC: External Resistor/Internal Capacitor Oscillator.
- LF: Low Frequency Crystal Oscillator.
Wide-operating voltage range:
- OTP: 2.3V to 5.5V.
This datasheet containn. Feeling Technology reserves the rights to modify the product specification without notice.
No liability is assumed as a rethis product. No rights under any patent accompany the sales of the product.
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 1 of 81, FM8PE68B
EELING
FM8PE68B
GENERAL DESCRIPTION
The FM8PE68B is a family of low-cost, high speed, OTP-based 8-bit CMOS microcontrollers. It employs a RISC
architecture with only 49 instructions. All instructions are single cycle except for program branches which take two
cycles. The easy to use and easy to remember instruction set reduces development time significantly.
The FM8PE68B consists of Power-on Reset (POR), Brown-out Reset (BOR), Power-up Reset Timer (PWRT),
Oscillator Start-up Timer(OST), Watchdog Timer, Data RAM, OTP/ROM, SRAM, LCD driver, IROUT function,
tristate I/O port, I/O pull-high/open-drain/pull-down control, Power saving SLEEP mode, real time programmable
clock/counter, Interrupt, Wake-up from SLEEP mode, RFC, and Code Protection for OTP products. There are
three oscillator configurations to choose from, including the power-saving LP (Low Power) oscillator and cost saving
RC oscillator.
The FM8PE68B address 4K of program memory.
The FM8PE68B can directly or indirectly address its register files and data memory. All special function registers
including the program counter are mapped in the data memory.
BLOCK DIAGRAM
PORTA
PORTB
PORTC
PORTD
RFC
Oscillator
Circuit
8-level
STACK
SRAM
FSR
Watchdog
Timer
Program
Counter
Instruction
Decoder
ALU
OTP ROM
TMR0
Interrupt
Control
PORTE
PORTF
COM
Accumulator
Counter 1/2,
High/Low-pulse
Width Timer
LCD
Controller
IR/PWM
DATA BUS
Control
128-bit
shadow
Control RAM
128-Byte
SRAM
Segment
Interrupt
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 2 of 81, FM8PE68B
EELING
FM8PE68B
PIN CONNECTION
QFP64 (14x20)
IOF7/SEG15
IOF6/SEG14
IOF5/SEG13
IOF4/SEG12
IOF3/SEG11
IOF2/SEG10
IOF1/SEG9
IOF0/SEG8
IOE7/SEG7
1
2
3
4
5
6
7
8
9
51 IOD5/SEG29/RFC1
50 IOD6/SEG30/RFC2
49 NC
48 NC
47 NC
46 IOD7/SEG31/CX
45 IOB7
44 IOB6
43 IOB5
FM8PE68BAF
IOE6/SEG6 10
IOE5/SEG5 11
IOE4/SEG4 12
IOE3/SEG3 13
IOE2/SEG2 14
IOE1/SEG1 15
IOE0/SEG0 16
COM3 17
42 IOB4
41 IOB3
40 IOB2
39 IOB1
38 IOB0
37 IOA7/IROUT
36 NC
35 NC
COM2 18
34 IOA6/T0CKI
33 IOA5/INT1
COM1 19
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 3 of 81, FM8PE68B
EELING
FM8PE68B
LQFP64 (10x10) / LQFP64 (7x7)
IOF7/SEG15
IOF6/SEG14
IOF5/SEG13
IOF4/SEG12
IOF3/SEG11
IOF2/SEG10
IOF1/SEG9
IOF0/SEG8
IOE7/SEG7
1
2
3
4
5
6
7
8
9
48 NC
47 NC
46 IOD7/SEG31/CX
45 IOB7
44 IOB6
43 IOB5
42 IOB4
41 IOB3
FM8PE68BAG/BBG
40 IOB2
IOE6/SEG6 10
IOE5/SEG5 11
IOE4/SEG4 12
IOE3/SEG3 13
IOE2/SEG2 14
IOE1/SEG1 15
IOE0/SEG0 16
39 IOB1
38 IOB0
37 IOA7/IROUT
36 NC
35 NC
34 IOA6/T0CKI
33 IOA5/INT1
QFP44 (10x10) / LQFP44 (10x10)
IOC0/SEG16
IOF6/SEG14
IOF5/SEG13
IOF4/SEG12
IOF3/SEG11
COM3
1
33 IOD4/SEG28
2
3
4
5
6
7
8
9
32 IOB7
31 IOB6
30 IOB5
29 IOB4
FM8PE68BCF/BCG
28 IOB3
COM2
27 IOB2
COM1
26 IOB1
COM0
25 IOB0
CUP2 10
CUP1 11
24 IOA7/IROUT
23 IOA6/T0CKI
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 4 of 81, FM8PE68B
EELING
FM8PE68B
PIN DESCRIPTIONS
Name
I/O
I/O
Description
Bi-direction I/O pin.
IOA4/INT0
External interrupt input 0, the trigger edge is controlled by INT0EDG bit.
Bi-direction I/O pin.
External interrupt input 1 with falling edge trigger.
Bi-direction I/O pin.
IOA5/INT1
I/O
I/O
IOA6/T0CKI
Clock input to Timer0.
Bi-direction I/O pin.
IR mode output pin.
IOA7/IROUT I/O
IOB0 ~ IOB7 I/O Bi-direction I/O port with system wake-up function.
IOC0 ~ IOC7 I/O Bi-direction I/O port.
IOD0 ~ IOD7 I/O Bi-direction I/O port with system wake-up function.
IOE0 ~ IOE7
IOF0 ~ IOF7
COM0 ~ COM3
SEG0 ~ SEG31
VLCD1
O
O
O
O
-
Output only pins.
Output only pins.
LCD common output pins.
LCD segment output pins.
One of LCD bias voltage.
VLCD2
-
One of LCD bias voltage.
CUP1
-
Connect capacitors for LCD bias voltage.
Connect capacitors for LCD bias voltage.
The RC oscillator network output of RFC module
The RC oscillator network input of RFC module
System clear (RESET) input. This pin is an active low RESET to the device.
Main Oscillator:
CUP2
-
RFC0 ~ RFC2
CX
O
I
RSTB
I
- X’tal type: Oscillator crystal input.
- ERIC type: Clock input of RC oscillator.
OSCI
I
- PLL type: Connect 0.01uF capacitor to VSS
.
Main Oscillator:
OSCO
XIN
O
I
- X’tal type: Oscillator crystal output.
-ERIC and PLL type: Instruction clock output.
Sub-Oscillator:
- X’tal type: 32.768KHZ Oscillator crystal input.
- ERIC type: Clock input of RC oscillator.
Sub-Oscillator:
XOUT
O
- X’tal type: 32.768KHZ Oscillator crystal output.
- ERIC type: Instruction clock output.
Positive supply
VDD
VSS
-
-
Ground
Legend: I=input, O=output, I/O=input/output
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 5 of 81, FM8PE68B
EELING
FM8PE68B
1.0 MEMORY ORGANIZATION
FM8PE68B memory is organized into program memory and data memory.
1.1 Program Memory Organization
The FM8PE68 have an 12-bit Program Counter capable of addressing a 4K program memory space.
The RESET vector for the FM8PE68B is at 0x000.
The H/W interrupt vector is at 0x003/0x006/0x009/0x00C/0x00F/0x012/0x015/0x018/0x01E/0x021 based on
different H/W interrupt event. And the S/W interrupt vector is at 0x002.
FM8PE68B has program memory size greater than 1K words, but the CALL and GOTO instructions only have a
10-bit address range. This 10-bit address range allows a branch within a 1K program memory page size. To allow
CALL and GOTO instructions to address the entire 4K program memory address range for FM8PE68B, there is
another two bits to specify the program memory page. This paging bit comes from the STATUS<6:5> bits. When
doing a CALL or GOTO instruction, the user must ensure that page bit STATUS<6:5> are programmed so that the
desired program memory page is addressed. When one of the return instructions is executed, the entire 12-bit PC
is POPed from the stack. Therefore, manipulation of the STATUS<6:5> is not required for the return instructions.
User can use “PAGE” instruction to change memory page directly and maintains the program memory page.
Otherwise, user can use “FCALL(far call)/FGOTO(far goto)” instructions to program user's code directly.
Figure 1.1: Program Memory Map and STACK
PC<11:0>
Stack 1
:
Stack 8
0xFFF
:
:
:
:
:
0x021 Sub-oscillator (Fs) divider overflow Interrupt Vector
:
0x01E
RFC Interrupt Vector
:
:
0x018 Port B, Port D input status change Interrupt Vector
:
:
0x015
LP timer underflow Interrupt Vector
:
:
0x012
HP timer underflow Interrupt Vector
:
:
0x00F
C2 timer underflow Interrupt Vector
:
:
0x00C
C1 timer underflow Interrupt Vector
:
:
0x009
:
External INT1 pin Interrupt Vector
:
0x006
:
External INT0 pin Interrupt Vector
:
TMR0 overflow Interrupt Vector
S/W Interrupt Vector
:
0x003
0x002
:
0x000
Reset Vector
FM8PE68B
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 6 of 81, FM8PE68B
EELING
FM8PE68B
1.2 Data Memory Organization
Data memory is composed of Special Function Registers and General Purpose Registers.
The General Purpose Registers are accessed either directly or indirectly through the FSR register.
The Special Function Registers are registers used by the CPU and peripheral functions to control the operation of
the device.
In FM8PE68B, the data memory is partitioned into four banks. Switching between these banks requires the RP1
and RP0 bits in the FSR register to be configured for the desired bank. User can use “BANK” instruction to change
the data memory bank.
Table 1.1: Registers File Map for FM8PE68B
Description
FSR<7:6>
0 0
Bank 0
INDF
TMR0
PCL
0 1
Bank 1
1 0
Bank 2
1 1
Bank 3
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
STATUS
FSR
Memory back to address in Bank 0
PORTA
PORTB
PORTC
PORTD
LCDCON
LCDA
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
IOSTA
IOSTB
IOSTC
IOSTD
DRAMA
DRAMD
C1PR
C2PR
HPPR
LPPR
INTEN
PORTE
LCDCON
LCDA
LCDD
CNTCON
SYSCON
IRCON
PORTE
PORTF
RFCCON
RFCDL
RFCDH
DIVCON
PORTF
RFCCON
RFCDL
RFCDH
DIVCON
LCDD
CNTCON
SYSCON
IRCON
INTFLAG
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
SEGCON
WUCON
T0CON
WDTCON
C12CON
HLPCON
BPHCON
BODCON
DPHCON
BPDCON
INTEN1
0x10
|
0x1F
General
Purpose
Registers
Memory back to address in Bank 0
0x20
|
0x3F
General
Purpose
Registers
General
Purpose
Registers
General
Purpose
Registers
General
Purpose
Registers
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 7 of 81, FM8PE68B
EELING
FM8PE68B
Table 1.2: Operational Registers Map
Address
Name
B7
B6
B5
B4
B3
B2
B1
B0
Unbanked
0x00 (r/w)
0x01 (r/w)
0x02 (r/w)
0x03 (r/w)
0x04 (r/w)
0x05 (r/w)
0x06 (r/w)
0x07 (r/w)
0x08 (r/w)
INDF
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PORTD
Uses contents of FSR to address data memory (not a physical register)
8-bit real-time clock/counter
Low order 8 bits of PC
̅̅̅̅
TO
̅̅̅̅
PD
*
RP1
PG1
RP0
PG0
Z
DC
C
Indirect data memory address pointer
IOA7
IOB7
IOC7
IOD7
IOA6
IOB6
IOC6
IOD6
IOA5
IOB5
IOC5
IOD5
IOA4
IOB4
IOC4
IOD4
-
-
*
-
IOB3
IOC3
IOD3
IOB2
IOC2
IOD2
IOB1
IOC1
IOD1
IOB0
IOC0
IOD0
Bank 0, Bank 2
0x09 (r/w)
0x0A (r/w)
0x0B (r/w)
0x0C (r/w)
0x0D (r/w)
0x0E (r/w)
LCDCON
LCDA
LCDD
CNTCON
SYSCON
IRCON
BIAS
0
0
0
0
DUTY1
0
0
0
PLLCK2
HF
DUTY0
0
0
LCDEN
LCDA4
0
0
PLLCK0
-
-
TYPE
LCDA2
LCDD2
HPEN
LCDBF1
ET0CKI
LCDF1
LCDA1
LCDD1
C2EN
LCDBF0
EINT1
LCDF0
LCDA0
LCDD0
C1EN
CPUS
EINT0
LCDA3
LCDD3
LPEN
IDLE
EIROUT
0
PLLCK1
LGP
IRE
Bank 1, Bank 3
0x09 (r/w)
0x0A (r/w)
0x0B (r/w)
0x0C (r)
0x0D (r)
0x0E (r/w)
Unbanked
PORTE
IOE7
IOF7
RFCON
RFCD7
RFCOV
DIVON
IOE6
IOF6
START
RFCD6
RFCD14
DIVRST
IOE5
IOF5
RFCIF
RFCD5
RFCD13
DIVIF
IOE4
IOF4
RFCMOD
RFCD4
RFCD12
-
IOE3
IOF3
-
RFCD3
RFCD11
-
IOE2
IOF2
-
RFCD2
RFCD10
-
IOE1
IOF1
RFCS1
RFCD1
RFCD9
-
IOE0
IOF0
RFCS0
RFCD0
RFCD8
-
PORTF
RFCCON
RFCDL
RFCDH
DIVCON
0x0F (r/w) INTFLAG
PBDIF
LPIF
HPIF
C2IF
C1IF
INT1IF
INT0IF
T0IF
Legend: - = unimplemented, read as ‘0’, * = unimplemented, read as ‘1’, 0 = Not used, must fix to ‘0’.
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 8 of 81, FM8PE68B
EELING
FM8PE68B
Table 1.3: The Registers Controlled by IOST / IOSTR Instructions
Address
Name
IOSTA
IOSTB
IOSTC
IOSTD
DRAMA
DRAMD
C1PR
B7
IOSTA7
IOSTB7
IOSTC7
IOSTD7
0
RAMD7
C1PR7
C2PR7
HPPR7
LPPR7
PBDIE
IOFHS
IRSC
INT0EDG
*
C2CS
LPCS
PHB7
ODB7
PHD7
PDB7
-
B6
IOSTA6
IOSTB6
IOSTC6
IOSTD6
RAMA6
RAMD6
C1PR6
C2PR6
HPPR6
LPPR6
LPIE
IOFLS
*
B5
IOSTA5
IOSTB5
IOSTC5
IOSTD5
RAMA5
RAMD5
C1PR5
C2PR5
HPPR5
LPPR5
HPIE
IOEHS
*
B4
IOSTA4
IOSTB4
IOSTC4
IOSTD4
RAMA4
RAMD4
C1PR4
C2PR4
HPPR4
LPPR4
C2IE
IOELS
*
B3
-
B2
B1
B0
0x05 (r/w)
0x06 (r/w)
0x07 (r/w)
0x08 (r/w)
0x09 (r/w)
0x0A (r/w)
0x0B (r/w)
0x0C (r/w)
0x0D (r/w)
0x0E (r/w)
0x0F (r/w)
0x15 (r/w)
0x16 (r/w)
0x17 (r/w)
0x18 (r/w)
0x19 (r/w)
0x1A (r/w)
0x1B (r/w)
0x1C (r/w)
0x1D (r/w)
0x1E (r/w)
0x1F (r/w)
-
-
-
IOSTB3
IOSTC3
IOSTD3
RAMA3
RAMD3
C1PR3
C2PR3
HPPR3
LPPR3
C1IE
IODHS
/WUEDH
T0PS3
WDTEN
C1CS
IOSTB2
IOSTC2
IOSTD2
RAMA2
RAMD2
C1PR2
C2PR2
HPPR2
LPPR2
INT1IE
IODLS
/WUEDL
T0PS2
WDTPS2
C1PS2
HPPS2
PHB2
IOSTB1
IOSTC1
IOSTD1
RAMA1
RAMD1
C1PR1
C2PR1
HPPR1
LPPR1
INT0IE
IOCHS
/WUEBH
T0PS1
WDTPS1
C1PS1
HPPS1
PHB1
IOSTB0
IOSTC0
IOSTD0
RAMA0
RAMD0
C1PR0
C2PR0
HPPR0
LPPR0
T0IE
IOCLS
/WUEBL
T0PS0
WDTPS0
C1PS0
HPPS0
PHB0
C2PR
HPPR
LPPR
INTEN
SEGCON
WUCON
T0CON
WDTCON
C12CON
HLPCON
BPHCON
BODCON
DPHCON
BPDCON
INTEN1
GIE
*
T0CS
*
T0SE
*
C2PS2
LPPS2
PHB6
ODB6
PHD6
PDB6
-
C2PS1
LPPS1
PHB5
ODB5
PHD5
PDB5
-
C2PS0
LPPS0
PHB4
ODB4
PHD4
PDB4
-
HPCS
PHB3
ODB3
PHD3
PDB3
-
ODB2
PHD2
PDB2
DIVIE
ODB1
PHD1
PDB1
RFCIE
ODB0
PHD0
PDB0
-
Legend: - = unimplemented, read as ‘0’, * = unimplemented, read as ‘1’, 0 = Not used, must fix to ‘0’.
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 9 of 81, FM8PE68B
EELING
FM8PE68B
2.0 FUNCTIONAL DESCRIPTIONS
2.1 Operational Registers
2.1.1
INDF (Indirect Addressing Register)
Read/Write-POR
R/W-x
B7
R/W-x
B6
R/W-x
B5
R/W-x
B4
R/W-x
B3
R/W-x
B2
R/W-x
B1
R/W-x
B0
Address
0x00
Name
INDF
Uses contents of FSR to address data memory (not a physical register)
Legend: x = unknown, more bits default state, please refer to Table 2.9.
The INDF Register is not a physical register. Any instruction accessing the INDF register can actually access the
register pointed by FSR Register. Reading the INDF register itself indirectly (FSR=”0”) will read 00h. Writing to the
INDF register indirectly results in a no-operation (although status bits may be affected).
The bits 5-0 of FSR register are used to select up to 64 registers (address: 0x00 ~ 0x3F).
In FM8PE68B, the data memory is partitioned into four banks. Switching between these banks requires the RP1
and RP0 bits in the FSR register to be configured for the desired bank. The lower locations of each bank are
reserved for the Special Function Registers. Above the Special Function Registers are General Purpose Registers.
All Special Function Registers and some of General Purpose Registers from other banks are mirrored in bank 0 for
code reduction and quicker access.
Accessed Bank
RP1:RP0
0
1
2
3
0
0
1
1
0
1
0
1
Example 2.1: INDIRECT ADDRESSING
Register file 38 contains the value 0x10
Register file 39 contains the value 0x0A
Load the value 38 into the FSR Register
A read of the INDF Register will return the value of 0x10
Increment the value of the FSR Register by one (@FSR=0x39)
A read of the INDF register now will return the value of 0x0A.
Figure 2.1: Direct/Indirect Addressing for FM8PE68B
Direct Addressing
Indirect Addressing
From FSR register 0
RP1:RP0
5
From opcode
0
5
bank select
0 0
0 1
1 0
1 1
0x00
location select
addressing INDF register
location select
0x3F
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 10 of 81, FM8PE68B
EELING
FM8PE68B
2.1.2
TMR0 (Time Clock/Counter register)
Read/Write-POR
R/W-0
B7
R/W-0
B6
R/W-0
B5
R/W-0
B4
R/W-0
B3
R/W-0
B2
R/W-0
B1
R/W-0
B0
Address
0x01
Name
TMR0
8-bit real-time clock/counter
Note: more bits default state, please refer to Table 2.9.
The Timer0 is a 8-bit timer/counter. The clock source of Timer0 can come from the instruction cycle clock or by an
external clock source (T0CKI pin) defined by T0CS bit (T0CON<5>). If T0CKI pin is selected, the Timer0 is increased
by T0CKI signal rising/falling edge (selected by T0SE bit (T0CON<4>)).
Please note, the pre-scaler will be cleared when TMR0 register is written with a value.
2.1.3
PCL (Low Bytes of Program Counter) & Stack
Read/Write-POR
R/W-0
B7
R/W-0
B6
R/W-0
B5
R/W-0
B4
R/W-0
B3
R/W-0
B2
R/W-0
B1
R/W-0
B0
Address
0x02
Name
PCL
Low order 8 bits of PC
Note: more bits default state, please refer to Table 2.9.
FM8PE68B devices have a 12-bit wide Program Counter (PC) and eight-level deep 12-bit hardware push/pop stack.
The low byte of PC is called the PCL register. This register is readable and writable. The high byte of PC is called
the PCH register. This register contains the PC<11:8> bits and is not directly readable or writable. All updates to the
PCH register go through the PG<1:0> bits (STATUS<6:5>). As a program instruction is executed, the Program
Counter will contain the address of the next program instruction to be executed. The PC value is increased by one,
every instruction cycle, unless an instruction changes the PC.
For a GOTO instruction, the PC<9:0> is provided by the GOTO instruction word. The PC<11:10> is updated from
the PG<1:0> bits (STATUS<6:5>). The PCL register is mapped to PC<7:0>.
For a CALL instruction, the PC<9:0> is provided by the CALL instruction word. The PC<11:10> is updated from the
PG<1:0> bits (STATUS<6:5>). The next PC will be loaded (PUSHed) into the top of STACK. The PCL register is
mapped to PC<7:0>.
For a FGOTO instruction, the PC<11:0> is provided by the FGOTO instruction word. The PCL register is mapped
to PC<7:0>, and the PG<1:0> bits is also updated from the FGOTO instruction word.
For a FCALL instruction, the PC<11:0> is provided by the FCALL instruction word. The next PC will be loaded
(PUSHed) onto the top of STACK. The PCL register is mapped to PC<7:0>, and the PG<1:0> bits is also updated
from the FCALL instruction word.
For a RETIA, RETFIE, or RETURN instruction, the PC are updated (POPed) from the top of STACK. The PCL
register is mapped to PC<7:0>.
For any instruction where the PCL is the destination, the PC<7:0> is provided by the instruction word or ALU result,
and the PC<9:8> will be not changed. The PG<1:0> bits whether to update to the PC<11:10>, It can be decision by
configure-word PCHS bit.
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 11 of 81, FM8PE68B
EELING
FM8PE68B
Figure 2.2: Loading of PC in Different Situations
Situation 1: GOTO Instruction
PCH
11 10
PCL
9
8
7
0
PC
PG<1:0>
Opcode <9:0>
-
-
-
-
-
-
STATUS
Situation 2: CALL Instruction
STACK<11:0>
Opcode <9:0>
PCH
PCL
11 10
9
8
-
7
-
0
PC
PG<1:0>
-
-
-
-
STATUS
Situation 3: FGOTO Instruction
PCH
PCL
11 10
9
8
-
7
-
0
PC
Opcode <11:0>
Opcode <11:10>
-
-
-
-
STATUS
To PG<1:0>
Situation 4: FCALL Instruction
STACK<11:0>
PCH
PCL
11 10
9
8
-
7
-
0
PC
Opcode <11:0>
Opcode <11:10>
-
-
-
-
STATUS
To PG<1:0>
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 12 of 81, FM8PE68B
EELING
FM8PE68B
Situation 5: RETIA, RETFIE, or RETURN Instruction
STACK<11:0>
PCH
11 10
PCL
9
8
7
-
0
PC
-
-
-
-
-
STATUS
Situation 6: Instruction with PCL as destination (Configuration bit PCHS is select to PC<11:10>=PG<1:0>)
PCH PCL
11 10
9
8
u
7
0
PC
u
PG<1:0>
ALU result <7:0>
PCH <9:8> bits are unchanged
-
-
-
-
-
-
STATUS
Situation 7: Instruction with PCL as destination (Configuration bit PCHS is select to Unchanged)
PCH PCL
11 10
9
8
u
7
0
PC
u
u
u
ALU result <7:0>
PCH <11:8> bits are unchanged
-
-
-
-
-
-
STATUS
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 13 of 81, FM8PE68B
EELING
FM8PE68B
2.1.4
STATUS (Status Register)
Read/Write-POR
*
B7
*
R/W-0
B6
R/W-0
B5
R-#
B4
̅̅̅̅
TO
R-#
B3
̅̅̅̅
PD
R/W-x
B2
R/W-x
B1
R/W-x
B0
Address
0x03
Name
STATUS
PG1
PG0
Z
DC
C
Legend: * = unimplemented, read as ‘1’, x = unknown, # = refer Table 2.10 for detail description, more bits default
state, please refer to Table 2.9.
This register contains the arithmetic status of the ALU, the RESET status.
If the STATUS Register is the destination for an instruction that affects the Z, DC or C bits, then the write to these
̅̅̅̅
̅̅̅̅
three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD
bits are not writable. Therefore, the result of an instruction with the STATUS Register as destination may be different
than intended. For example, CLRR STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS
Register as 100u u1uu (where u = unchanged).
C:Carry/borrow bit.
ADDAR, ADDIA:
= 0, No Carry occurred.
= 1, Carry occurred.
SUBAR, SUBIA:
= 0, Borrow occurred.
= 1, No borrow occurred.
Note:A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRR, RLR)
instructions, this bit is loaded with either the high or low order bit of the source register.
DC:Half carry/half borrow bit
ADDAR, ADDIA:
= 0, No Carry from the 4th low order bit of the result occurred.
= 1, Carry from the 4th low order bit of the result occurred.
SUBAR, SUBIA:
= 0, Borrow from the 4th low order bit of the result occurred.
= 1, No Borrow from the 4th low order bit of the result occurred.
Z:Zero bit.
= 0, The result of a logic operation is not zero.
= 1, The result of a logic operation is zero.
̅̅̅̅
PD:Power down flag bit.
= 0, by the SLEEP instruction.
= 1, after power-up or by the CLRWDT instruction.
̅̅̅̅
TO:Time overflow flag bit.
= 0, a watch-dog time overflow occurred.
= 1, after power-up or by the CLRWDT or SLEEP instruction.
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 14 of 81, FM8PE68B
EELING
FM8PE68B
PG1:PG0:Program memory page select bits. Used for GOTO, CALL, or any instruction with PCL as destination.
PG1:PG0
Program Memory Page [Address]
Page 0 [0x000~0x3FF]
Page 1 [0x400~0x7FF]
Page 2 [0x800~0xBFF]
Page 3 [0xC00~0xFFF]
0
0
1
1
0
1
0
1
User can use “PAGE” instruction to change page and maintains the program page. Otherwise, user can
use “FGOTO” (far goto), or “FCALL” (far call) instructions to program user's code. It changes the user's
program by inserting instructions within the program.
2.1.5
FSR (Indirect Data Memory Address Pointer)
Read/Write-POR
R/W-0
B7
R/W-0
B6
R/W-x
B5
R/W-x
B4
R/W-x
B3
R/W-x
B2
R/W-x
B1
R/W-x
B0
Address
0x04
Name
FSR
RP1
RP0
Indirect data memory address pointer
Legend: x = unknown, more bits default state, please refer to Table 2.9.
Bit5:Bit0:Select registers address in the indirect addressing mode. See 2.1.1 for detail description.
RP1:RP0:These bits are used to switching the bank of four data memory banks. See 2.1.1 for detail description.
2.1.6 PORTA, PORTB, PORTC & PORTD (Port Data Registers)
Read/Write-POR
R/W-x
B7
R/W-x
B6
R/W-x
B5
R/W-x
B4
-
B3
-
-
B2
-
*
B1
*
-
B0
-
Address
0x05
Name
PORTA
IOA7
IOA6
IOA5
IOA4
Read/Write-POR
R/W-x
B7
R/W-x
B6
R/W-x
B5
R/W-x
B4
R/W-x
B3
R/W-x
B2
R/W-x
B1
R/W-x
B0
Address
0x06
Name
PORTB
IOB7
IOB6
IOB5
IOB4
IOB3
IOB2
IOB1
IOB0
Read/Write-POR
R/W-x
B7
R/W-x
B6
R/W-x
B5
R/W-x
B4
R/W-x
B3
R/W-x
B2
R/W-x
B1
R/W-x
B0
Address
0x07
Name
PORTC
IOC7
IOC6
IOC5
IOC4
IOC3
IOC2
IOC1
IOC0
Read/Write-POR
R/W-x
B7
R/W-x
B6
R/W-x
B5
R/W-x
B4
R/W-x
B3
R/W-x
B2
R/W-x
B1
R/W-x
B0
Address
0x08
Name
PORTD
IOD7
IOD6
IOD5
IOD4
IOD3
IOD2
IOD1
IOD0
Legend: - = unimplemented, read as ‘0’, * = unimplemented, read as ‘1’, more bits default state, please refer to
Table 2.9.
Reading the port (PORTA, PORTB, PORTC and PORTD register) reads the status of the pins independent of the
pin’s input/output modes. Writing to these ports will write to the port data latch.
For FM8PE68B devices, PORTA is a 4-bit port data Register. Only the high order 4 bits are used (PORTA<7:4>)
and bits 3-0 are unimplemented and read as ‘0’s.
All of PORTB, PORTC and PORTD are 8-bit port data registers.
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 15 of 81, FM8PE68B
EELING
FM8PE68B
2.1.7
LCDCON (LCD Control Register) (Bank 0, 2)
Read/Write-POR
R/W-1
B7
R/W-1
B6
R/W-0
B5
R/W-0
B4
-
B3
-
R/W-0
B2
R/W-0
B1
R/W-0
B0
Address
0x09
Name
LCDCON
BIAS
DUTY1
DUTY0
LCDEN
TYPE
LCDF1
LCDF0
Legend: - = unimplemented, read as ‘0’, more bits default state, please refer to Table 2.9.
LCDF1:LCDF0:LCD frame frequency select bits
LCD frame frequency (FS=32.768KHZ
)
LCDF1
LCDF0
1/2 duty
1/3 duty
1/4 duty
0
0
1
1
0
1
0
1
FS/(256*2)=64.0
FS/(280*2)=58.5
FS/(304*2)=53.9
FS/(232*2)=70.6
FS/(172*3)=63.5
FS/(188*3)=58.0
FS/(204*3)=53.5
FS/(156*3)=70.0
FS/(128*4) =64.0
FS/(140*4) =58.5
FS/(152*4) =53.9
FS/(116*4) =70.6
FS: sub-oscillator frequency
TYPE:LCD drive waveform type select bit.
= 0, A type waveform.
= 1, B type waveform.
LCDEN:LCD enable bit. When LCD function is disabled, all common/segment outputs are set to ground level.
= 0, LCD circuit disable.
= 1, LCD circuit enable.
DUTY1:DUTY0:LCD duty select bits.
= 0, 0 1/2 duty.
= 0, 1 1/3 duty.
= 1, 0 1/4 duty.
BIAS:LCD bias select bit.
= 0, 1/2 bias.
= 1, 1/3 bias.
2.1.8
LCDA (LCD Address Register) (Bank 0, 2)
Read/Write-POR
-
B7
0
-
B6
0
-
B5
0
R/W-0
B4
R/W-0
B3
R/W-0
B2
R/W-0
B1
R/W-0
B0
Address
0x0A
Name
LCDA
LCDA4
LCDA3
LCDA2
LCDA1
LCDA0
Legend: 0 = Not used, must fixed to “0”, more bits default state, please refer to Table 2.9.
LCDA4:LCDA0:LCD RAM address.
LCDD (LCD data buffer)
LCD Address
Segment
Bit3
Bit2
Bit1
Bit0
Bit7 Bit6 Bit5 Bit4
LCDD3 LCDD2 LCDD1 LCDD0
00h
01h
-
-
-
-
-
-
-
-
-
-
-
-
C3S0
C3S1
C3S2
|
C2S0
C2S1
C2S2
C1S0
C1S1
C1S2
C0S0
C0S1
C0S2
SEG0
SEG1
SEG2
|
02h
|
1Dh
1Eh
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
C3S29 C2S29 C1S29 C0S29
C3S30 C2S30 C1S30 C0S30
C3S31 C2S31 C1S31 C0S31
SEG29
SEG30
SEG31
1Fh
Common
COM3
COM2
COM1
COM0
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 16 of 81, FM8PE68B
EELING
FM8PE68B
2.1.9
LCDD (LCD Data Buffer) (Bank 0, 2)
Read/Write-POR
x
B7
0
x
B6
0
x
B5
0
x
B4
0
R/W-x
B3
R/W-x
B2
R/W-x
B1
R/W-x
B0
Address
0x0B
Name
LCDD
LCDD3
LCDD2
LCDD1
LCDD0
Legend: 0 = Not used, must fixed to “0”, x = unknown, more bits default state, please refer to Table 2.9.
LCDD4:LCDD0:LCD RAM data transfer buffer.
2.1.10 CNTCON (Counter Control Register) (Bank 0, 2)
Read/Write-POR
x
B7
0
x
B6
0
x
B5
0
x
B4
0
R/W-0
B3
R/W-0
B2
R/W-0
B1
R/W-0
B0
Address
0x0C
Name
CNTCON
LPEN
HPEN
C2EN
C1EN
Legend: 0 = Not used, must fixed to “0”, x = unknown, more bits default state, please refer to Table 2.9.
C1EN:Counter 1 enable bit.
= 0, Disable.
= 1, Enable.
C2EN:Counter 2 enable bit.
= 0, Disable.
= 1, Enable.
HPEN:High pulse width timer enable bit.
= 0, Disable.
= 1, Enable.
LPEN:Low pulse width timer enable bit.
= 0, Disable.
= 1, Enable.
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 17 of 81, FM8PE68B
EELING
FM8PE68B
2.1.11 SYSCON (System Control Register) (Bank 0, 2)
Read/Write-POR
x
B7
0
R/W-0
B6
R/W-0
B5
R/W-0
B4
R/W-1
B3
R/W-0
B2
R/W-0
B1
R/W-%
B0
Address
0Dh
Name
SYSCON
PLLCK2
PLLCK1
PLLCK0
IDLE
LCDBF1
LCDBF0
CPUS
Legend: 0 = Not used, must fixed to “0”, x = unknown, % = refer to the configuration bit “HLFS”, more bits default
state, please refer to Table 2.9.
CPUS:CPU oscillator source select bit.
= 0, Sub-oscillator (FS) is selected, and the main oscillator is stopped.
= 1, Main oscillator (FM) is selected.
Figure 2.3: CPU Operation Mode
Configuration Bit
Configuration Bit
HLFS="sub oscillator"
HLFS="main oscillator"
RESET
IDLE="0"
SLEEP
lnstruction
IDLE="1"
SLEEP
lnstruction
SLEEP Mode
Fm: stop
Fs: stop
Normal Mode
Fm: oscillation
Fs: oscillation
CPU using Fm
IDLE Mode
Fm: stop
Fs: oscillation
CPU stop
CPU stop
Wake-up
Wake-up
The wake-up time is 18ms+16/Fs.
CPUS="1"
The wake-up time is 18ms+16/Fs.
CPUS="0"
IDLE="0"
SLEEP
lnstruction
IDLE="1"
SLEEP
lnstruction
SLEEP Mode
Fm: stop
Fs: stop
Green Mode
Fm: stop
Fs: oscillation
CPU using Fs
IDLE Mode
Fm: stop
Fs: oscillation
CPU stop
CPU stop
Wake-up
Wake-up
The wake-up time is 18ms+16/Fs.
The wake-up time is 16/Fs.
LCDBF1:LCDBF0:LCD booster frequency select bits.
= 0, 0 FS
= 0, 1 FS/4
= 1, 0 FS/8
= 1, 1 FS/16
IDLE:Idle / sleep mode select bit of the SLEEP instruction.
= 0, Sleep mode after SLEEP instruction.
= 1, Idle mode after SLEEP instruction.
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 18 of 81, FM8PE68B
EELING
FM8PE68B
PLLCK2:PLLCK0:Main clock select bit for PLL mode (code option select)
PLLCK2:PLLCK0
Main clock (FM) Frequency
0
0
0
0
1
0
0
1
1
x
0
1
0
1
x
32.768K*130 = 4.26MHZ
32.768K*65 = 2.13MHZ
32.768K*65/2 = 1.065MHZ
32.768K*65/4 = 532.5KHZ
32.768K*244 = 8MHZ
2.1.12 IRCON (IR Control Register) (Bank 0, 2)
Read/Write-POR
R/W-0
B7
R/W-0
B6
R/W-0
B5
-
B4
-
R/W-0
B3
R/W-0
B2
R/W-0
B1
R/W-0
B0
Address
0x0E
Name
IRCON
IRE
HF
LGP
EIROUT
ET0CKI
EINT1
EINT0
Legend: - = unimplemented, read as ‘0’, more bits default state, please refer to Table 2.9.
EINT0:Define the function of IOA4/INT0 pin.
= 0, IOA4, bi-directional I/O pin.
= 1, INT0, external interrupt pin. The I/O control bit of IOA4 (bit 4 of IOSTA) must be set to “1”.
EINT1:Define the function of IOA5/INT1 pin.
= 0, IOA5, bi-directional I/O pin.
= 1, INT1, external interrupt pin. The I/O control bit of IOA5 (bit 5 of IOSTA) must be set to “1”.
ET0CKI:Define the function of IOA6/T0CKI pin.
= 0, IOA6, bi-directional I/O pin.
= 1, T0CKI, external input pin of Timer0. The I/O control bit of IOA6 (bit 6 of IOSTA) must be set to “1”.
EIROUT:Define the function of IOA7/IROUT pin.
= 0, IOA7, bi-directional I/O pin.
= 1, IROUT, The I/O control bit of IOA7 (bit 7 of IOSTA) must be set to “0”.
LGP:Long pulse.
=0,The high-pulse timer register and low-pulse width timer is valid.
=1,The high-pulse width timer register is ignored. So the IROUT waveform is dependent on low-pulse width
timer register only
HF:High frequency.
=0,For PWM application, IROUT waveform is created according to high-pulse and low-pulse width time as
determined by the high pulse and low pulse width timers respectively.
=1,For IR application mode, the low time sections of the generated pulse is modulated with the frequency
FCARRIER
.
IRE:Infrared Remote Enable bit.
= 0, Disable IR H/W Modulator Function. IROUT pin fixed to high level.
= 1, Enable IR H/W Modulator Function.
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 19 of 81, FM8PE68B
EELING
FM8PE68B
2.1.13 PORTE & PORTF (Port Data Register) (Bank 1, 3)
Read/Write-POR
R/W-1
B7
R/W-1
B6
R/W-1
B5
R/W-1
B4
R/W-1
B3
R/W-1
B2
R/W-1
B1
R/W-1
B0
Address
0x09
Name
PORTE
IOE7
IOE6
IOE5
IOE4
IOE3
IOE2
IOE1
IOE0
Read/Write-POR
R/W-1
B7
R/W-1
B6
R/W-1
B5
R/W-1
B4
R/W-1
B3
R/W-1
B2
R/W-1
B1
R/W-1
B0
Address
0x0A
Name
PORTF
IOF7
IOF6
IOF5
IOF4
IOF3
IOF2
IOF1
IOF0
Note: more bits default state, please refer to Table 2.9.
Data latch of PORTE and PORTF. These registers are readable and writable.
2.1.14 RFCCON (RFC Control Register) (Bank 1, 3)
Read/Write-POR
R/W-0
B7
R/W-0
B6
R/W-0
B5
R/W-0
B4
-
B3
-
-
B2
-
R/W-0
B1
R/W-0
B0
Address
0x0B
Name
RFCCON
RFCON
START
RFCIF
RFCMOD
RFCS1
RFCS0
Legend: - = unimplemented, read as ‘0’, more bits default state, please refer to Table 2.9.
RFCS1:RFCS0:Select one the RFC oscillation network of RFCx (x = 0 to 2). The selected RFCx pin will be
configured as output pin if RFCON = 1. Other RFCx pins will behave as tristate input pins. If
RFCON = 0, all RFCx pins will behave as tristate input pins.
RFCS1:RFCS0
RFC channel
RFC0 pin is selected.
RFC1 pin is selected.
RFC2 pin is selected.
No function, don’t use.
0, 0
0, 1
1, 0
1, 1
RFCMOD:RFC mode selection bit.
= 0,Enable/disable the counter by CX signal, and the clock source of the counter is the internal system
clock (FOSC).
= 1,Enable/disable the counter by START bit, and the clock source of the counter is the CX signal.
RFCIF:RFC module interrupt flag. Set when RFC conversion is completed if RFCMOD = 0, reset by software.
START:RFC counter enable bit
= 0, Stop the RFC conversion, reset by hardware when conversion is finished or by software.
= 1, RFC counter start to convert.
RFCON:RFC module enable bit.
= 0, Disable RFC module, all the RFCx and CX pins will behave as tristate input pins.
= 1, Enable RFC module.
2.1.15 RFCDL (RFC Data Register Low Byte) (Bank 1, 3)
Read/Write-POR
R-0
B7
R-0
B6
R-0
B5
R-0
B4
R-0
B3
R-0
B2
R-0
B1
R-0
B0
Address
0x0C
Name
RFCDL
RFCD7
RFCD6
RFCD5
RFCD4
RFCD3
RFCD2
RFCD1
RFCD0
Note: more bits default state, please refer to Table 2.9.
RFCD7:RFCD0:The low byte of RFC conversion result.
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 20 of 81, FM8PE68B
EELING
FM8PE68B
2.1.16 RFCDH (RFC Data Register High Byte) (Bank 1, 3)
Read/Write-POR
R-0
B7
R-0
B6
R-0
B5
R-0
B4
R-0
B3
R-0
B2
R-0
B1
R-0
B0
Address
0x0D
Name
RFCDH
RFCOV
RFCD14
RFCD13
RFCD12
RFCD11
RFCD10
RFCD9
RFCD8
Note: more bits default state, please refer to Table 2.9.
RFCD14:RFCD8:The high byte of RFC conversion result.
RFCOV:RFC counter overflow flag. Set when RFC counter overflow, reset by RFC counter reset.
= 0, Not overflow.
= 1, Overflow.
2.1.17 DIVCON (Divider Control Register) (Bank 1, 3)
Read/Write-POR
R/W-0
B7
R/W-1
B6
R/W-0
B5
-
B4
-
-
B3
-
-
B2
-
-
B1
-
-
B0
-
Address
0x0E
Name
DIVCON
DIVON
DIVRST
DIVIF
Legend: - = unimplemented, read as ‘0’, more bits default state, please refer to Table 2.9.
DIVIF:Sub-oscillator (FS) divider overflow (0.5 sec) interrupt flag. Set when FS divider overflows, reset by software.
DIVRST:Sub-oscillator (FS) divider RESET bit.
= 0, Reset the sub-oscillator divider. Set to “1” by hardware after the Sub-oscillator (FS) divider is reset.
= 1, No action.
DIVON:Sub-oscillator (FS) divider PAUSE bit.
= 0, Pause.
= 1, Continue.
2.1.18 INTFLAG (Interrupt Status Register)
Read/Write-POR
R/W-0
B7
R/W-0
B6
R/W-0
B5
R/W-0
B4
R/W-0
B3
R/W-0
B2
R/W-0
B1
R/W-0
B0
Address
0x0F
Name
INTFLAG
PBDIF
LPIF
HPIF
C2IF
C1IF
INT1IF
INT0IF
T0IF
Note: more bits default state, please refer to Table 2.9.
T0IF:Timer0 overflow interrupt flag. Set when Timer0 overflows, reset by software.
INT0IF:External INT0 pin interrupt flag. Set by rising/falling (selected by INTEDG bit (T0CON<7>)) edge on INT0
pin, reset by software.
INT1IF:External INT1 pin interrupt flag. Set by falling edge on INT1 pin, reset by software.
C1IF:Counter 1 underflow interrupt flag. Set when counter 1 underflows, reset by software.
C2IF:Counter 2 underflow interrupt flag. Set when counter 2 underflows, reset by software.
HPIF:High-pulse width timer underflow interrupt flag. Set when high-pulse width timer underflows, reset by
software.
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 21 of 81, FM8PE68B
EELING
FM8PE68B
LPIF:Low-pulse width timer underflow interrupt flag. Set when low-pulse width timer underflows, reset by software.
PBDIF:Port B / Port D input change interrupt flag. Set when Port B / Port D input changes, reset by software.
2.1.19 ACC (Accumulator)
Read/Write-POR
R/W-x
B7
R/W-x
B6
R/W-x
B5
R/W-x
B4
R/W-x
B3
R/W-x
B2
R/W-x
B1
R/W-x
B0
Address
N/A
Name
ACC
Accumulator
Note: more bits default state, please refer to Table 2.9.
Accumulator is an internal data transfer, or instruction operand holding. It cannot be addressed.
2.1.20 IOSTA, IOSTB, IOSTC & IOSTD (Port I/O Control Registers)
Read/Write-POR
R/W-1
B7
R/W-1
B6
R/W-1
B5
R/W-1
B4
-
B3
-
-
B2
-
-
B1
-
-
B0
-
Address
0x05
Name
IOSTA
IOSTA7
IOSTA6
IOSTA5
IOSTA4
Read/Write-POR
R/W-1
B7
R/W-1
B6
R/W-1
B5
R/W-1
B4
R/W-1
B3
R/W-1
B2
R/W-1
B1
R/W-1
B0
Address
0x06
Name
IOSTB
IOSTB7
IOSTB6
IOSTB5
IOSTB4
IOSTB3
IOSTB2
IOSTB1 IOSTB0
Read/Write-POR
R/W-1
B7
R/W-1
B6
R/W-1
B5
R/W-1
B4
R/W-1
B3
R/W-1
B2
R/W-1
B1
R/W-1
B0
Address
0x07
Name
IOSTC
IOSTC7
IOSTC6
IOSTC5
IOSTC4
IOSTC3
IOSTC2
IOSTC1 IOSTC0
Read/Write-POR
R/W-1
B7
R/W-1
B6
R/W-1
B5
R/W-1
B4
R/W-1
B3
R/W-1
B2
R/W-1
B1
R/W-1
B0
Address
0x08
Name
IOSTD
IOSTD7
IOSTD6
IOSTD5
IOSTD4
IOSTD3
IOSTD2
IOSTD1 IOSTD0
Accessed by IOST / IOSTR instruction.
Legend: - = unimplemented, read as ‘0’, more bits default state, please refer to Table 2.9.
The Port I/O Control Registers are loaded with the contents of the ACC Register by executing the IOST R
(0x05~0x08) instruction. A ‘1’ from a IOST Register bit puts the corresponding output driver in hi-impedance state
(input mode). A ‘0’ enables the output buffer and puts the contents of the output data latch on the selected pins
(output mode).
The IOST Registers are set (output drivers disabled) upon RESET.
IOSTA7:IOSTA4:PORTA I/O direction control register.
= 0, set the relative I/O pins as output.
= 1, set the relative I/O pin into high impedance (input pin).
IOSTB7:IOSTB0:PORTB I/O direction control register.
= 0, set the relative I/O pins as output.
= 1, set the relative I/O pin into high impedance (input pin).
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 22 of 81, FM8PE68B
EELING
FM8PE68B
IOSTC7:IOSTC0:PORTC I/O direction control register.
= 0, set the relative I/O pins as output.
= 1, set the relative I/O pin into high impedance (input pin).
IOSTD7:IOSTD0:PORTD I/O direction control register.
= 0, set the relative I/O pins as output.
= 1, set the relative I/O pin into high impedance (input pin).
2.1.21 DRAMA (128 Bytes Data RAM Address Register)
Read/Write-POR
-
B7
0
R/W-0
B6
R/W-0
B5
R/W-0
B4
R/W-0
B3
R/W-0
B2
R/W-0
B1
R/W-0
B0
Address
0x09
Name
DRAMA
RAMA6
RAMA5
RAMA4
RAMA3
RAMA2
RAMA1
RAMA0
Accessed by IOST / IOSTR instruction.
Legend: 0 = Not used, must fixed to “0”, - = unimplemented, read as ‘0’, more bits default state, please refer to
Table 2.9.
RAMA6:RAMA0:128 bytes data RAM address.
2.1.22 DRAMD (128 Bytes Data RAM Data Buffer)
Read/Write-POR
R/W-x
B7
R/W-x
B6
R/W-x
B5
R/W-x
B4
R/W-x
B3
R/W-x
B2
R/W-x
B1
R/W-x
B0
Address
0x0A
Name
DRAMD
RAMD7
RAMD6
RAMD5
RAMD4
RAMD3
RAMD2
RAMD1
RAMD0
Accessed by IOST / IOSTR instruction.
Note: more bits default state, please refer to Table 2.9.
RAMD7:RAMD0:128 bytes data RAM data transfer buffer.
2.1.23 C1PR (Counter 1 Preset Register)
Read/Write-POR
R/W-0
B7
R/W-0
B6
R/W-0
B5
R/W-0
B4
R/W-0
B3
R/W-0
B2
R/W-0
B1
R/W-0
B0
Address
0x0B
Name
C1PR
C1PR7
C1PR6
C1PR5
C1PR4
C1PR3
C1PR2
C1PR1
C1PR0
Accessed by IOST / IOSTR instruction.
Note: more bits default state, please refer to Table 2.9.
C1PR7:C1PR0:All are Counter 1 buffer which is readable and writable. Counter 1 is an 8-bit down-counter with 8-
bit pre-scaler. User can preset the counter and read preset value through C1PR register. After
interrupt, it will auto reload the preset value. (The pre-scaler value is controlled by C12CON
register)
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 23 of 81, FM8PE68B
EELING
FM8PE68B
2.1.24 C2PR (Counter 2 Preset Register)
Read/Write-POR
R/W-0
B7
R/W-0
B6
R/W-0
B5
R/W-0
B4
R/W-0
B3
R/W-0
B2
R/W-0
B1
R/W-0
B0
Address
0x0C
Name
C2PR
C2PR7
C2PR6
C2PR5
C2PR4
C2PR3
C2PR2
C2PR1
C2PR0
Accessed by IOST / IOSTR instruction.
Note: more bits default state, please refer to Table 2.9.
C2PR7:C2PR0:All are Counter 2 buffer which is readable and writable. Counter 2 is an 8-bit down-counter with 8-
bit pre-scaler. User can preset the counter and read preset value through C2PR register. After
interrupt, it will auto reload the preset value.
When IR output is enabled, this control register can obtain carrier frequency output.
If the Counter 2 clock source is equal to FT (FM or FS, select by C12CON register):
Carrier frequency (FCARRIER) = FT/[2*(preset value+1)*pre-scaler]
(The pre-scaler value is controlled by C12CON register)
2.1.25 HPPR (High-Pulse Width Timer Preset Register)
Read/Write-POR
R/W-0
B7
R/W-0
B6
R/W-0
B5
R/W-0
B4
R/W-0
B3
R/W-0
B2
R/W-0
B1
R/W-0
B0
Address
0x0D
Name
HPPR
HPPR7
HPPR6
HPPR5
HPPR4
HPPR3
HPPR2
HPPR1
HPPR0
Accessed by IOST / IOSTR instruction.
Note: more bits default state, please refer to Table 2.9.
HPPR7:HPPR0:All are high-pulse width timer buffer which is readable and writable. High-pulse width timer is an
8-bit down-counter with 8-bit pre-scaler. User can preset the counter and read preset value through
HPPR register. After interrupt, it will auto reload the preset value.
When PWM or IR output is enabled, this control register is set as high-pulse width.
If the high-pulse width timer clock source is equal to FT (FM or FS, select by HLPCON register):
The high-pulse width = [(preset value+1)*pre-scaler] / FT
(The pre-scaler value is controlled by HLPCON register)
2.1.26 LPPR (Low-Pulse Width Timer Preset Register)
Read/Write-POR
R/W-0
B7
R/W-0
B6
R/W-0
B5
R/W-0
B4
R/W-0
B3
R/W-0
B2
R/W-0
B1
R/W-0
B0
Address
0Eh
Name
LPPR
LPPR7
LPPR6
LPPR5
LPPR4
LPPR3
LPPR2
LPPR1
LPPR0
Accessed by IOST / IOSTR instruction.
Note: more bits default state, please refer to Table 2.9.
LPPR7:LPPR0:All are low-pulse width timer buffer which is readable and writable. Low-pulse width timer is an 8-
bit down-counter with 8-bit pre-scaler. User can preset the counter and read preset value through
LPPR register. After interrupt, it will auto reload the preset value.
When PWM or IR output is enabled, this control register is set as low-pulse width.
If the low-pulse width timer clock source is equal to FT (FM or FS, select by HLPCON register):
The low-pulse width = [(preset value+1)*pre-scaler]/ FT
(The pre-scaler value is controlled by HLPCON register)
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 24 of 81, FM8PE68B
EELING
FM8PE68B
2.1.27 INTEN (Interrupt Mask Register)
Read/Write-POR
R/W-0
B7
R/W-0
B6
R/W-0
B5
R/W-0
B4
R/W-0
B3
R/W-0
B2
R/W-0
B1
R/W-0
B0
Address
0Fh
Name
INTEN
PBDIE
LPIE
HPIE
C2IE
C1IE
INT1IE
INT0IE
T0IE
Accessed by IOST / IOSTR instruction.
Note: more bits default state, please refer to Table 2.9.
T0IE:Timer0 overflow interrupt enable bit.
= 0, Disable the Timer0 overflow interrupt.
= 1, Enable the Timer0 overflow interrupt.
INT0IE:External INT0 pin interrupt enable bit.
= 0, Disable the External INT0 pin interrupt.
= 1, Enable the External INT0 pin interrupt.
INT1IE:External INT1 pin interrupt enable bit.
= 0, Disable the External INT1 pin interrupt.
= 1, Enable the External INT1 pin interrupt.
C1IE:Counter 1 underflow interrupt enable bit.
= 0, Disable the counter 1 underflow interrupt.
= 1, Enable the counter 1 underflow interrupt.
C2IE:Counter 2 underflow interrupt enable bit.
= 0, Disable the counter 2 underflow interrupt.
= 1, Enable the counter 2 underflow interrupt.
HPIE:High-pulse width timer underflow interrupt enable bit.
= 0, Disable the high-pulse width timer underflow interrupt.
= 1, Enable the high-pulse width timer underflow interrupt.
LPIE:Low-pulse width timer underflow interrupt enable bit.
= 0, Disable the low-pulse width timer underflow interrupt.
= 1, Enable the low-pulse width timer underflow interrupt.
PBDIE:Port B / Port D input change interrupt enable bit.
= 0, Disable the Port B / Port D input change interrupt.
= 1, Enable Port B / Port D input change interrupt.
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 25 of 81, FM8PE68B
EELING
FM8PE68B
2.1.28 SEGCON (Segment Control Register)
Read/Write-POR
R/W-1
B7
R/W-1
B6
R/W-1
B5
R/W-1
B4
R/W-0
B3
R/W-0
B2
R/W-0
B1
R/W-0
B0
Address
0x15
Name
SEGCON
IOFHS
IOFLS
IOEHS
IOELS
IODHS
IODLS
IOCHS
IOCLS
Accessed by IOST / IOSTR instruction.
Note: more bits default state, please refer to Table 2.9.
IOCLS:Select IOC0~IOC3 or SEG16~SEG19 output for SEGxx/IOCx pins.
= 0, Bi-directional I/O pins as normal IOC0~IOC3 are selected.
= 1, LCD segment SEG16~SEG19 output are selected.
IOCHS:Select IOC4~IOC7 or SEG20~SEG23 output for SEGxx/IOCx pins.
= 0, Bi-directional I/O pins as normal IOC4~IOC7 are selected.
= 1, LCD segment SEG20~SEG23 output are selected.
IODLS:Select IOD0~IOD3 or SEG24~SEG27output for SEGxx/IODx pins.
= 0, Bi-directional I/O pins as normal IOD0~IOD3 are selected.
= 1, LCD segment SEG24~SEG27 output are selected.
IODHS:Select IOD4~IOD7 (or RFC pins) or SEG28~SEG31 output for SEGxx/IODx/RFCx pins.
= 0, Bi-directional I/O pins as normal IOD4~IOD7 (or RFC pins) are selected.
= 1, LCD segment SEG28~SEG31 output are selected.
IOELS:Select IOE0~IOE3 or SEG0~SEG3 output for SEGxx/IOCx pins.
= 0, Output only pins as normal IOE0~IOE3 are selected.
= 1, LCD segment SEG0~SEG3 output are selected.
IOEHS:Select IOE4~IOE7 or SEG4~SEG7 output for SEGxx/IOCx pins.
= 0, Output only pins as normal IOE4~IOE7 are selected.
= 1, LCD segment SEG4~SEG7 output are selected.
IOFLS:Select IOF0~IOF3 or SEG8~SEG11output for SEGxx/IODx pins.
= 0, Output only I/O pins as normal IOF0~IOF3 are selected.
= 1, LCD segment SEG8~SEG11 output are selected.
IOFHS:Select IOF4~IOF7 or SEG12~SEG15 output for SEGxx/IODx pins.
= 0, Output only pins as normal IOF4~IOF7 are selected.
= 1, LCD segment SEG12~SEG15 output are selected.
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 26 of 81, FM8PE68B
EELING
FM8PE68B
2.1.29 WUCON (Wake-up Control Register)
Read/Write-POR
R/W-0
B7
*
B6
*
*
B5
*
*
B4
*
R/W-0
B3
R/W-0
B2
R/W-0
B1
R/W-0
B0
Address
0x16
Name
WUCON
IRSC
/WUEDH
/WUEDL
/WUEBH /WUEBL
Accessed by IOST / IOSTR instruction.
Legend: * = unimplemented, read as ‘1’, more bits default state, please refer to Table 2.9.
/WUEBL:Pin change wake up enable bit of IOB0~IOB3 pins.
= 0, enable IOB0~IOB3 pin change wake up function.
= 1, disable IOB0~IOB3 pin change wake up function.
/WUEBH:Pin change wake up enable bit of IOB4~IOB7 pins.
= 0, enable IOB4~IOB7 pin change wake up function.
= 1, disable IOB4~IOB7 pin change wake up function.
/WUEDL:Pin change wake up enable bit of IOD0~IOD3 pins.
= 0, enable IOD0~IOD3 pin change wake up function.
= 1, disable IOD0~IOD3 pin change wake up function.
/WUEDH:Pin change wake up enable bit of IOD4~IOD7 pins.
= 0, enable IOD4~IOD7 pin change wake up function.
= 1, disable IOD4~IOD7 pin change wake up function.
IRSC:IOA7/IROUT output Drive / Sink current select bit.
IOA7/IROUT Sink current
IOA7/IROUT Drive current
IRSC
VDD=3V
7mA
VDD=5V
10mA
VDD=3V
1mA
VDD=5V
3mA
0
1
14mA
20mA
2mA
6mA
2.1.30 T0CON (Timer0 Control Register)
Read/Write-POR
R/W-1
B7
R-0
B6
R/W-1
B5
R/W-1
B4
R/W-1
B3
R/W-1
B2
R/W-1
B1
R/W-1
B0
Address
0x17
Name
T0CON
INT0EDG
GIE
T0CS
T0SE
T0PS3
T0PS2
T0PS1
T0PS0
Accessed by OPTION / OPTIONR instruction. The T0CON Register are set all “1”s except GIE bit.
Note: more bits default state, please refer to Table 2.9.
T0PS3:T0PS0:Timer0 Pre-scaler rate select bits.
T0PS3:T0PS0
Timer0 Pre-Scaler Rate
0
1
1
1
1
1
1
1
1
x
0
0
0
0
1
1
1
1
x
0
0
1
1
0
0
1
1
x
0
1
0
1
0
1
0
1
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 27 of 81, FM8PE68B
EELING
FM8PE68B
T0SE:TMR0 source edge select bit.
= 0, Rising edge on T0CKI pin.
= 1, Falling edge on T0CKI pin.
T0CS:TMR0 clock source select bit.
= 0, internal instruction clock cycle.
= 1, External T0CKI pin.
GIE: Global interrupt enable bit. Set by “ENI” or “RETFIE” instructions. Cleared by “DISI” instruction or entering
into interrupt subroutine.
= 0, Disable all interrupts. For wake-up from SLEEP mode through an interrupt event, the device will continue
execution at the instruction after the SLEEP instruction.
= 1, Enable all un-masked interrupts. For wake-up from SLEEP mode through an interrupt event, the device
will branch to the interrupt address (0x003~0x021, based on different interrupt event).
Note: 1. The GIE bit is not writable bit. This bit is only set by “ENI” or “RETFIE” instructions, and cleared
by “DISI” instruction or entering into interrupt subroutine.
2. When an interrupt event occur with the GIE bit and its corresponding interrupt enable bit are all
set, the GIE bit will be cleared by hardware to disable any further interrupts. The RETFIE
instruction will exit the interrupt routine and set the GIE bit to re-enable interrupt.
INT0EDG:INT0 pin interrupt edge select bit.
= 1, interrupt on falling edge of INT0 pin.
= 0, interrupt on rising edge of INT0 pin.
2.1.31 WDTCON (Watch-Dog Timer Control Register)
Read/Write-POR
*
B7
*
*
B6
*
*
B5
*
*
B4
*
R/W-0
B3
R/W-1
B2
R/W-1
B1
R/W-1
B0
Address
0x18
Name
WDTCON
WDTEN
WDTPS2
WDTPS1 WDTPS0
Accessed by IOST / IOSTR instruction.
Legend: * = unimplemented, read as ‘1’, more bits default state, please refer to Table 2.9.
WDTPS2:WDTPS0:Watch-Dog timer Pre-scaler rate select bits.
WDTPS2:WDTPS0
WDT Pre-Scaler Rate
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
WDTEN:Watchdog timer enable bit.
= 1, Enable WDT function.
= 0, Disable WDT function.
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 28 of 81, FM8PE68B
EELING
FM8PE68B
2.1.32 C12CON (Counter 1 & 2 Control Register)
Read/Write-POR
R/W-0
B7
R/W-0
B6
R/W-0
B5
R/W-0
B4
R/W-0
B3
R/W-0
B2
R/W-0
B1
R/W-0
B0
Address
0x19
Name
C12CON
C2CS
C2PS2
C2PS1
C2PS0
C1CS
C1PS2
C1PS1
C1PS0
Accessed by IOST / IOSTR instruction.
Note: more bits default state, please refer to Table 2.9.
C1S2:C1PS0:Counter1 pre-scaler select bits.
C1PS2:C1PS0
Counter 1 Pre-scaler Rate
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
C1CS:Counter 1 clock source select bit.
= 0, Sub-oscillator clock (FS) is selected.
= 1, Main-oscillator clock (FM) is selected.
C2S2:C2PS0:Counter 1 pre-scaler select bits.
C2PS2:C2PS0
Counter 2 Pre-scaler Rate
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
C2CS:Counter 2 clock source select bit.
= 0, Sub-oscillator clock (FS) is selected.
= 1, Main-oscillator clock (FM) is selected.
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 29 of 81, FM8PE68B
EELING
FM8PE68B
2.1.33 HLPCON (High-pulse / Low-pulse width timer Control Register)
Read/Write-POR
R/W-0
B7
R/W-0
B6
R/W-0
B5
R/W-0
B4
R/W-0
B3
R/W-0
B2
R/W-0
B1
R/W-0
B0
Address
0x1A
Name
HLPCON
LPCS
LPPS2
LPPS1
LPPS0
HPCS
HPPS2
HPPS1
HPPS0
Accessed by IOST / IOSTR instruction.
Note: more bits default state, please refer to Table 2.9.
HPPS2:HPPS0:High-pulse width timer pre-scaler select bits.
HPPS2:HPPS0
High-pulse width timer Pre-Scaler Rate
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
HPCS:High-pulse width timer clock source select bit.
= 0, Sub-oscillator clock (FS) is selected.
= 1, Main-oscillator clock (FM) is selected.
LPPS2:LPPS0:Low-pulse width timer pre-scaler select bits.
LPPS2:LPPS0
Low-pulse width timer Pre-Scaler Rate
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
LPCS:Low-pulse width timer clock source select bit.
= 0, Sub-oscillator clock (FS) is selected.
= 1, Main-oscillator clock (FM) is selected.
2.1.34 BPHCON (PORTB Pull-high Control Register)
Read/Write-POR
R/W-0
B7
R/W-0
B6
R/W-0
B5
R/W-0
B4
R/W-0
B3
R/W-0
B2
R/W-0
B1
R/W-0
B0
Address
0x1B
Name
BPHCON
PHB7
PHB6
PHB5
PHB4
PHB3
PHB2
PHB1
PHB0
Accessed by IOST / IOSTR instruction.
Note: more bits default state, please refer to Table 2.9.
PHB0:= 0, Disable the internal pull-high of IOB0 pin.
= 1, Enable the internal pull-high of IOB0 pin.
PHB1:= 0, Disable the internal pull-high of IOB1 pin.
= 1, Enable the internal pull-high of IOB1 pin.
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 30 of 81, FM8PE68B
EELING
FM8PE68B
PHB2:= 0, Disable the internal pull-high of IOB2 pin.
= 1, Enable the internal pull-high of IOB2 pin.
PHB3:= 0, Disable the internal pull-high of IOB3 pin.
= 1, Enable the internal pull-high of IOB3 pin.
PHB4:= 0, Disable the internal pull-high of IOB4 pin.
= 1, Enable the internal pull-high of IOB4 pin.
PHB5:= 0, Disable the internal pull-high of IOB5 pin.
= 1, Enable the internal pull-high of IOB5 pin.
PHB6:= 0, Disable the internal pull-high of IOB6 pin.
= 1, Enable the internal pull-high of IOB6 pin.
PHB7:= 0, Disable the internal pull-high of IOB7 pin.
= 1, Enable the internal pull-high of IOB7 pin.
2.1.35 BODCON (PORTB Open-drain Control Register)
Read/Write-POR
R/W-0
B7
R/W-0
B6
R/W-0
B5
R/W-0
B4
R/W-0
B3
R/W-0
B2
R/W-0
B1
R/W-0
B0
Address
0x1C
Name
BODCON
ODB7
ODB6
ODB5
ODB4
ODB3
ODB2
ODB1
ODB0
Accessed by IOST / IOSTR instruction.
Note: more bits default state, please refer to Table 2.9.
ODB0:= 0, Disable the internal open-drain of IOB0 pin.
= 1, Enable the internal open-drain of IOB0 pin.
ODB1:= 0, Disable the internal open-drain of IOB1 pin.
= 1, Enable the internal open-drain of IOB1 pin.
ODB2:= 0, Disable the internal open-drain of IOB2 pin.
= 1, Enable the internal open-drain of IOB2 pin.
ODB3:= 0, Disable the internal open-drain of IOB3 pin.
= 1, Enable the internal open-drain of IOB3 pin.
ODB4:= 0, Disable the internal open-drain of IOB4 pin.
= 1, Enable the internal open-drain of IOB4 pin.
ODB5:= 0, Disable the internal open-drain of IOB5 pin.
= 1, Enable the internal open-drain of IOB5 pin.
ODB6:= 0, Disable the internal open-drain of IOB6 pin.
= 1, Enable the internal open-drain of IOB6 pin.
ODB7:= 0, Disable the internal open-drain of IOB7 pin.
= 1, Enable the internal open-drain of IOB7 pin.
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 31 of 81, FM8PE68B
EELING
FM8PE68B
2.1.36 DPHCON (PORTD Pull-high Control Register)
Read/Write-POR
R/W-0
B7
R/W-0
B6
R/W-0
B5
R/W-0
B4
R/W-0
B3
R/W-0
B2
R/W-0
B1
R/W-0
B0
Address
0x1D
Name
DPHCON
PHD7
PHD6
PHD5
PHD4
PHD3
PHD2
PHD1
PHD0
Accessed by IOST / IOSTR instruction.
Note: more bits default state, please refer to Table 2.9.
PHD0:= 0, Disable the internal pull-high of IOD0 pin.
= 1, Enable the internal pull-high of IOD0 pin.
PHD1:= 0, Disable the internal pull-high of IOD1 pin.
= 1, Enable the internal pull-high of IOD1 pin.
PHD2:= 0, Disable the internal pull-high of IOD2 pin.
= 1, Enable the internal pull-high of IOD2 pin.
PHD3:= 0, Disable the internal pull-high of IOD3 pin.
= 1, Enable the internal pull-high of IOD3 pin.
PHD4:= 0, Disable the internal pull-high of IOD4 pin.
= 1, Enable the internal pull-high of IOD4 pin.
PHD5:= 0, Disable the internal pull-high of IOD5 pin.
= 1, Enable the internal pull-high of IOD5 pin.
PHD6:= 0, Disable the internal pull-high of IOD6 pin.
= 1, Enable the internal pull-high of IOD6 pin.
PHD7:= 0, Disable the internal pull-high of IOD7 pin.
= 1, Enable the internal pull-high of IOD7 pin.
2.1.37 BPDCON (PORTB Pull-down Control Register)
Read/Write-POR
R/W-0
B7
R/W-0
B6
R/W-0
B5
R/W-0
B4
R/W-0
B3
R/W-0
B2
R/W-0
B1
R/W-0
B0
Address
0x1E
Name
BPDCON
PDB7
PDB6
PDB5
PDB4
PDB3
PDB2
PDB1
PDB0
Accessed by IOST / IOSTR instruction.
Note: more bits default state, please refer to Table 2.9.
PDB0:= 0, Disable the internal pull-down of IOB0 pin.
= 1, Enable the internal pull-down of IOB0 pin.
PDB1:= 0, Disable the internal pull-down of IOB1 pin.
= 1, Enable the internal pull-down of IOB1 pin.
PDB2:= 0, Disable the internal pull-down of IOB2 pin.
= 1, Enable the internal pull-down of IOB2 pin.
PDB3:= 0, Disable the internal pull-down of IOB3 pin.
= 1, Enable the internal pull-down of IOB3 pin.
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 32 of 81, FM8PE68B
EELING
FM8PE68B
PDB4:= 0, Disable the internal pull-down of IOB4 pin.
= 1, Enable the internal pull-down of IOB4 pin.
PDB5:= 0, Disable the internal pull-down of IOB5 pin.
= 1, Enable the internal pull-down of IOB5 pin.
PDB6:= 0, Disable the internal pull-down of IOB6 pin.
= 1, Enable the internal pull-down of IOB6 pin.
PDB7:= 0, Disable the internal pull-down of IOB7 pin.
= 1, Enable the internal pull-down of IOB7 pin.
2.1.38 INTEN1 (Interrupt Mask Register 1)
Read/Write-POR
-
B7
-
-
B6
-
-
B5
-
-
B4
-
-
B3
-
R/W-0
B2
R/W-0
B1
-
B0
-
Address
0x1F
Name
INTEN1
DIVIE
RFCIE
Accessed by IOST / IOSTR instruction.
Legend: - = unimplemented, read as ‘0’, more bits default state, please refer to Table 2.9.
RFCIE:RFC module interrupt enable bit.
= 0, Disable the RFC module interrupt.
= 1, Enable the RFC module interrupt.
DIVIE:Sub-oscillator (FS) divider overflow (0.5 sec) interrupt enable bit.
= 0, Disable the sub-oscillator divider interrupt. And the divider will be cleared.
= 1, Enable the sub-oscillator divider interrupt.
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 33 of 81, FM8PE68B
EELING
FM8PE68B
2.2 I/O Ports
Port A, port B, port C and port D are bi-directional tri-state I/O ports, and Port E and port F are output only ports.
Port A is a 4-pin I/O port. Port B, port C and port D are 8-pin I/O ports. Port E and port F are 8-pin output only ports.
All I/O pins (IOA<7:4>, IOB<7:0>, IOC<7:0> and IOD<7:0>) have data direction control registers (IOSTA, IOSTB,
IOSTC and IOSTD) which can configure these pins as output or input.
IOB<7:0> and IOD<7:0> have its corresponding pull-high control bits (BPHCON and DPHCON registers) to enable
the weak internal pull-high. The weak pull-high is automatically turned off when the pin is configured as an output
pin.
IOB<7:0> have its corresponding pull-down control bits (BPDCON register) to enable the weak internal pull-down.
The weak pull-down is automatically turned off when the pin is configured as an output pin.
IOB<7:0> have its corresponding open-drain control bits (BODCON register) to enable the open-drain output when
these pins are configured to be an output pin.
IOB<7:0> and IOD<7:0> also provide the input status change interrupt/wake-up function. Each pin has its
corresponding input change interrupt/wake-up enable bits (WUCON register) to select the input change
interrupt/wake-up source.
Figure 2.4: Block Diagram of I/O Pins
IOA7 ~ IOA4, IOB7 ~ IOB0, IOC7 ~ IOC0, IOD7 ~ IOD0:
DATA BUS
D
Q
IOST
Latch
IOST R
EN
Q
Q
I/O PIN
D
DATA
Latch
WR PORT
RD PORT
EN
Q
Pull-high/pull-down and open-drain are not shown in the figure
IOE7 ~ IOE0, IOF7 ~ IOF0:
DATA BUS
D
Q
Pin Function
Latch
WR SEGCON
EN
Q
Output PIN
D
Q
DATA
Latch
WR PORT
RD PORT
EN
Q
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 34 of 81, FM8PE68B
EELING
FM8PE68B
2.3 Timer0/WDT & Pre-scaler
2.3.1
Timer0
The Timer0 is a 8-bit timer/counter. The clock source of Timer0 can come from the internal clock or by an external
clock source (T0CKI pin).
2.3.1.1 Using Timer0 with an Internal Clock: Timer mode
Timer mode is selected by clearing the T0CS bit (T0CON<5>). In timer mode, the timer0 register (TMR0) will
increment every instruction cycle (without pre-scaler). If TMR0 register is written, the increment is inhibited for the
following two cycles.
2.3.1.2 Using Timer0 with an External Clock: Counter mode
Counter mode is selected by setting the T0CS bit (T0CON<5>). In this mode, Timer0 will increment either on
every rising or falling edge, setting by T0SE bit (T0CON<4>), of pin T0CKl. The incrementing edge is determined
by the T0SE bit (T0CON<4>).
2.3.1.3 Timer0 Pre-scaler
An 8-bit counter (down counter) is available as a pre-scaler for the Timer0. And the T0PS<2:0> bits (T0CON<2:0>)
determine pre-scaler ratio.
The pre-scaler is neither readable nor writable. All instructions writing to the TMR0 register will clear the pre-scaler.
On a RESET, the pre-scaler contains all ‘1’s.
2.3.2
Watchdog Timer (WDT)
The Watchdog Timer (WDT) is a free running on sub-oscillator on operation mode, and running on sub-oscillator or
on-chip RC oscillator selected by WDTS configuration bit on SLEEP mode. So the WDT can still run even if the
oscillator driver has been turned off if WDTS = Internal RC. During Normal mode, Green mode, or Idle mode
̅̅̅̅
operation, a WDT time-out will cause the device to reset and the TO bit (STATUS<4>) will be cleared.
The WDT can be disabled by clearing the control bit WDTEN (WDTCON<3>) to “0”.
The WDT time-out period is equal to (pre-scaler * (512/FS))
The “CLRWDT” instruction clears the WDT and the pre-scaler, and prevents it from timing out and generating a
device reset.
The “SLEEP” instruction resets the WDT and the pre-scaler. This gives the maximum SLEEP time before a WDT
Wake-up Reset.
2.3.2.1 Watchdog Pre-scaler
An 8-bit counter (down counter) is available as a pre-scaler for the Watchdog Timer (WDT). And the WDTPS<2:0>
bits (WDTCON<2:0>) determine pre-scaler ratio.
The pre-scaler is neither readable nor writable. A “CLRWDT” or “SLEEP” instruction will clear the pre-scaler. On a
RESET, the pre-scaler contains all ‘1’s.
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 35 of 81, FM8PE68B
EELING
FM8PE68B
Figure 2.5: Block Diagram of the Timer0/WDT Pre-scaler
Instruction Cycle
(Fosc/4 or Fosc/2)
0
8
Data Bus
8-Bit
Sync
TMR0
MUX
Prescaler
2 Cycles
Register
T0CKI
1
Set T0IF flag
On overflow
T0PS3:T0PS0
T0SE
T0CS
Figure 2.6: Block Diagram of the Timer0/WDT Pre-scaler
0
RC oscillator
8-Bit
Watchdog
Timer
8-Bit
Prescaler
WDT Time-out
MUX
1
Fs/2
WDTEN
WDTPS2:WDTPS0
WDTS
SLEEP
2.4 Interrupts
The FM8PE68B has up to ten sources of interrupt:
1. TMR0 overflow.
2. External interrupt INT0 pin.
3. External interrupt INT1 pin.
4. Counter 1 underflow.
5. Counter 2 underflow.
6. High-pulse width timer underflow.
7. Low-pulse width timer underflow.
8. Port B, Port D input status change.
9. RFC module interrupt.
10. Sub-oscillator (FS) divider overflow (0.5 sec).
INTFLAG is the interrupt flag register that recodes the interrupt requests in the relative flags.
A global interrupt enable bit, GIE (T0CON<6>), enables (if set) all un-masked interrupts or disables (if cleared) all
interrupts. Individual interrupts can be enabled/disabled through their corresponding enable bits in INTEN and
INTEN1 registers regardless of the status of the GIE bit.
When an interrupt event occur with the GIE bit and its corresponding interrupt enable bit are all set, the GIE bit will
be cleared by hardware to disable any further interrupts, and the next instruction will be fetched from address
003h~0021h based on the interrupt source. The interrupt flag bits must be cleared by software before re-enabling
GIE bit to avoid recursive interrupts.
The existing interrupt service routine does not allow other interrupt service routine to be executed. So if other
interrupts occur while the existing interrupt service routine is being executed, the hardware will save the later
interrupts. Only after the existing interrupt service routine is completed that the next interrupt service routine is
executed.
Executing the “ENI” instruction will set the GIE bit, and executing the “DISI” instruction will clear the GIE bit.
The RETFIE instruction exits the interrupt routine and set the GIE bit to re-enable interrupt.
When an interrupt is generated by the INT instruction, the next instruction will be fetched from address 0x002.
Each individual interrupt source has its own interrupt vector as the table list below. Before the interrupt subroutine
is executed, the contents of ACC and the STATUS register are initially saved by hardware. After the interrupt service
routine is completed, ACC and STATUS register are restored.
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 36 of 81, FM8PE68B
EELING
FM8PE68B
Table 2.1: Interrupt Vector
Interrupt Vector
0x003
Interrupt Source
TMR0 overflow
0x006
External interrupt INT0 pin
External interrupt INT1 pin
Counter 2 underflow
0x009
0x00C
0x00F
Counter 1 underflow
0x012
High-pulse width timer underflow
Low-pulse width timer underflow
Port B, Port D input status change wake-up
RFC module interrupt
0x015
0x018
0x01E
0x021
FS divider overflow (0.5 sec)
Figure 2.7: Interrupt Backup Diagram
Interrupt Occur
ACC
STACK of ACC
STATUS
STACK of STATUS
RETFIE instruction
2.4.1
Timer0 Overflow Interrupt
An overflow (0xFF 0x00) in the TMR0 register will set the flag bit T0IF (INTFLAG<0>). This interrupt can be
disabled by clearing T0IE bit (INTEN<0>).
2.4.2
External INT0 Pin Interrupt
External interrupt on INT0 pin is rising or falling edge triggered selected by INT0EDG (T0CON<7>).
When a valid edge appears on the INT0 pin the flag bit INT0IF (INTFLAG<1>) is set. This interrupt can be disabled
by clearing INT0IE bit (INTEN<1>).
2.4.3
External INT1 Pin Interrupt
External interrupt on INT1 pin is falling edge triggered.
When a falling edge appears on the INT1 pin the flag bit INT1IF (INTFLAG<2>) is set. This interrupt can be disabled
by clearing INT1IE bit (INTEN<2>).
2.4.4
Counter 1 Underflow Interrupt
An underflow (0x00 0xFF) in the counter 1 timer will set the flag bit C1IF (INTFLAG<3>). This interrupt can be
disabled by clearing C1IE bit (INTEN<3>).
2.4.5
Counter 2 Underflow Interrupt
An underflow (0x00 0xFF) in the counter 2 timer will set the flag bit C2IF (INTFLAG<4>). This interrupt can be
disabled by clearing C2IE bit (INTEN<4>).
2.4.6
High-pulse Width Timer Underflow Interrupt
An underflow (0x00 0xFF) in the high-pulse width timer will set the flag bit HPIF (INTFLAG<5>). This interrupt
can be disabled by clearing HPIE bit (INTEN<5>).
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 37 of 81, FM8PE68B
EELING
FM8PE68B
2.4.7
Low-pulse Width Timer Underflow Interrupt
An underflow (0x00 0xFF) in the low-pulse width timer will set the flag bit LPIF (INTFLAG<6>). This interrupt can
be disabled by clearing LPIE bit (INTEN<6>).
2.4.8
Port B / Port D Input Status Change Interrupt
An input status change on IOB<7:0> or IOD<7:0> will set flag bit PBDIF (INTFLAG<7>). This interrupt can be
disabled by clearing PBDIE bit (INTEN<7>).
Before the port B / port D input change interrupt is enabled, reading PORTB and/or PORTD (any instruction
accessed to PORTB and/or PORTD, including read/write instructions) is necessary. Any pin which corresponding
WUEn bit (WUCON<3:0>) is cleared to “0” or configured as output will be excluded from this function.
2.4.9
RFC Module Interrupt
After RFC conversion is finished, the RFCIF flag (RFCCON<5>) will be set. This interrupt can be disabled by
clearing RFCIE bit (INTEN1<1>).
2.4.10 Sub-oscillator (Fs) divider overflow (0.5 sec) interrupt
An overflow (0x3FFF 0x0000) in the Sub-oscillator (FS) divider will set the flag bit DIVIF (DIVCON<5>). This
interrupt can be disabled by clearing DIVIE bit (INTEN1<2>).
2.5 Power-down (SLEEP) and IDLE Mode
Power-down (SLEEP) or IDLE mode is entered by executing a SLEEP instruction. The “IDLE” bit (SYSCON<3>)
decides the intended mode of the SLEEP instruction.
Table 2.2: SLEEP or IDLE Mode after SLEEP instruction
IDLE
SLEEP / IDLE Mode Selection
SLEEP Mode
0
1
IDLE Mode
̅̅̅̅
̅̅̅̅
When SLEEP instruction is executed, the PD bit (STATUS<3>) is cleared, the TO bit is set, the watchdog timer
will be cleared and keeps running, and the oscillator driver is turned off.
All I/O pins maintain the status they had before the SLEEP instruction was executed.
2.5.1
Wake-up from SLEEP Mode
The device can wake-up from SLEEP mode and IDLE mode through one of the following events:
1. RSTB reset.
2. WDT time-out reset (if enabled).
3. External interrupt INT0 pin.
4. External interrupt INT1 pin.
5. Port B, Port D input status change.
The device can wake-up from IDLE mode through one of the additional events:
6. Counter 1 underflow.
7. Counter 2 underflow.
8. High-pulse width timer underflow.
9. Low-pulse width timer underflow.
10. Sub-oscillator (FS) divider overflow.
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 38 of 81, FM8PE68B
EELING
FM8PE68B
̅̅̅̅
̅̅̅̅
External RSTB reset and WDT time-out reset will cause a device reset. The PD and TO bits can be used to
̅̅̅̅
determine the cause of device reset. The PD bit is set on power-up and is cleared when SLEEP instruction is
̅̅̅̅
executed. The TO bit is cleared if a WDT time-out occurred.
For the device to wake-up through an PORTB/PORTD input status change, and the program will execute interrupt
service routine or next PC after wake-up. Any pin which corresponding /WUEmn bit (WUCON<3:0>) is set to “1” or
configured as output will be excluded from this function.
And GIE bit also decides whether or not the processor branches to the interrupt vector following wake-up. If GIE bit
was set, the program will execute interrupt service routine after wake-up; or if GIE bit was cleared, the program will
execute next PC after wake-up.
The system wake-up delay time is 18ms plus 16 sub-oscillator cycle time.
Table 2.3: Wake-up from SLEEP or IDLE Mode
Wake-up signal
Sleep mode
Idle mode
X
Green mode
Normal mode
Timer0 overflow
(T0IE = 1)
X
Interrupt (0x003) Interrupt (0x003)
Wake-up
Wake-up
INT0 pin
(INT0IE = 1)
+ interrupt (0x006)
+ next instruction
Wake-up
+ interrupt (0x009)
+ next instruction
+ interrupt (0x006) Interrupt (0x006) Interrupt (0x006)
+ next instruction
Wake-up
INT1 pin
(INT1IE = 1)
+ interrupt (0x009) Interrupt (0x009) Interrupt (0x009)
+ next instruction
Wake-up
Counter 1 underflow
(C1IE = 1)
X
X
X
X
+ interrupt (0x00C) Interrupt (0x00C) Interrupt (0x00C)
+ next instruction
Wake-up
Counter 2 underflow
(C2IE = 1)
+ interrupt (0x00F) Interrupt (0x00F) Interrupt (0x00F)
+ next instruction
Wake-up
High-pulse timer underflow
(HPIE = 1)
+ interrupt (0x012) Interrupt (0x012) Interrupt (0x012)
+ next instruction
Wake-up
Low-pulse timer underflow
(LPIE = 1)
+ interrupt (0x015) Interrupt (0x015) Interrupt (0x015)
+ next instruction
Port B, Port D
input status change
(PBDIE = 0)
Wake-up
+ next instruction
Wake-up
+ next instruction
X
X
X
X
Port B, Port D
input status change
(PBDIE = 1)
Wake-up
+ interrupt (0x018)
+ next instruction
Wake-up
+ interrupt (0x018)
+ next instruction
RFC conversion finished
(RFCIE = 1)
X
X
X
X
Interrupt (0x01E) Interrupt (0x01E)
Sub-oscillator (Fs) divider
overflow
Wake-up
+ interrupt (0x021) Interrupt (0x021) Interrupt (0x021)
+ next instruction
(DIVIE = 1)
WDT time out
(WDTS = FS)
Reset
Reset
Reset
WDT time out
(WDTS = Internal RC)
RSTB pin
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Reset
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 39 of 81, FM8PE68B
EELING
FM8PE68B
2.6 Infrared Remote Output (IROUT) / PWM Generator
The FM8PE68B devices can output infrared carrier in a friendly manner or in PWM standard waveform. The IR and
PWM waveform generated functions include an 8-bit down count timer, high-pulse width timer, low-pulse width timer,
and IR control register. The IROUT waveform is determined by IR control register (IRCON), Counter 1, 2 control
register (C12CON), high-pulse width timer, low-pulse width timer control register (HLPCON), Counter 2 preset
register (C2PR), high-pulse width timer preset register (HPPR), and low-pulse width timer preset register (LPPR).
Details on IR carrier, high-pulse time, and low pulse time are explained as follows:
If Counter 2 source clock is FT (FM or FS, select by C12CON register);
FT
IR carrier =
2 * [Counter 2 preset value (C2PR)+1]*pre-scaler
(The pre-scaler value is controlled by C12CON register)
If high-pulse width timer source clock is FT (FM or FS, select by HLPCON register);
pre-scaler * [ high-pulse width timer value (HPPR)+1]
High-pulse time =
FT
(The pre-scaler value is controlled by HLPCON register)
If low-pulse width timer source clock is FT (FM or FS, select by HLPCON register);
pre-scaler * [ low-pulse width timer value (LPPR)+1]
Low-pulse time =
FT
(The pre-scaler value is controlled by HLPCON register)
Figure 2.8: IROUT / PWM System Block Diagram
FM FS
Auto-reload buffer
(C2PR)
Auto-reload buffer
(HPPR)
Auto-reload buffer
(LPPR)
Pre-scaler
Pre-scaler
Pre-scaler
8
8
8
8-bit binary down counter
(counter 2)
8-bit binary down counter
(high-pulse width timer)
8-bit binary down counter
(low-pulse width timer)
8
8
IRcarrier
H/W Modulator
HF
LGP
IRE
IROUT
FM: Main-oscillator frequency; FS: Sub-oscillator frequency
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 40 of 81, FM8PE68B
EELING
FM8PE68B
Figure 2.9: IROUT Pin Output Waveform (HF=1, LGP=0)
The IROUT waveform can modulate IR carrier waveform when in low-pulse width time.
IR carrier
low-pulse width
high-pulse width
low-pulse width
high-pulse width
IRE
IROUT
Figure 2.10: IROUT Pin Output Waveform (HF=1, LGP=0)
The IROUT waveform can modulate IR carrier waveform when in low-pulse width time. When IRE goes from high
to low, the output waveform of IROUT will keep on transmitting till high-pulse width timer interrupt occurs.
IR carrier
low-pulse width
high-pulse width
low-pulse width
high-pulse width
IRE
IR disable
IROUT
Figure 2.11: IROUT Pin Output Waveform (HF=0, LGP=0)
The IROUT waveform cannot modulate IR carrier waveform when in low-pulse width time. So IROUT waveform is
determined by high-pulse time and low-pulse time. This mode can produce standard PWM waveform
IR carrier
low-pulse width
high-pulse width
low-pulse width
high-pulse width
IRE
IROUT
Figure 2.12: IROUT Pin Output Waveform (HF=0, LGP=0)
The IROUT waveform cannot modulate IR carrier waveform when in low-pulse width time. So IROUT waveform is
determined by high-pulse time and low-pulse time. This mode can produce standard PWM waveform. When IRE
goes from high to low, the output waveform of IROUT will keep on transmitting till high-pulse width timer interrupt
occurs.
IRcarrier
low-pulse width
high-pulse width
low-pulse width
high-pulse width
IRE
IR disable
IROUT
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 41 of 81, FM8PE68B
EELING
FM8PE68B
Figure 2.13: IROUT Pin Output Waveform (HF=1, LGP=1)
When LGP bit is set to high level, the high-pulse width timer is ignored. So IROUT waveform output from low-pulse
width timer is established.
IRcarrier
low-pulse width
low-pulse width
low-pulse width
IRE
IR disable
IROUT
Figure 2.14: IR / PWM function enable flowchart
Set IOA7 to output atate(IOSTA)
Set IOA7 to output atate(IOSTA)
Set IOA7 for IR/PWM output pin (IRCON)
EIROUT=1
Set IOA7 for IR/PWM output pin (IRCON)
Set Counter 2 clock source and prescaler
(C12CON)
Set High-pulse width timer, Low-pulse width timer
clock source and prescaler(HLPCON)
Set High-pulse width timer, Low-pulse width timer
clock source and prescaler(HLPCON)
Set Counter 2, High-pulse width timer, Low-pulse
width timer preset value(C2PR, HPPR, LPPR)
Set High-pulse width timer, Low-pulse width timer
preset value(HPPR, LPPR)
Enable IR (IRCON)
Enable IR (IRCON)
(IRE 1ꢀ, HF 1ꢀ)
(IRE 1ꢀ, HF 0ꢀ)
Enable High-pulse width timer, Low-pulse width
Enable High-pulse width timer, Low-pulse width
timer (INTEN0), execute ENIꢀinstruction
timer (INTEN0), execute ENIꢀinstruction
Enable Counter 2, High-pulse width timer,
Low-pulse width timer (CNTCON)
Enable High-pulse width timer, Low-pulse width
timer (CNTCON)
(a) IR application
(b) PWM application
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 42 of 81, FM8PE68B
EELING
FM8PE68B
2.7 LCD
The FM8PE68B devices can drive LCD of up to 32 segments and 4 commons that can drive a total of 4*32 dots.
LCD block is made up of LCD driver, display RAM, segment output pins, common output pins, and LCD operating
power supply pins. This circuit works on normal mode, green mode, and idle mode. The LCD duty, bias, the number
of segment, the number of common, and frame frequency are determined by the LCD controller register (LCDCON).
The basic structure contains a timing control that uses a subsystem clock to generate the proper timing for different
duty and display accesses. The LCDCON register is a command register for LCD driver which includes LCD
enable/disable, bias (1/2 and 1/3), duty (1/2, 1/3, 1/4), and LCD frame frequency control. The register LCDA is an
LCD RAM address control register. The register LCDD is an LCD RAM data buffer. LCD booster circuit can change
operation frequency to improve VLCD1 and VLCD2 drive capability.
Figure 2.15: LCD Bias Selection
BIAS
LCD bias
1/2 bias
1/3 bias
0
1
Figure 2.16: LCD Duty Selection
DUTY1
DUTY0
LCD duty
1/2 duty
1/3 duty
1/4 duty
0
0
1
0
1
X
Table 2.4: LCD Enable / Disable
LCDEN
LCD ON / OFF
Disable
0
1
Enable
Table 2.5: LCD Display Type Selection
TYPE
LCD display type
A type
0
1
B type
Table 2.6: LCD Frame Frequency Selection
LCD frame frequency (Fs=32.768KHZ
)
LCDF1
LCDF0
1/2 duty
1/3 duty
1/4 duty
0
0
1
1
0
1
0
1
FS/(256*2)=64.0
FS/(280*2)=58.5
FS/(304*2)=53.9
FS/(232*2)=70.6
FS/(172*3)=63.5
FS/(188*3)=58.0
FS/(204*3)=53.5
FS/(156*3)=70.0
FS/(128*4) =64.0
FS/(140*4) =58.5
FS/(152*4) =53.9
FS/(116*4) =70.6
FS: sub-oscillator frequency
Table 2.7: LCD Duty Selection
LCDBF1 LCDBF0
Booster frequency
0
0
1
1
0
1
0
1
FS
FS/4
FS/8
FS/16
FS: sub-oscillator frequency
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 43 of 81, FM8PE68B
EELING
FM8PE68B
Figure 2.17: The Connection of Charge Pump Circuit
1/3 Bias
1/2 Bias
VDD
VDD
VLCD2
CUP1
VLCD2
VLCD1
Vss
CUP1
CUP2
VLCD1
CUP2
Vss
Figure 2.18: The Initial Setting Flowchart for LCD Function
Set Port C, D, E, F for general I/O or LCD segment (SEGCON)
Set to output pins if LCD segment pin is selected (IOSTC, IOSTD)
Set LCD type, duty bias and LCD frame frequency (LCDCON)
Set LCD booster frequency (SYSCON)
Clear all LCD RAM (LCDA, LCDD)
Enable LCD (LCDCON)
Use LCDA and LCDD to implement LCD display (LCDA, LCDD)
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 44 of 81, FM8PE68B
EELING
FM8PE68B
Figure 2.19: LCD Waveform for 1/2 Bias, 1/2 Duty
1 frame
1 frame
Vdd
Vdd
COM0
COM1
SEGn
COM0
COM1
SEGn
VLCD2
Vss
VLCD2
Vss
Vdd
Vdd
VLCD2
Vss
VLCD2
Vss
Vdd
Vdd
VLCD2
Vss
VLCD2
Vss
Vdd
Vdd
VLCD2
Vss
VLCD2
Vss
SEGn-COM0
(ON)
SEGn-COM0
(ON)
-VLCD2
-Vdd
-VLCD2
-Vdd
Vdd
Vdd
VLCD2
Vss
VLCD2
Vss
SEGn-COM1
(OFF)
SEGn-COM1
(OFF)
-VLCD2
-Vdd
-VLCD2
-Vdd
A type
B type
Figure 2.20: LCD Waveform for 1/2 Bias, 1/3 Duty
1 frame
1 frame
Vdd
Vdd
VLCD2
VLCD2
Vss
COM0
COM1
COM2
SEGn
COM0
COM1
COM2
SEGn
Vss
Vdd
Vdd
VLCD2
Vss
VLCD2
Vss
Vdd
Vdd
VLCD2
Vss
VLCD2
Vss
Vdd
Vdd
VLCD2
Vss
VLCD2
Vss
Vdd
Vdd
VLCD2
Vss
VLCD2
Vss
SEGn-COM0
(ON)
SEGn-COM0
(ON)
-VLCD2
-Vdd
-VLCD2
-Vdd
Vdd
Vdd
VLCD2
Vss
VLCD2
Vss
SEGn-COM1
(OFF)
SEGn-COM1
(OFF)
-VLCD2
-Vdd
-VLCD2
-Vdd
Vdd
Vdd
VLCD2
Vss
VLCD2
Vss
SEGn-COM2
(OFF)
SEGn-COM2
(OFF)
-VLCD2
-VLCD2
-Vdd
-Vdd
A type
B type
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 45 of 81, FM8PE68B
EELING
FM8PE68B
Figure 2.21: LCD Waveform for 1/3 Bias, 1/3 Duty
1 frame
1 frame
Vdd
Vdd
VLCD2
VLCD2
VLCD1
Vss
COM0
COM0
COM1
COM2
SEGn
VLCD1
Vss
Vdd
Vdd
VLCD2
VLCD2
VLCD1
Vss
COM1
VLCD1
Vss
Vdd
Vdd
VLCD2
VLCD2
VLCD1
Vss
COM2
VLCD1
Vss
Vdd
Vdd
VLCD2
VLCD2
VLCD1
Vss
SEGn
VLCD1
Vss
Vdd
Vdd
VLCD2
VLCD2
VLCD1
Vss
VLCD1
SEGn-COM0
SEGn-COM0
(ON)
Vss
(ON)
-VLCD1
-VLCD2
-Vdd
-VLCD1
-VLCD2
-Vdd
Vdd
Vdd
VLCD2
VLCD2
VLCD1
Vss
VLCD1
SEGn-COM1
SEGn-COM1
(OFF)
Vss
(OFF)
-VLCD1
-VLCD2
-Vdd
-VLCD1
-VLCD2
-Vdd
Vdd
Vdd
VLCD2
VLCD2
VLCD1
Vss
VLCD1
SEGn-COM2
SEGn-COM2
(OFF)
Vss
(OFF)
-VLCD1
-VLCD2
-VLCD1
-VLCD2
-Vdd
-Vdd
A type
B type
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 46 of 81, FM8PE68B
EELING
FM8PE68B
Figure 2.22: LCD Waveform for 1/3 Bias, 1/4 Duty
1 frame
1 frame
Vdd
VLCD2
VLCD1
Vss
Vdd
Vdd
VLCD2
VLCD1
Vss
COM0
COM1
COM2
COM3
SEGn
COM0
COM1
COM2
COM3
SEGn
Vdd
VLCD2
VLCD1
Vss
VLCD2
VLCD1
Vss
Vdd
Vdd
VLCD2
VLCD1
Vss
VLCD2
VLCD1
Vss
Vdd
Vdd
VLCD2
VLCD1
Vss
VLCD2
VLCD1
Vss
Vdd
Vdd
VLCD2
VLCD1
Vss
VLCD2
VLCD1
Vss
Vdd
Vdd
VLCD2
VLCD1
Vss
VLCD2
VLCD1
Vss
SEGn-COM0
(ON)
SEGn-COM0
(ON)
-VLCD1
-VLCD2
-Vdd
-VLCD1
-VLCD2
-Vdd
Vdd
Vdd
VLCD2
VLCD1
Vss
VLCD2
VLCD1
Vss
SEGn-COM1
(OFF)
SEGn-COM1
(OFF)
-VLCD1
-VLCD2
-Vdd
-VLCD1
-VLCD2
-Vdd
Vdd
Vdd
VLCD2
VLCD1
Vss
VLCD2
VLCD1
Vss
SEGn-COM2
(OFF)
SEGn-COM2
(OFF)
-VLCD1
-VLCD2
-Vdd
-VLCD1
-VLCD2
-Vdd
Vdd
Vdd
VLCD2
VLCD1
Vss
-VLCD1
-VLCD2
-Vdd
VLCD2
VLCD1
Vss
-VLCD1
-VLCD2
-Vdd
SEGn-COM3
(OFF)
SEGn-COM3
(OFF)
A type
B type
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 47 of 81, FM8PE68B
EELING
FM8PE68B
2.8 Resistor to Frequency Converter (RFC)
The Resistor to Frequency Converter (RFC) can compare nineteen different sensors with the reference resistor
separately.
This RFC contains eighteen external pins:
CX: the oscillation Schmitt trigger input (IOA1/CX pin).
RFC0 ~ RFC2: the resistor/sensor output pin 0 ~ 2 (RFC0, RFC1, and RFC2 pins)
Figure 2.23: The Block Diagram of RFC
RFCS1:0 = 2
RRFC2
Counter active signal, controlled by
CX pin signal if RFCMOD = 0, or
START bit if RFCMOD = 1
RFCS1:0 = 1
RFC2
RRFC1
Set RFCIF Flag
when count finished
RFC1
RFCS1:0 = 0
RRFC0
EN
1
15-bit counter
CLKIN
RFC0
Mux
0
Fosc
CX
CCx
RFCMOD
Table 2.8: The Description of RFC Control Bits
Select one the RFC oscillation network of RFCx (x = 0 to 2). The selected RFCx pin will be
RFCS1:RFCS0 configured as RFCx output pin if RFCON = 1. Other RFCx pins will still behave as tristate input
pins. If RFCON = 0, all RFCx pins will behave as tristate input pins.
= 0, Enable/disable the counter by CX signal, and the clock source of the counter is the internal
system clock (FOSC).
RFCMOD
= 1, Enable/disable the counter by START bit, and the clock source of the counter is the CX
signal.
= 0, Stop the RFC conversion
START
= 1, RFC counter start to convert. Reset by hardware after conversion is finished.
Note: Don’t clear START bit by software during the RFC conversion.
= 0, Disable RFC module, all the RFCx and CX pins will behave as tristate input pins.
= 1, Enable RFC module.
RFCON
2.8.1
RC Oscillator Network
The RFC circuitry may build up 3 RC oscillation networks through RFC0 to RFC2 and CX pins with external resistors.
Only one RC oscillation network may be active at a time. When the oscillation network is built up, the count active
pulse will be generated by the oscillation network and transferred to the 15-bit counter through the CX pin. It will
then enable or disable the 15-bit counter in order to count the oscillation clock. The 15-bit RFC counter is cleared
when a value is written to RFCCON register, RFCON bit is cleared, and during any kind of reset as well.
How to build the RC oscillation network:
1. Connect the resistor and capacitor on RFCx (x = 0 to 2, if needed) and CX pins.
2. Switch all of the needed RFCx and CX pins to input mode.
3. Enable the RFC module by set the RFCON bit.
4. Select one of RFCx pins by RFCS1:RFCS0 bits to enable the output pin for RC networks respectively. The
selected RFCx will output low at this time. Other RFCx pins will become of a tristate type.
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 48 of 81, FM8PE68B
EELING
FM8PE68B
5. Set START bit to enable the RC oscillation network and 15-bit counter. The RC oscillation network will not
operate if this bit has not been set. Clear the START bit by H/W or S/W will finish the conversion, and the RFCIF
flag will be set if RFCMOD = 0 (if enable).
2.8.2
Enable/Disable the Counter by CX Signal
In this mode, CX pin is the signal to control the counter period and the clock source of the counter comes from the
internal system clock (FOSC).
The counter will start to count after the first rising edge signal applied on the CX pin after the RFCON bit
(RFCCON<7>) is set. Once the second rising edge is applied to the CX pin after the counter is enabled, the counter
will stop counting. And after the second falling edge is applied to the CX pin, the RFC block will clear the START bit
and set the RFC interrupt flag RFCIF bit (RFCCON<5>) if RFCIE bit (INTEN1<1>) is set.
User also can be polling the RFCON or RFCIF bit to check if the conversion is finished.
Figure 2.24: The Sample of the RFC Counter Controlled by the CX Pin (RFCMOD = 0)
START
CX signal on pin
CX signal
By S/W
By H/W
Counter active
RFC Counter
Fosc
0
1
2
3
N-2 N-1
N
Counter active
By S/W
Counter starts
to count
Counting stops, caused by
the 2nd falling edge of CX
2.8.3
Enable/Disable the Counter by START Bit
In this mode, START bit is the signal to control the counter period and the clock source of the counter comes from
the CX pin.
The counter will start to count after the START bit (RFCCON<6>) is set. Once the START bit is cleared by S/W, the
counter will stop counting. And after the second falling edge is applied to the CX pin, the RFC block will clear the
START bit and set the RFC interrupt flag RFCIF bit (RFCCON<5>) is not needed.
Figure 2.25: The Sample of the RFC Counter Controlled by the START Bit (RFCMOD = 1)
START
Counter active
RFC Counter
CX signal
By S/W
0
1
2
3
4
5
6
7
N-2 N-1
N
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 49 of 81, FM8PE68B
EELING
FM8PE68B
2.9 Reset
FM8PE68B devices may be RESET in one of the following ways:
1. Power-on Reset (POR)
2. Brown-out Reset (BOR)
3. RSTB Pin Reset
4. WDT time-out Reset
Some registers are not affected in any RESET condition. Their status is unknown on Power-on Reset and
unchanged in any other RESET. Most other registers are reset to a “reset state” on Power-on Reset, RSTB or WDT
Reset.
A Power-on RESET pulse is generated on-chip when VDD rise is detected. To use this feature, the user merely ties
the RSTB pin to VDD
.
On-chip Low Voltage Detector (LVD) places the device into reset when VDD is below a fixed voltage. This ensures
that the device does not continue program execution outside the valid operation VDD range. Brown-out RESET is
typically used in AC line or heavy loads switched applications.
A RSTB or WDT Wake-up from SLEEP also results in a device RESET, and not a continuation of operation before
SLEEP.
̅̅̅̅
̅̅̅̅
The TO and PD bits (STATUS<4:3>) are set or cleared depending on the different reset conditions.
2.9.1
Power-up Reset Timer (PWRT)
The Power-up Reset Timer provides a nominal 18ms delay after Power-on Reset (POR), Brown-out Reset (BOR),
RSTB Reset or WDT time-out Reset. The device is kept in reset state as long as the PWRT is active.
The PWDT delay will vary from device to device due to VDD, temperature, and process variation.
2.9.2
Oscillator Start-up Timer (OST)
The OST timer provides a 16 sub-oscillator cycle delay (from OSCI input) after the PWRT delay (18ms) is over. This
delay ensures that the X’tal oscillator or resonator has started and stabilized. The device is kept in reset state as
long as the OST is active.
This counter only starts incrementing after the amplitude of the OSCI signal reaches the oscillator input thresholds.
2.9.3
Reset Sequence
When Power-on Reset (POR), Brown-out Reset (BOR), RSTB Reset or WDT time-out Reset is detected, the reset
sequence is as follows:
1. The reset latch is set and the PWRT & OST are cleared.
2. When the internal POR, BOR, RSTB Reset or WDT time-out Reset pulse is finished, then the PWRT begins
counting.
3. After the PWRT time-out, the OST is activated.
4. And after the OST delay is over, the reset latch will be cleared and thus end the on-chip reset signal.
The totally system reset delay time is 18ms plus 16 sub-oscillator cycle time.
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 50 of 81, FM8PE68B
EELING
FM8PE68B
Figure 2.26: Simplified Block Diagram of on-chip Reset Circuit
WDT
Time-out
WDT
Module
RSTB
VDD
S
R
Q
Q
Reset
Latch
Low Voltage
Detector
(LVD)
BOR
CHIP RESET
Power-on
Reset
POR
(POR)
RESET
RESET
On-Chip
RC OSC
Power-up
Reset Timer
(PWRT)
Oscillator
Start-up Timer
(OST)
OSCI
Figure 2.27: Time-out Sequence on Power-up (RSTB Pin Tied to VDD
)
VDD
RSTB
INTERNAL PWRB
PWRT TIME-OUT
TPWRT
TOST
OST TIME-OUT
INTERNAL RESET
Note: TPWRT = 18ms; TOST = 16 sub-oscillator cycle time
Figure 2.28: Time-out Sequence on Power-up (RSTB Pin Not Tied to VDD
)
VDD
RSTB
INTERNAL PWRB
PWRT TIME-OUT
TPWRT
TOST
OST TIME-OUT
INTERNAL RESET
Note: TPWRT = 18ms; TOST = 16 sub-oscillator cycle time
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 51 of 81, FM8PE68B
EELING
FM8PE68B
Table 2.9: Reset Conditions for All Registers
Power-on Reset
Brown-out Reset
RSTB Reset
Wake-up
from pin change
Register
Address
WDT Reset
uuuu uuuu
1111 ----
1111 1111
1111 1111
1111 1111
-000 0000
uuuu uuuu
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
1111 0000
0*** 0000
1011 1111
**** 0111
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
---- -00-
uuuu uuuu
0000 0000
0000 0000
*00# #uuu
00uu uuuu
xxxx --*-
xxxx xxxx
xxxx xxxx
xxxx xxxx
1100 -000
---0 0000
xxxx uuuu
xxxx 0000
x000 100%
000- 0000
1111 1111
1111 1111
0000 --00
0000 0000
ACC
N/A
0x05
xxxx xxxx
1111 ----
1111 1111
1111 1111
1111 1111
-000 0000
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
1111 0000
0*** 0000
1011 1111
**** 0111
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
---- -00-
xxxx xxxx
0000 0000
0000 0000
*001 1xxx
00xx xxxx
xxxx --*-
xxxx xxxx
xxxx xxxx
xxxx xxxx
1100 -000
---0 0000
xxxx xxxx
xxxx 0000
x000 100%
000- 0000
1111 1111
1111 1111
0000 --00
0000 0000
uuuu uuuu
uuuu ----
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
u*** uuuu
uuuu uuuu
**** uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- -uu-
uuuu uuuu
uuuu uuuu
See Table 2.3
*uu# #uuu
uuuu uuuu
uuuu --*-
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu -uuu
---u uuuu
xxxx uuuu
xxxx uuuu
xuuu uuuu
uuu- uuuu
uuuu uuuu
uuuu uuuu
uuuu --uu
uuuu uuuu
IOSTA
IOSTB
IOSTC
IOSTD
DRAMA
DRAMD
C1PR
0x06
0x07
0x08
0x09
0x0A
0x0B
C2PR
0x0C
HPPR
0x0D
LPPR
0x0E
INTEN
SEGCON
WUCON
T0CON
WDTCON
C12CON
HLPCON
BPHCON
BODCON
DPHCON
BPDCON
INTEN1
INDF
0x0F
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x00, unbanked
0x01, unbanked
0x02, unbanked
0x03, unbanked
0x04, unbanked
0x05, unbanked
0x06, unbanked
0x07, unbanked
0x08, unbanked
0x09, bank 0 & 2
0x0A, bank 0 & 2
0x0B, bank 0 & 2
0x0C, bank 0 & 2
0x0D, bank 0 & 2
0x0E, bank 0 & 2
0x09, bank 1 & 3
0x0A, bank 1 & 3
0x0B, bank 1 & 3
0x0C, bank 1 & 3
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PORTD
LCDCON
LCDA
LCDD
CNTCON
SYSCON
IRCON
PORTE
PORTF
RFCCON
RFCDL
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 52 of 81, FM8PE68B
EELING
FM8PE68B
Power-on Reset
Brown-out Reset
0000 0000
RSTB Reset
Wake-up
Register
Address
WDT Reset
0000 0000
010- ----
0000 0000
from pin change
RFCDH
DIVCON
INTFLAG
0x0D, bank 1 & 3
0x0E, bank 1 & 3
0x0F, unbanked
uuuu uuuu
uuu- ----
uuuu uuuu
010- ----
0000 0000
General Purpose
Registers
0x10 ~ 0x3F
xxxx xxxx
uuuu uuuu
uuuu uuuu
Legend:u = unchanged, x = unknown, - and * = unimplemented, # = refer to the following table for possible values.
% = refer to the configuration bit “HLFS”.
̅̅̅̅ ̅̅̅̅
Table 2.10: TO / PD Status after Reset or Wake-up
̅̅̅̅
̅̅̅̅
TO
PD
RESET was caused by
Power-on Reset
1
1
u
1
0
0
1
1
u
0
1
0
Brown-out reset
RSTB Reset during normal operation
RSTB Reset during SLEEP
WDT Reset during normal operation
WDT Wake-up during SLEEP
Legend: u = unchanged
̅̅̅̅ ̅̅̅̅
Table 2.11: Events Affecting TO / PD Status Bits
̅̅̅̅
̅̅̅̅
PD
Event
TO
Power-on
1
0
1
1
1
u
0
1
WDT Time-Out
SLEEP instruction
CLRWDT instruction
Legend: u = unchanged
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 53 of 81, FM8PE68B
EELING
FM8PE68B
2.10 Hexadecimal Convert to Decimal (HCD)
Decimal format is another number format for FM8PE68B. When the content of the data memory has been assigned
as decimal format, it is necessary to convert the results to decimal format after the execution of ALU instructions.
When the decimal converting operation is processing, all of the operand data (including the contents of the data
memory (RAM), accumulator (ACC), immediate data, and look-up table) should be in the decimal format, or the
results of conversion will be incorrect.
Instruction DAA can convert the ACC data from hexadecimal to decimal format after any addition operation and
restored to ACC.
The conversion operation is illustrated in example 2.2.
Example 2.2: DAA CONVERSION
Code
#include <8PE68B.ASH>
…
MOVIA 0x90
MOVAR 0x30
MOVIA 0x10
;Set immediate data = decimal format number “90” (ACC 0x90)
;Load immediate data “90” to data memory address 0x30
;Set immediate data = decimal format number “10” (ACC 0x10)
ADDAR 0x30,A ;Contents of the data memory address 0x30 and ACC are binary-added
;the result loads to the ACC (ACC 0xA0, C 0)
DAA
0x30,A ;Convert the content of ACC to decimal format, and restored to ACC
;The result in the ACC is “00” and the carry bit C is “1”. This represents
;the decimal number “100”
…
Instruction DAS can convert the ACC data from hexadecimal to decimal format after any subtraction operation and
restored to ACC.
The conversion operation is illustrated in example 2.3.
Example 2.3: DAS CONVERSION
Code
#include <8PE68B.ASH>
…
MOVIA 0x10
MOVAR 0x30
MOVIA 0x20
;Set immediate data = decimal format number “10” (ACC 0x10)
;Load immediate data “90” to data memory address 0x30
;Set immediate data = decimal format number “20” (ACC 0x20)
SUBAR 0x30,A ;Contents of the data memory address 0x30 and ACC are binary-subtracted
;the result loads to the ACC (ACC 0xF0, C 0)
DAS
0x30,A ;Convert the content of ACC to decimal format, and restored to ACC
;The result in the ACC is “90” and the carry bit C is “0”. This represents
;the decimal number “ -10”
…
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 54 of 81, FM8PE68B
EELING
FM8PE68B
2.11 Oscillator Configurations
FM8PE68B can be operated in four different oscillator modes, and two different sub-oscillator modes. Users can
program FOSC configuration bit to select the appropriate modes:
Selectable main-oscillator options:
- ERIC: External Resistor/Internal Capacitor Oscillator
- XT: Crystal/Resonator Oscillator
- LF: Low Frequency Crystal Oscillator
- PLL: Phase lock loop
Selectable sub-oscillator options:
- ERIC: External Resistor/Internal Capacitor Oscillator
- LF: Low Frequency Crystal Oscillator
In LF, or XT modes, a crystal or ceramic resonator in connected to the OSCI/XIN and OSCO/XOUT pins to establish
oscillation. When in LF or XT modes, the devices can have an external clock source drive the OSCI pin.
The ERIC device option offers additional cost savings for timing insensitive applications. The RC oscillator
frequency is a function of the resistor (Rext), and the process parameter.
In PLL mode, connect 0.01uF capacitor to the OSCI pin and VSS
.
Figure 2.29: HF, XT or LF Oscillator Modes (Crystal Operation or Ceramic Resonator)
FM8PE68B
C1
OSCI/XIN
R1
VDD
SLEEP
X`TAL
RS
RF
0.1uF
VSS
OSCO/XOUT
C2
Internal
Circuit
Figure 2.30: HF, XT or LF Oscillator Modes (External Clock Input Operation)
FM8PE68B
OSCI/XIN
VDD
Clock from
External System
0.1uF
VSS
OSCO/XOUT
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 55 of 81, FM8PE68B
EELING
FM8PE68B
Figure 2.31: ERIC Oscillator Mode (External R, Internal C Oscillator)
FM8PE68B
Rext
OSCI/XIN
VDD
Internal
Circuit
Cext
C
0.1uF
VSS
(300pF~0.1uF)
OSCO/XOUT
/2, /4
The typical oscillator frequency vs. external resistor is as following table
When Cext = 0.01uf (103)
Frequency
455KHZ
1MHZ
Rext @ 3V
392.3K
201.4K
52.1K
Rext @ 5V
447.4K
216.8K
54.7K
4MHZ
8MHZ
25.4K
26.6K
16MHZ
NA
12.4K
Note: Values are provided for design reference only.
Figure 2.32: PLL Oscillator Mode
FM8PE68B
OSCI
VDD
PLL
Internal
Circuit
0.01uF
0.1uF
VSS
Open
/2, /4
OSCO
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 56 of 81, FM8PE68B
EELING
FM8PE68B
2.12 Configuration Words
Table 2.12: Configuration Words
Name
Description
Main-Oscillator Selection Bit
ERIC mode (external R & internal C) (default)
Main_Fosc XT mode
LF mode
PLL mode
Sub-Oscillator Selection Bit
Sub_Fosc ERIC mode (external R & internal C)
LF mode
Watchdog Timer Enable Bit
WDTEN
WDT enabled (default)
WDT disabled
Code Protection Bit
PROTECT OTP code protection off (default)
OTP code protection on
Low Voltage Detector Selection Bit
Enable, LVDT voltage = 2.4V (default)
Enable, LVDT voltage = 2.2V, controlled by SLEEP
Enable, LVDT voltage = 2.2V
Enable, LVDT voltage = 2.0V, controlled by SLEEP
LVDT
Enable, LVDT voltage = 2.0V
Enable, LVDT voltage = 1.8V, controlled by SLEEP
Enable, LVDT voltage = 1.8V
Instruction Period Selection Bits
OSCD
HLFS
Four oscillator periods (default)
Two oscillator periods
Main or Sub-oscillator Selection Bit
CPU is set to select main-oscillator when reset occurred (default)
CPU is set to select sub-oscillator when reset occurred
Cycle Selection for CALL and GOTO instruction
2 instruction cycles (default)
CYES
1 instruction cycles
Type Selection Bit
TYPE
64-pins (A/B Type) is selected (default)
44-pins (C Type) is selected
Read Port Control Bit for Output Pins
From registers (default)
RDPORT
From pins
I/O Pin Input Buffer Control Bit
SCHMITT With Schmitt-trigger (default)
Without Schmitt-trigger
Watchdog Timer Clock Source in Sleep Mode
Fs (default)
Internal RC
WDTS
PCHS
Program Counter High Bits Operation Selection Bit for Instruction with PCL as Destination
PC<11:10> = PG<1:0>; PC<9:8> is unchanged. (default)
PC<11: 8> is unchanged.
Wake-up Trigger Control Bit
WUTRIG
Falling edge trigger (default)
Low level trigger
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 57 of 81, FM8PE68B
EELING
FM8PE68B
3.0 INSTRUCTION SET
Mnemonic,
Operands
Status
Cycles
Description
Operation
Affected
BCR
R, bit Clear bit in R
R, bit Set bit in R
0 R<b>
1 R<b>
1
1
-
-
-
-
-
BSR
BTRSC
BTRSS
NOP
R, bit Test bit in R, Skip if Clear
R, bit Test bit in R, Skip if Set
No Operation
Skip if R<b> = 0
Skip if R<b> = 1
No operation
1/2/3(1)
1/2/3(1)
1
0x00 WDT,
0x00 WDT pre-scaler
0x00 WDT,
̅̅̅̅ ̅̅̅̅
CLRWDT
SLEEP
DAA
Clear Watchdog Timer
1
1
1
TO,PD
̅̅̅̅ ̅̅̅̅
Go into power-down mode
TO,PD
0x00 WDT pre-scaler
Adjust ACC’s data format from HEX to
DEC after any addition operation
ACC(hex) ACC (dec)
C
Adjust ACC’s data format from HEX to
DEC after any subtraction operation
DAS
ACC(hex) ACC (dec)
Top of Stack PC
1
2
2
-
-
-
RETURN
RETFIE
Return from subroutine
Top of Stack PC,
1 GIE
Return from interrupt, set GIE bit
PC + 1 Top of Stack
0x002 PC
INT
S/W interrupt
2
-
IOST
R
R
Load IOST register
Read IOST register
ACC IOST register
IOST register ACC
1
1
-
-
IOSTR
PC<7:0> + ACC PC<7:0>
PC<9:8> unchanged
TBL
Table look-up
1
C, DC, Z
PG<1:0> PC<11:10>
CLRA
CLRR
MOVAR
MOVR
MOV2
DECR
Clear ACC
Clear R
0x00 ACC
0x00 R
ACC R
R dest
1
1
1
1
1
1
Z
Z
-
R
R
Move ACC to R
R, d Move R
Z
-
R, d Move R
R dest
R, d Decrement R
R - 1 dest
Z
R - 1 dest,
Skip if result = 0
DECRSZ
INCR
R, d Decrement R, Skip if 0
R, d Increment R
1/2/3(1)
1
-
Z
-
R + 1 dest
R + 1 dest,
Skip if result = 0
INCRSZ
R, d Increment R, Skip if 0
1/2/3(1)
ADDAR
SUBAR
ADCAR
SBCAR
ANDAR
IORAR
XORAR
COMR
R, d Add ACC and R
R + ACC dest
R - ACC dest
1
1
1
1
1
1
1
1
C, DC, Z
R, d Subtract ACC from R
R, d Add ACC and R with Carry
R, d Subtract ACC from R with Carry
R, d AND ACC with R
C, DC, Z
R + ACC + C dest
C, DC, Z
̅̅̅̅̅̅̅
R + ACC + C dest
C, DC, Z
ACC and R dest
ACC or R dest
R xor ACC dest
Z
Z
Z
Z
R, d Inclusive OR ACC with R
R, d Exclusive OR ACC with R
R, d Complement R
ꢀ
R dest
R<7> C,
RLR
R, d Rotate left R through Carry
R<6:0> dest<7:1>,
C dest<0>
1
C
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 58 of 81, FM8PE68B
EELING
FM8PE68B
Mnemonic,
Operands
Status
Cycles
Description
Operation
C dest<7>,
Affected
RRR
R, d Rotate right R through Carry
R<7:1> dest<6:0>,
R<0> C
1
C
R<3:0> dest<7:4>,
R<7:4> dest<3:0>
SWAPR
R, d Swap R
1
-
MOVIA
ADDIA
SUBIA
ANDIA
IORIA
I
I
I
I
I
I
Move Immediate to ACC
I ACC
1
1
1
1
1
1
-
Add ACC and Immediate
Subtract ACC from Immediate
AND Immediate with ACC
OR Immediate with ACC
I + ACC ACC
I - ACC ACC
ACC and I ACC
ACC or I ACC
ACC xor I ACC
C, DC, Z
C, DC, Z
Z
Z
Z
XORIA
Exclusive OR Immediate to ACC
I ACC,
Top of Stack PC
RETIA
I
Return, place Immediate in ACC
2
-
BANK
PAGE
I
I
Move Immediate to memory bank bits
I RP<1:0>
1
1
-
-
Move Immediate to program page bits I PG<1:0>
PC + 1 Top of Stack,
I PC<9:0>
CALL
I
I
I
I
Call subroutine
2
2
3
3
-
-
-
-
PG<1:0> PC<11:10>
I PC<9:0>
PG<1:0> PC<11:10>
PC + 1 Top of Stack,
I PC<11:0>
I<11:10> PG<1:0>
I PC<11:0>
I<11:10> PG<1:0>
GOTO
FCALL
FGOTO
Unconditional branch
Call subroutine
Unconditional branch
Note:1.2 cycles for skip, else 1 cycle. (3 cycles if skip and followed by a 2-word instruction FCALL/FGOTO)
2. bit: Bit address within an 8-bit register R
R: Register address (0x00 to 0x3F)
I: Immediate data
ACC: Accumulator
d: Destination select;
=0 (store result in ACC)
=1 (store result in file register R)
dest: Destination
PC: Program Counter
RP: RAM Page(Bank) Select Bits
PG: Program Memory Page Select Bits
WDT: Watchdog Timer Counter
GIE: Global interrupt enable bit
̅̅̅̅
TO: Time-out bit
̅̅̅̅
PD: Power-down bit
C: Carry bit
DC: Half carry bit
Z: Zero bit
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 59 of 81, FM8PE68B
EELING
FM8PE68B
ADCAR
Add ACC and R with Carry
Syntax:
ADCAR R, d
Operands:
0x00≤R≤0x3F
d∈[0,1]
Operation:
Status Affected:
Description:
R + ACC + C dest
C, DC, Z
Add the contents of the ACC register and register ‘R’ with Carry. If ‘d’ is 0 the result is stored
in the ACC register. If ‘d’ is ‘1’ the result is stored back in register ‘R’.
1
Cycles:
ADDAR
Syntax:
Add ACC and R
ADDAR R, d
Operands:
0x00≤R≤0x3F
d∈[0,1]
Operation:
ACC + R dest
Status Affected:
Description:
C, DC, Z
Add the contents of the ACC register and register ‘R’. If ‘d’ is 0 the result is stored in the ACC
register. If ‘d’ is ‘1’ the result is stored back in register ‘R’.
1
Cycles:
ADDIA
Add ACC and Immediate
Syntax:
ADDIA I
Operands:
Operation:
Status Affected:
Description:
0x00≤I≤0xFF
ACC + I ACC
C, DC, Z
Add the contents of the ACC register with the 8-bit immediate ‘I’. The result is placed in the
ACC register.
1
Cycles:
ANDAR
Syntax:
AND ACC and R
ANDAR R, d
Operands:
0x00≤R≤0x3F
d∈[0,1]
Operation:
ACC and R dest
Status Affected:
Description:
Z
The contents of the ACC register are AND’ed with register ‘R’. If ‘d’ is 0 the result is stored
in the ACC register. If ‘d’ is ‘1’ the result is stored back in register ‘R’.
1
Cycles:
ANDIA
AND Immediate with ACC
Syntax:
ANDIA I
Operands:
Operation:
Status Affected:
Description:
0x00≤I≤0xFF
ACC AND I ACC
Z
The contents of the ACC register are AND’ed with the 8-bit immediate ‘I’. The result is placed
in the ACC register.
1
Cycles:
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 60 of 81, FM8PE68B
EELING
FM8PE68B
BANK
Move Immediate to memory bank bits
Syntax:
BANK
I
Operands:
Operation:
Status Affected:
Description:
Cycles:
0x0≤I≤0x3
I RP<1:0>
None
The memory bank bits are loaded with the 2-bit immediate ‘I’.
1
BCR
Clear Bit in R
BCR R, b
0x00≤R≤0x3F
0x0≤b≤0x7
0 R<b>
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
None
Clear bit ‘b’ in register ‘R’.
1
BSR
Set Bit in R
BSR R, b
0x00≤R≤0x3F
0x0≤b≤0x7
1 R<b>
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
None
Set bit ‘b’ in register ‘R’.
1
BTRSC
Test Bit in R, Skip if Clear
Syntax:
BTRSC R, b
Operands:
0x00≤R≤0x3F
0x0≤b≤0x7
Operation:
Skip if R<b> = 0
Status Affected:
Description:
None
If bit ‘b’ in register ‘R’ is 0 then the next instruction is skipped.
If bit ‘b’ is 0 then next instruction fetched during the current instruction execution is discarded,
and a NOP is executed instead making this a 2-cycle instruction.
Cycles:
1/2 (3 cycles if skip and followed by a 2-word instruction FCALL/FGOTO)
BTRSS
Test Bit in R, Skip if Set
Syntax:
BTRSS R, b
Operands:
0x00≤R≤0x3F
0x0≤b≤0x7
Operation:
Skip if R<b> = 1
Status Affected:
Description:
None
If bit ‘b’ in register ‘R’ is ‘1’ then the next instruction is skipped.
If bit ‘b’ is ‘1’, then the next instruction fetched during the current instruction execution, is
discarded and a NOP is executed instead, making this a 2-cycle instruction.
1/2 (3 cycles if skip and followed by a 2-word instruction FCALL/FGOTO)
Cycles:
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 61 of 81, FM8PE68B
EELING
Subroutine Call
FM8PE68B
CALL
Syntax:
CALL I
Operands:
Operation:
0x000≤I≤0x3FF
PC + 1 Top of Stack,
I PC<9:0>
PG<1:0> PC<11:10>
None
Subroutine call. First, return address (PC+1) is pushed onto the stack. The 10-bit
Status Affected:
Description:
immediate address is loaded into PC bits <9:0>.
2
Cycles:
CLRA
Clear ACC
Syntax:
CLRA
Operands:
Operation:
None
0x00 ACC;
1 Z
Status Affected:
Description:
Cycles:
Z
The ACC register is cleared. Zero bit (Z) is set.
1
CLRR
Clear R
Syntax:
CLRR
R
Operands:
Operation:
0x00≤R≤0x3F
0x00 R;
1 Z
Status Affected:
Description:
Cycles:
Z
The contents of register ‘R’ are cleared and the Z bit is set.
1
CLRWDT
Syntax:
Clear Watchdog Timer
CLRWDT
Operands:
Operation:
None
0x00 WDT;
0x00 WDT pre-scaler (if assigned);
̅̅̅̅
1 TO;
̅̅̅̅
1 PD
̅̅̅̅ ̅̅̅̅
Status Affected:
Description:
TO, PD
The CLRWDT instruction resets the WDT. It also resets the pre-scaler, if the pre-scaler is
̅̅̅̅
̅̅̅̅
assigned to the WDT and not Timer0. Status bits TO and PD are set.
1
Cycles:
COMR
Complement R
COMR R, d
0x00≤R≤0x3F
d∈[0,1]
Syntax:
Operands:
ꢀ
Operation:
R dest
Status Affected:
Description:
Z
The contents of register ‘R’ are complemented. If ‘d’ is 0 the result is stored in the ACC
register. If ‘d’ is 1 the result is stored back in register ‘R’.
1
Cycles:
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 62 of 81, FM8PE68B
EELING
FM8PE68B
DAA
Adjust ACC’s data format from HEX to DEC
Syntax:
DAA
Operands:
Operation:
Status Affected:
Description:
None
ACC(hex) ACC(dec)
C
Convert the ACC data from hexadecimal to decimal format after any addition operation and
restored to ACC.
1
Cycles:
DAS
Adjust ACC’s data format from HEX to DEC
Syntax:
DAS
Operands:
Operation:
Status Affected:
Description:
None
ACC(hex) ACC(dec)
None
Convert the ACC data from hexadecimal to decimal format after any subtraction operation
and restored to ACC.
1
Cycles:
DECR
Decrement R
Syntax:
Operands:
DECR R, d
0x00≤R≤0x3F
d∈[0,1]
Operation:
R - 1 dest
Status Affected:
Description:
Z
Decrement of register ‘R’. If ‘d’ is 0 the result is stored in the ACC register. If ‘d’ is 1 the
result is stored back in register ‘R’.
1
Cycles:
DECRSZ
Syntax:
Decrement R, Skip if 0
DECRSZ R, d
Operands:
0x00≤R≤0x3F
d∈[0,1]
Operation:
R - 1 dest; skip if result =0
Status Affected:
Description:
None
The contents of register ‘R’ are decrement. If ‘d’ is 0 the result is placed in the ACC register.
If ‘d’ is 1 the result is stored back in register ’R’.
If the result is 0, the next instruction, which is already fetched, is discarded and a NOP is
executed instead and making it a 2-cycle instruction.
1/2 (3 cycles if skip and followed by a 2-word instruction FCALL/FGOTO)
Cycles:
DISI
Clear GIE bit
DISI
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
None
0 GIE
None
Disable interrupt
1
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 63 of 81, FM8PE68B
EELING
FM8PE68B
ENI
Set GIE bit
Syntax:
ENI
Operands:
Operation:
Status Affected:
Description:
Cycles:
None
1 GIE
None
Enable interrupt
1
FCALL
Subroutine Call
Syntax:
FCALL I
Operands:
Operation:
0x000≤I≤0xFFF
PC +1 Top of Stack;
I PC<11:0>
I<11:10> PG<1:0>
None
Status Affected:
Description:
Subroutine call. First, return address (PC+1) is pushed onto the stack. The 12-bit
immediate address is loaded into PC bits <11:0>. FCALL is a two-word (3-cycle) instruction.
3
Cycles:
FGOTO
Unconditional Branch
Syntax:
FGOTO
I
Operands:
Operation:
0x000≤I≤0xFFF
I PC<11:0>
I<11:10> PG<1:0>
Status Affected:
Description:
None
FGOTO is an unconditional branch. The 12-bit immediate value is loaded into PC bits
<11:0>. FGOTO is a two-word (3-cycle) instruction.
3
Cycles:
GOTO
Unconditional Branch
Syntax:
GOTO
I
Operands:
Operation:
0x000≤I≤0x3FF
I PC<9:0>
PG<1:0> PC<11:10>
Status Affected:
Description:
Cycles:
None
GOTO is an unconditional branch. The 10-bit immediate value is loaded into PC bits <9:0>.
2
INCR
Increment R
Syntax:
Operands:
INCR R, d
0x00≤R≤0x3F
d∈[0,1]
Operation:
R + 1 dest
Status Affected:
Description:
Z
The contents of register ‘R’ are increment. If ‘d’ is 0 the result is placed in the ACC register.
If ‘d’ is 1 the result is stored back in register ‘R’.
1
Cycles:
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 64 of 81, FM8PE68B
EELING
FM8PE68B
INCRSZ
Increment R, Skip if 0
Syntax:
INCRSZ R, d
Operands:
0x00≤R≤0x3F
d∈[0,1]
Operation:
R + 1 dest, skip if result = 0
Status Affected:
Description:
None
The contents of register ‘R’ are increment. If ‘d’ is 0 the result is placed in the ACC register.
If ‘d’ is the result is stored back in register ‘R’.
If the result is 0, then the next instruction, which is already fetched, is discarded and a NOP
is executed instead and making it a 2-cycle instruction.
Cycles:
1/2 (3 cycles if skip and followed by a 2-word instruction FCALL/FGOTO)
INT
S/W Interrupt
Syntax:
Operands:
Operation:
INT
None
PC + 1 Top of Stack,
0x002 PC
Status Affected:
Description:
None
Interrupt subroutine call. First, return address (PC+1) is pushed onto the stack. The
address 0x002 is loaded into PC bits <9:0>.
2
Cycles:
IORAR
OR ACC with R
Syntax:
IORAR R, d
Operands:
0x00≤R≤0x3F
d∈[0,1]
Operation:
ACC or R dest
Status Affected:
Description:
Z
Inclusive OR the ACC register with register ‘R’. If ‘d’ is 0 the result is placed in the ACC
register. If ‘d’ is 1 the result is placed back in register ‘R’.
1
Cycles:
IORIA
OR Immediate with ACC
Syntax:
IORIA I
Operands:
Operation:
Status Affected:
Description:
0x00≤I≤0x3F
ACC or I ACC
Z
The contents of the ACC register are OR’ed with the 8-bit immediate ‘I’. The result is placed
in the ACC register.
1
Cycles:
IOST
Load IOST Register
Syntax:
IOST R
Operands:
Operation:
Status Affected:
Description:
R = 0x05~0x0F or 0x15~0x1F
ACC IOST register R
None
IOST register ‘R’ (R= 0x05~0x0F or 0x15~0x1F) is loaded with the contents of the ACC
register.
1
Cycles:
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 65 of 81, FM8PE68B
EELING
FM8PE68B
IOSTR
Read IOST Register
Syntax:
IOST R
Operands:
Operation:
Status Affected:
Description:
Cycles:
R = 0x05~0x0F or 0x15~0x1F
IOST register R ACC
None
The ACC register is loaded with the contents of IOST register ‘R’ (0x05~0x0F or 0x15~0x1F).
1
MOVAR
Move ACC to R
Syntax:
MOVAR
R
Operands:
Operation:
Status Affected:
Description:
Cycles:
0x00≤R≤0x3F
ACC R
None
Move data from the ACC register to register ‘R’.
1
MOVIA
Move Immediate to ACC
Syntax:
MOVIA I
Operands:
Operation:
Status Affected:
Description:
Cycles:
0x00≤I≤0xFF
I ACC
None
The 8-bit immediate ‘I’ is loaded into the ACC register. The don’t cares will assemble as 0s.
1
MOVR
Move R
Syntax:
MOVR R, d
Operands:
0x00≤R≤0x3F
d∈[0,1]
Operation:
R dest
Status Affected:
Description:
Z
The contents of register ‘R’ is moved to destination ‘d’. If ‘d’ is 0, destination is the ACC
register. If ‘d’ is 1, the destination is file register ‘R’. ‘d’ is 1 is useful to test a file register
since status flag Z is affected.
1
Cycles:
NOP
No Operation
NOP
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
None
No operation
None
No operation.
1
PAGE
Move Immediate to program page bits
Syntax:
PAGE
I
Operands:
Operation:
Status Affected:
Description:
Cycles:
0x0≤I≤0x3
I PG<1:0>
None
The program page bits are loaded with the 2-bit immediate ‘I’.
1
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 66 of 81, FM8PE68B
EELING
FM8PE68B
RETFIE
Return from Interrupt, Set ‘GIE’ Bit
Syntax:
RETFIE
Operands:
Operation:
None
Top of Stack PC
1 GIE
Status Affected:
Description:
None
The program counter is loaded from the top of the stack (the return address). The ‘GIE’ bit
is set to 1. This is a 2-cycle instruction.
2
Cycles:
RETIA
Return with Immediate in ACC
Syntax:
RETIA I
Operands:
Operation:
0x00≤I≤0xFF
I ACC;
Top of Stack PC
Status Affected:
Description:
None
The ACC register is loaded with the 8-bit immediate ‘I’. The program counter is loaded from
the top of the stack (the return address). This is a 2-cycle instruction.
2
Cycles:
RETURN
Return from Subroutine
Syntax:
RETURN
Operands:
Operation:
Status Affected:
Description:
None
Top of Stack PC
None
The program counter is loaded from the top of the stack (the return address). This is a two-
cycle instruction.
2
Cycles:
RLR
Rotate Left R through Carry
Syntax:
Operands:
RLR R, d
0x00≤R≤0x3F
d∈[0,1]
Operation:
R<7> C;
R<6:0> dest<7:1>;
C dest<0>
Status Affected:
Description:
C
The contents of register ‘R’ are rotated left one bit to the left through the Carry Flag. If ‘d’ is
0 the result is placed in the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’.
1
Cycles:
RRR
Rotate Right R through Carry
Syntax:
Operands:
RRR R, d
0x00≤R≤0x3F
d∈[0,1]
Operation:
C dest<7>;
R<7:1> dest<6:0>;
R<0> C
Status Affected:
Description:
C
The contents of register ‘R’ are rotated one bit to the right through the Carry Flag. If ‘d’ is 0
the result is placed in the ACC register. If ‘d’ is 1 the result is placed back in register ‘R’.
1
Cycles:
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 67 of 81, FM8PE68B
EELING
FM8PE68B
SLEEP
Enter SLEEP Mode
Syntax:
SLEEP
Operands:
Operation:
None
0x00 WDT;
0x00 WDT pre-scaler;
̅̅̅̅
1 TO;
̅̅̅̅
0 PD
̅̅̅̅ ̅̅̅̅
Status Affected:
Description:
TO, PD
̅̅̅̅
̅̅̅̅
Time-out status bit (TO) is set. The power-down status bit (PD) is cleared. The WDT and its
pre-scaler cleared.
The processor is put into SLEEP mode.
1
Cycles:
SBCAR
Syntax:
Subtract ACC from R with Carry
SBCAR R, d
Operands:
0x00≤R≤0x3F
d∈[0,1]
̅̅̅̅̅̅̅
Operation:
R + ACC + C dest
Status Affected:
Description:
C, DC, Z
Add the 2’s complement data of the ACC register from register ‘R’ with Carry. If ‘d’ is 0 the
result is stored in the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’.
1
Cycles:
SUBAR
Syntax:
Subtract ACC from R
SUBAR R, d
Operands:
0x00≤R≤0x3F
d∈[0,1]
Operation:
R - ACC dest
Status Affected:
Description:
C, DC, Z
Subtract (2’s complement method) the ACC register from register ‘R’. If ‘d’ is 0 the result is
stored in the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’.
1
Cycles:
SUBIA
Subtract ACC from Immediate
Syntax:
SUBIA I
Operands:
Operation:
Status Affected:
Description:
0x00≤I≤0xFF
I - ACC ACC
C, DC, Z
Subtract (2’s complement method) the ACC register from the 8-bit immediate ‘I’. The result
is placed in the ACC register.
1
Cycles:
SWAPR
Syntax:
Swap nibbles in R
SWAPR R, d
Operands:
0x00≤R≤0x3F
d∈[0,1]
Operation:
R<3:0> dest<7:4>;
R<7:4> dest<3:0>
Status Affected:
Description:
None
The upper and lower nibbles of register ‘R’ are exchanged. If ‘d’ is 0 the result is placed in
ACC register. If ‘d’ is 1 the result in placed in register ‘R’.
1
Cycles:
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 68 of 81, FM8PE68B
EELING
FM8PE68B
TBL
Table Look-up
Syntax:
TBL
Operands:
Operation:
None
PC<7:0> + ACC PC<7:0>
PC<9:8> unchanged
PG<1:0> PC<11:10>
C, DC, Z
Operate with RETIA to look-up table
1
Status Affected:
Description:
Cycles:
XORAR
Syntax:
Operands:
Exclusive OR ACC with R
XORAR R, d
0x00≤R≤0x3F
d∈[0,1]
Operation:
Status Affected:
Description:
ACC xor R dest
Z
Exclusive OR the contents of the ACC register with register ’R’. If ‘d’ is 0 the result is stored
in the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’.
1
Cycles:
XORIA
Exclusive OR Immediate with ACC
Syntax:
XORIA I
Operands:
Operation:
Status Affected:
Description:
0x00≤I≤0xFF
ACC xor I ACC
Z
The contents of the ACC register are XOR’ed with the 8-bit immediate ‘I’. The result is placed
in the ACC register.
1
Cycles:
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 69 of 81, FM8PE68B
EELING
FM8PE68B
4.0 ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Conditions
-
Min.
0
Typ.
-
Max.
70
Unit
°C
Ambient Operating
Temperature
Store Temperature
DC Supply Voltage
Input Voltage with respect to
Ground
-
-
-65
0
-
-
150
6
°C
V
VDD
-
-0.3
-
VDD+0.3
V
HBM (Human Body Mode)
MM (Machine Mode)
Soldering, 10 Sec
-
-
-
2
200
-
-
-
KV
V
ESD Susceptibility
Lead Temperature
250
°C
This table need update
4.1 PACKAGE IR Re-flow Soldering Curve
250 5ꢁ
10 1 sec
150 10ꢁ
90 30 sec
2 ~ 5ꢁ/ sec
2 ~ 5ꢁ/ sec
Time
5.0 RECOMMENDED OPERATING CONDITIONS
Symbol
VDD
Parameter
DC Supply Voltage
Operating Temperature
Conditions
Min.
2.3
0
Typ.
Max.
5.5
Unit
V
-
-
-
-
70
°C
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 70 of 81, FM8PE68B
EELING
FM8PE68B
6.0 ELECTRICAL CHARACTERISTICS
6.1 AC Characteristics
Ta=25°C
Test Conditions
Conditions
Symbol
Description
Min.
Typ.
Max.
Unit
MHZ
MHZ
KHZ
MHZ
KHZ
KHZ
VDD
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
DC
DC
0.4
0.4
32
32
0.5
0.5
DC
DC
32
32
-
-
8
16
8
FM ERIC Main ERIC Oscillation range
ERIC mode
XT mode
-
-
FM XT
FM LF
Main X’tal Oscillation range
-
16
455
455
8
-
Main X’tal Oscillation range
LF mode
-
-
FM PLL Main PLL Oscillation range
FS ERIC Sub ERIC Oscillation range
PLL mode, FS=32KHZ
ERIC mode
LF mode
-
8
-
455
455
32
455
-
-
-
FS LF
Sub X’tal Oscillation range
-
20
16.7
14.8
TWDT
WDT period time
4V Pre-scaler rate=1:1
5V
-
-
mS
-
-
Note: 1. In the PLL mode, to maintain the accuracy of the internal PLL oscillator frequency, a 300pF ~ 0.01μF
decoupling capacitor should be connected between OSCI and VSS and located as close to the device
as possible.
2. At any time, a 0.1μF decoupling capacitor should be connected between VDD and VSS and device as
close as possible.
6.2 DC Characteristics
Ta=25°C
Under Operating Conditions, at two clock instruction cycles and WDT & LVDT are disable, I/O output float, no LCD
load.
Test Conditions
Symbol
VIH1
VIH2
VIL1
Description
Min.
Typ.
Max.
Unit
VDD
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
Conditions
-
2.1
-
1.36
-
VDD
Input high voltage with
Schmitt-trigger, I/O Ports
Input high voltage with
Schmitt-trigger, RSTB Pin
Input high voltage without
Schmitt-trigger, I/O Ports
Input low voltage with
-
VDD
V
1.73
-
VDD
-
-
-
-
-
3.5
-
VDD
1.13
1.6
0.99
VDD
V
-
VDD
VSS
VSS
VSS
VSS
VSS
VSS
-
-
Schmitt-trigger, I/O Ports
Input low voltage with
0.9
V
1.21
1.35
1.06
1.48
1.44
3.69
2.9
-
-
-
-
-
-
-
-
-
-
Schmitt-trigger, RSTB Pin
Input low voltage without
Schmitt-trigger, I/O Ports
I/O Ports Drive current, I/O
Ports, IOA7 Pin (IRSC=0)
VIL2
V
VOH=0.9VDD
1.0
-
IOH
mA
mA
Only IOA7 Pin (IRSC=1)
VOH=0.9VDD
VOL=0.1VDD
-
7.6
-
7.7
I/O Ports Sink current, I/O
Ports, IOA7 Pin (IRSC=0)
IOL
15
18.1
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 71 of 81, FM8PE68B
EELING
Description
Only IOA7 Pin (IRSC=1)
Pull-high current
FM8PE68B
Test Conditions
Conditions
Symbol
IOL
Min.
Typ.
Max.
Unit
mA
uA
VDD
3V
5V
3V
5V
3V
5V
-
-
14.4
32.4
22
-
VOL=0.1VDD
-
-
-
-
IPH
Input pin at VSS
Input pin at VDD
65
80
95
-
21.5
70
-
IPL
Pull-low current
uA
55
85
LVDT=2.4V
LVDT=2.2V
LVDT=2.0V
LVDT=1.8V
LVDT=2.4V
LVDT=2.2V
LVDT=2.0V
LVDT=1.8V
2.04
2.4
2.76
-
1.87
2.2
2.53
Low Voltage Detector
Voltage
-
1.7
2.0
2.3
-
1.6
1.8
2.07
VLVDT
V
-
1.87
2.2
2.53
-
1.7
2.0
2.3
Low Voltage Reset Voltage
-
1.6
1.8
2.07
-
1.6
-
1.7
1.84
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
0.13
0.38
0.13
0.42
0.14
0.37
0.12
0.38
0.6
-
-
-
-
-
-
-
-
-
-
-
1
-
-
-
-
LVDT=2.4V
LVDT=2.2V
LVDT=2.0V
LVDT=1.8V
-
-
-
ILVDT
LVDT current
WDT current
uA
-
-
-
-
-
Sleep mode, Pre-scaler
rate=1:256
IWDT
ISB
IDD1
IDD2
uA
uA
uA
uA
-
3.7
-
<1
Sleep mode (Power down)
current
-
-
<1
-
5.8
FS=32KHZ
LCD=Enable
FS=32KHZ
,
IDLE mode current
Green mode current
-
15.8
90.4
240.1
-
,
LCD=Enable
-
FS=32KHZ, FM=8MHZ,
LCD=Enable
3V
5V
-
-
2.2
7.6
-
-
IDD3
Normal mode current
mA
FS=32KHZ, FM=16MHZ,
LCD=Enable
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 72 of 81, FM8PE68B
EELING
FM8PE68B
6.3 ELECTRICAL CHARACTERISTICS Charts of FM8PE68B
6.3.1
6.3.2
6.3.3
WDT 18mS Reset time vs. Temperature
30.00
25.00
20.00
15.00
10.00
5.00
Avg-5V
Avg-3V
0.00
-10
0
10
20
25
30
40
50
60
70
80
Temperature
Note: Curves are for design reference only.
WDT 18mS Reset time vs. Supply Voltage (Ta=25℃)
35.00
30.00
25.00
20.00
15.00
10.00
5.00
Avg-18mS
0.00
1.8
2
2.2 2.4 2.6 2.8
3
3.2 3.4 3.6 3.8
Voltage
4
4.2 4.4 4.6 4.8
5
5.2 5.4 5.6 5.8
6
Note: Curves are for design reference only.
LVDT 2.4V vs. Temperature
3.00
2.50
2.00
1.50
1.00
0.50
0.00
Avg-2.4V
-10
0
10
20
25
30
40
50
60
70
80
Temperature
Note: Curves are for design reference only.
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 73 of 81, FM8PE68B
EELING
FM8PE68B
6.3.4
6.3.5
6.3.6
LVDT 2.2V vs. Temperature
2.50
2.00
1.50
1.00
0.50
0.00
Avg-2.2V
-10
0
10
20
25
30
40
40
40
50
50
50
60
60
60
70
70
70
80
Temperature
Note: Curves are for design reference only.
LVDT 2.0V vs. Temperature
2.50
2.00
1.50
1.00
0.50
0.00
Avg-2.0V
-10
0
10
20
25
30
80
Temperature
Note: Curves are for design reference only.
LVDT 1.8V vs. Temperature
2.50
2.00
1.50
1.00
0.50
0.00
Avg-1.8V
-10
0
10
20
25
30
80
Temperature
Note: Curves are for design reference only.
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 74 of 81, FM8PE68B
EELING
FM8PE68B
7.0 PACKAGE DIMENSION
7.1 64-PIN QFp(14x20)
Dimension In MM
Nom
Symbols
Min
Max
A
A1
A2
b
-
-
3.40
-
0.25
2.55
0.35
0.11
-
2.72
3.05
0.50
0.23
0.40
c
0.15
D
25.00 BASIC
20.00 BASIC
1.00 BASIC
19.00 BASIC
14.00 BASIC
1.30
D1
e
E
E1
L
1.15
0o
1.45
7o
L1
θo
2.50 REF
3.5o
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 75 of 81, FM8PE68B
EELING
FM8PE68B
7.2 64-PIN QFP(14x14)
Dimension In MM
Symbols
Min
-
Nom
Max
2.45
0.25
2.2
A
A1
A2
b
-
0.05
1.8
0.3
0.11
-
-
-
0.45
0.23
c
-
D
14.00 BASIC
17.00 BASIC
0.800 BASIC
14.00 BASIC
17.00 BASIC
-
D1
e
E
E1
L
θo
0.73
0o
1.03
7o
-
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 76 of 81, FM8PE68B
EELING
FM8PE68B
7.3 64-PIN QFP(7x7)
Dimension In MM
Symbols
Min
-
Nom
-
Max
1.6
A
A1
A2
b
0.05
1.35
0.13
0.09
-
0.15
1.45
0.23
0.20
1.40
0.18
c
-
D
9.00 BASIC
7.00 BASIC
0.40 BASIC
9.00 BASIC
7.00 BASIC
0.60
D1
e
E
E1
L
0.45
0o
0.75
7o
L1
θo
1.00 REF
3.5o
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 77 of 81, FM8PE68B
EELING
FM8PE68B
7.4 64-PIN QFP(10x10)
Dimension In MM
Symbols
Min
-
Nom
Max
1.6
A
A1
A2
b
-
0.05
1.35
0.17
0.09
-
0.15
1.45
0.27
0.16
1.40
0.18
c1
D
-
12.00 BASIC
10.00 BASIC
0.50 BASIC
12.00 BASIC
10.00 BASIC
-
D1
e
E
E1
L
0.45
0.75
L1
1.00 REF
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 78 of 81, FM8PE68B
EELING
FM8PE68B
7.5 44-PIN QFP(10x10)
D
“
A
D1
44
34
33
1
11
23
0.20MIN
0'MIN
H
GAGE PLANE
SEATING PLANE
o
£
b
e
0.10
L
1.6
Dimension In Millimeters
Symbols
Min
Nom
-
Max
2.7
A
A1
A2
b
-
0.25
1.9
-
0.50
2.2
2.0
0.3 (TYP)
13.20
10.00
13.20
10.00
0.88
D
13.00
9.9
13.40
10.10
13.40
10.10
0.93
D1
E
13.00
9.9
E1
L
0.73
e
θo
0.80 (TYP)
-
0o
7o
C
0.1
0.15
0.2
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 79 of 81, FM8PE68B
EELING
FM8PE68B
7.6 44-PIN LQFP(10x10)
Dimension In Millimeters
Symbols
Min
-
Nom
-
Max
1.60
0.15
1.45
0.16
A
A1
A2
c1
D
0.05
1.35
0.09
-
1.40
-
12.00 BSC
10.00 BSC
12.00 BSC
10.00 BSC
0.80 BSC
0.37
D1
E
E1
e
b
0.30
0.45
0.45
0.75
L
0.60
L1
θo
1.00 REF
3.5o
0o
7o
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 80 of 81, FM8PE68B
EELING
FM8PE68B
8.0 ORDERING INFORMATION
OTP Type MCU
FM8PE68BAF
FM8PE68BAG
FM8PE68BBG
FM8PE68BCF
FM8PE68BCG
Package Type
QFP
Pin Count
Package Size
SAMPLE Stock
Available
No stock
64
64
64
44
44
14mm x 20mm
10mm x 10mm
7mm x 7mm
LQFP
LQFP
No stock
QFP
10mm x 10mm
10mm x 10mm
No stock
LQFP
No stock
Web site: http://www.feeling-teccom.tw
Rev 1.00.012 Feb 17, 2016
Page 81 of 81, FM8PE68B
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明