FT29F040B-150EK [FORCE]

4 Megabit (512 K x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory;


型号：	FT29F040B-150EK
厂家：	Force Technologies
描述：	4 Megabit (512 K x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory
文件：	总36页 (文件大小：3898K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FT29F040B

4 Megabit (512 K x 8-Bit)

CMOS 5.0 Volt-only, Uniform Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

■ 5.0 V ± 10% for read and write operations

— Minimises system level power requirements

■ Embedded Algorithms

— Embedded Erase algorithm automatically

preprograms and erases the entire chip or any

combination of designated sectors

■ Manufactured on 0.32 µm process technology

— Compatible with 0.5 µm FT29F040 device

— Embedded Program algorithm automatically

writes and verifies bytes at specified addresses

■ High performance

— Access times as fast as 55 ns

■ Minimum 1,000,000 program/erase cycles per

sector guaranteed

■ Low power consumption

■ 20-year data retention at 125°C

— Reliable operation for the life of the system

■ Package options

— 20 mA typical active read current

— 30 mA typical program/erase current

— 1 µA typical standby current (standard access

time to active mode)

— 32-pin PLCC, TSOP, or PDIP

■ Flexible sector architecture

— 8 uniform sectors of 64 Kbytes each

— Any combination of sectors can be erased

— Supports full chip erase

■ Compatible with JEDEC standards

— Pinout and software compatible with

single-power-supply Flash standard

— Superior inadvertent write protection

— Sector protection:

■ Data# Polling and toggle bits

A hardware method of locking sectors to prevent

any program or erase operations within that sector

— Provides a software method of detecting

program or erase cycle completion

■ Erase Suspend/Erase Resume

— Suspends a sector erase operation to read data

from, or program data to, a non-erasing sector,

then resumes the erase operation

Rev 2

Page 1 of 36

FT29F040B

GENERAL DESCRIPTION

The FT29F040B is a 4 Mbit, 5.0 volt-only Flash mem-

ory organised as 524,288 Kbytes of 8 bits each. The

512 Kbytes of data are divided into eight sectors of 64

Kbytes each for flexible erase capability. The 8 bits of

data appear on DQ0–DQ7. The FT29F040B is offered

in 32-pin PLCC, TSOP, and PDIP packages. This device

is designed to be programmed in-system with the stan-

matically times the program pulse widths and verifies

proper cell margin.

Device erasure occurs by executing the erase com-

mand sequence. This initiates the Embedded Erase

algorithm—an internal algorithm that automatically

preprograms the array (if it is not already programmed)

before executing the erase operation. During erase, the

device automatically times the erase pulse widths and

verifies proper cell margin.

dard system 5.0 volt V supply. A 12.0 volt V is not

required for write or erase operations. The device can

also be programmed in standard EPROM programmers.

The host system can detect whether a program or

erase operation is complete by reading the DQ7 (Data#

Polling) and DQ6 (toggle) status bits. After a program

or erase cycle has been completed, the device is ready

to read array data or accept another command.

This device is manufactured using 0.32 µm pro-

cess technology, and offers all the features and

benefits of the FT29F040, which was manufactured

using 0.5 µm process technology. In addtion, the

FT29F040B has a second toggle bit, DQ2, and also of-

fers the ability to program in the Erase Suspend mode.

The sector erase architecture allows memory sectors

to be erased and reprogrammed without affecting the

data contents of other sectors. The device is fully

erased when shipped from the factory.

The standard FT29F040B offers access times of 55,

70, 90, 120, and 150 ns, allowing high-speed micropro-

cessors to operate without wait states. To eliminate bus

contention the device has separate chip enable (CE#),

write enable (WE#) and output enable (OE#) controls.

Hardware data protection measures include a low

detector that automatically inhibits write opera-

tions during power transitions. The hardware sector

protection feature disables both program and erase

operations in any combination of the sectors of mem-

ory. This can be achieved via programming equipment.

The device requires only a single 5.0 volt power sup-

ply for both read and write functions. Internally

generated and regulated voltages are provided for the

program and erase operations.

The Erase Suspend feature enables the user to put

erase on hold for any period of time to read data from,

or program data to, any sector that is not selected for

erasure. True background erase can thus be achieved.

The device is entirely command set compatible with the

JEDEC single-power-supply Flash standard. Com-

mands are written to the command register using

standard microprocessor write timings. Register con-

tents serve as input to an internal state-machine that

controls the erase and programming circuitry. Write cy-

cles also internally latch addresses and data needed

for the programming and erase operations. Reading

data out of the device is similar to reading from other

Flash or EPROM devices.

The system can place the device into the standby mode.

Power consumption is greatly reduced in this mode.

Our Flash technology combines years of Flash

memory manufacturing experience to produce the

highest levels of quality, reliability and cost effective-

ness. The device electrically erases all bits within a

sector simultaneously via Fowler-Nordheim tunneling.

The data is programmed using hot electron injection.

Device programming occurs by executing the program

command sequence. This initiates the Embedded

Program algorithm—an internal algorithm that auto-

Rev 2

Page 2 of 36

FT29F040B

PRODUCT SELECTOR GUIDE

Family Part Number

FT29F040B

= 5.0 V ± 5%

= 5.0 V ± 10%

-55

N/A

-70

N/A

-90

N/A

-120

120

N/A

-150

150

Speed Option

Max access time, ns (t

)

ACC

Max CE# access time, ns (t

)

Max OE# access time, ns (t

)

Note: See the “AC Characteristics” section for more information.

BLOCK DIAGRAM

DQ0–DQ7

Input/Output

Buffers

Erase Voltage

Generator

State

Control

WE#

Command

PGM Voltage

Generator

Chip Enable

Output Enable

Logic

Data Latch

STB

CE#

OE#

Y-Decoder

Y-Gating

STB

Detector

Timer

X-Decoder

Cell Matrix

A0–A18

Rev 2

Page 3 of 36

FT29F040B

CONNECTION DIAGRAMS

A18

A16

A15

A12

31 WE#

30 A17

29 A14

28 A13

27 A8

1 32 31 30

A14

A13

26 A9

25 A11

24 OE#

23 A10

22 CE#

21 DQ7

20 DQ6

19 DQ5

18 DQ4

17 DQ3

PDIP

A11

OE#

A10

CE#

DQ7

PLCC

A2 10

A1 11

A0 12

DQ0

DQ0 13

DQ1 14

DQ2 15

14 15 16 17 18 19 20

A11

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

V_SS

DQ2

DQ1

DQ0

A13

A14

A17

WE#

V_CC

A18

A16

A15

A12

32-Pin Standard TSOP

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

V_SS

DQ2

DQ1

DQ0

A11

A13

A14

A17

WE#

V_CC

A18

A16

A15

A12

32-Pin Reverse TSOP

Rev 2

Page 4 of 36

FT29F040B

PIN CONFIGURATION

LOGIC SYMBOL

A0–A18

Address Inputs

DQ0–DQ7 = Data Input/Output

CE#

WE#

OE#

Chip Enable

A0–A18

Write Enable

Output Enable

Device Ground

DQ0–DQ7

CE#

OE#

+5.0 V single power supply

(see Product Selector Guide for

device speed ratings and voltage

supply tolerances)

WE#

Rev 2

Page 5 of 36

FT29F040B

ORDERING INFORMATION

FT29F040B

-XX

TEMPERATURE RANGE

Commercial (0°C to +70°C)

Industrial (–40°C to +85°C)

Extended (–55°C to +125°C)

Commercial (0°C to +70°C) for Pb-free Package

Industrial (-40°C to +85°C) for Pb-free Package

Extended (-55°C to +125°C) for Pb-free Package

PACKAGE TYPE

32-Pin Plastic DIP (FTP 032)

32-Pin Rectangular Plastic Leaded Chip Carrier (FTJ 032)

32-Pin Thin Small Outline Package (TSOP) Standard Pinout (FTE 032)

32-Pin Thin Small Outline Package (TSOP) Reverse Pinout (FTF032)

32 Lead Cerquad "K" (CQ032)

SPEED OPTION

See Product Selector Guide and Valid Combinations

DEVICE NUMBER/DESCRIPTION

FT29F040B

4 Megabit (512 K x 8-Bit) CMOS 5.0 Volt-only Sector Erase Flash Memory

5.0 V Read, Program, and Erase

Valid Combinations

Voltage

FT29F040B-55

JC, JI, JE, JD, JF, JK

EC, ED, EI, EE, EF

FC, FI, FE, EK

5.0 V ± 5%

FT29F040B-70

FT29F040B-90

FT29F040B-120

FT29F040B-150

PC, PI, PE, PD, PF, PK,

JC, JI, JE, JD, JF, JK

EC, EI, EE, ED, EF, EK

FC, FI, FE

5.0 V ± 10%

Rev 2

Page 6 of 36

FT29F040B

mation needed to execute the command. The contents

of the register serve as inputs to the internal state ma-

chine. The state machine outputs dictate the function of

the device. The appropriate device bus operations

table lists the inputs and control levels required, and the

resulting output. The following subsections describe

each of these operations in further detail.

DEVICE BUS OPERATIONS

This section describes the requirements and use of the

device bus operations, which are initiated through the

internal command register. The command register it-

self does not occupy any addressable memory

location. The register is composed of latches that store

the commands, along with the address and data infor-

Table 1. FT29F040B Device Bus Operations

CE# OE# WE#

Operation

A0–A20

DQ0–DQ7

Read

OUT

Write

CMOS Standby

TTL Standby

Output Disable

± 0.5 V

High-Z

Legend:

L = Logic Low = V , H = Logic High = V , V = 12.0 ± 0.5 V, X = Don’t Care, D = Data In, D

= Data Out, A = Address In

OUT

Note: See the “Sector Protection/Unprotection” section. for more information.

indicate the address space that each sector occupies.

A “sector address” consists of the address bits required

to uniquely select a sector. See the “Command Defini-

tions” section for details on erasing a sector or the

entire chip, or suspending/resuming the erase

operation.

Requirements for Reading Array Data

To read array data from the outputs, the system must

drive the CE# and OE# pins to V . CE# is the power

control and selects the device. OE# is the output con-

trol and gates array data to the output pins. WE# should

remain at V .

After the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autoselect codes from the inter-

nal register (which is separate from the memory array)

on DQ7–DQ0. Standard read cycle timings apply in this

mode. Refer to the “Autoselect Mode” and “Autoselect

Command Sequence” sections for more information.

The internal state machine is set for reading array data

upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory con-

tent occurs during the power transition. No command is

necessary in this mode to obtain array data. Standard

microprocessor read cycles that assert valid addresses

on the device address inputs produce valid data on the

device data outputs. The device remains enabled for

read access until the command register contents are

altered.

in the DC Characteristics table represents the ac-

CC2

tive current specification for the write mode. The “AC

Characteristics” section contains timing specification

tables and timing diagrams for write operations.

See “Reading Array Data” for more information. Refer

to the AC Read Operations table for timing specifica-

tions and to the Read Operations Timings diagram for

Program and Erase Operation Status

During an erase or program operation, the system may

check the status of the operation by reading the status

the timing waveforms. I

table represents the active current specification for

reading array data.

in the DC Characteristics

CC1

bits on DQ7–DQ0. Standard read cycle timings and I

read specifications apply. Refer to “Write Operation

Status” for more information, and to each AC Charac-

teristics section for timing diagrams.

Writing Commands/Command Sequences

To write a command or command sequence (which in-

cludes programming data to the device and erasing

sectors of memory), the system must drive WE# and

Standby Mode

When the system is not reading or writing to the device,

it can place the device in the standby mode. In this

mode, current consumption is greatly reduced, and the

CE# to V , and OE# to V .

An erase operation can erase one sector, multiple sec-

tors, or the entire device. The Sector Address Tables

Rev 2

Page 7 of 36

FT29F040B

outputs are placed in the high impedance state, inde-

pendent of the OE# input.

If the device is deselected during erasure or program-

ming, the device draws active current until the

operation is completed.

The device enters the CMOS standby mode when the

CE# pin is held at V ± 0.5 V. (Note that this is a more

in the DC Characteristics tables represents the

CC3

restricted voltage range than V .) The device enters

standby current specification.

the TTL standby mode when CE# is held at V . The

Output Disable Mode

device requires the standard access time (t ) before it

is ready to read data.

When the OE# input is at V , output from the device is

disabled. The output pins are placed in the high imped-

ance state.

Table 2. Sector Addresses Table

A17 A16

Sector

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

A18

Address Range

00000h–0FFFFh

10000h–1FFFFh

20000h–2FFFFh

30000h–3FFFFh

40000h–4FFFFh

50000h–5FFFFh

60000h–6FFFFh

70000h–7FFFFh

Note: All sectors are 64 Kbytes in size.

Rev 2

Page 8 of 36

FT29F040B

Autoselect Mode

The autoselect mode provides manufacturer and de-

vice identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This

mode is primarily intended for programming equipment

to automatically match a device to be programmed with

its corresponding programming algorithm. However,

the autoselect codes can also be accessed in-system

through the command register.

address must appear on the appropriate highest order

address bits. Refer to the corresponding Sector Ad-

dress Tables. The Command Definitions table shows

the remaining address bits that are don’t care. When all

necessary bits have been set as required, the program-

ming equipment may then read the corresponding

identifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host

system can issue the autoselect command via the

command register, as shown in the Command Defini-

When using programming equipment, the autoselect

mode requires V (11.5 V to 12.5 V) on address pin

A9. Address pins A6, A1, and A0 must be as shown in

Autoselect Codes (High Voltage Method) table. In addi-

tion, when verifying sector protection, the sector

tions table. This method does not require V . See

“Command Definitions” for details on using the autose-

lect mode.

Table 3. FT29F040B Autoselect Codes (High Voltage Method)

Identifier Code on

DQ7-DQ0

Description

A18–A16 A15–A10 A9 A8–A7 A6 A5–A2 A1

Manufacturer ID: AMD

Device ID: Am29F040B

01h

A4h

01h (protected)

00h (unprotected)

Sector Protection

Verification

Sector

Address

gramming, which might otherwise be caused by

Sector Protection/Unprotection

spurious system level signals during V power-up and

The hardware sector protection feature disables both

program and erase operations in any sector. The hard-

ware sector unprotection feature re-enables both

program and erase operations in previously protected

sectors.

power-down transitions, or from system noise.

Low V

Write Inhibit

When V

is less than V

, the device does not ac-

LKO

cept any write cycles. This protects data during V

power-up and power-down. The command register and

all internal program/erase circuits are disabled, and the

Sector protection/unprotection must be implemented

using programming equipment. The procedure re-

device resets. Subsequent writes are ignored until V

quires a high voltage (V ) on address pin A9 and the

is greater than V

. The system must provide the

control pins. Details on this method are provided in a

supplement, publication number 19957. Contact an

representative to obtain a copy of the appropriate

document.

LKO

proper signals to the control pins to prevent uninten-

tional writes when V is greater than V

LKO

Write Pulse “Glitch” Protection

The device is shipped with all sectors unprotected.

Force offer the option of programming and protecting

sectors at its factory prior to shipping the device

Contact a Force representative for details.

Noise pulses of less than 5 ns (typical) on OE#, CE# or

WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =

It is possible to determine whether a sector is protected

or unprotected. See “Autoselect Mode” for details.

V , CE# = V or WE# = V . To initiate a write cycle,

CE# and WE# must be a logical zero while OE# is a

logical one.

Hardware Data Protection

Power-Up Write Inhibit

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadvertent writes (refer to the Command Defi-

nitions table). In addition, the following hardware data

protection measures prevent accidental erasure or pro-

If WE# = CE# = V and OE# = V during power up, the

IL IH

device does not accept commands on the rising edge

of WE#. The internal state machine is automatically

reset to reading array data on power-up.

Rev 2

Page 9 of 36

FT29F040B

COMMAND DEFINITIONS

Writing specific address and data commands or se-

quences into the command register initiates device

operations. The Command Definitions table defines the

valid register command sequences. Writing incorrect

address and data values or writing them in the im-

proper sequence resets the device to reading array

data.

however, the device ignores reset commands until the

operation is complete.

The reset command may be written between the se-

quence cycles in an autoselect command sequence.

Once in the autoselect mode, the reset command must

be written to return to reading array data (also applies

to autoselect during Erase Suspend).

All addresses are latched on the falling edge of WE# or

CE#, whichever happens later. All data is latched on

the rising edge of WE# or CE#, whichever happens

first. Refer to the appropriate timing diagrams in the

“AC Characteristics” section.

If DQ5 goes high during a program or erase operation,

writing the reset command returns the device to read-

ing array data (also applies during Erase Suspend).

Autoselect Command Sequence

The autoselect command sequence allows the host

system to access the manufacturer and devices codes,

and determine whether or not a sector is protected.

The Command Definitions table shows the address

and data requirements. This method is an alternative to

that shown in the Autoselect Codes (High Voltage

Method) table, which is intended for PROM program-

Reading Array Data

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data. The device is also ready to read array

data after completing an Embedded Program or Em-

bedded Erase algorithm.

After the device accepts an Erase Suspend command,

the device enters the Erase Suspend mode. The sys-

tem can read array data using the standard read

timings, except that if it reads at an address within

erase-suspended sectors, the device outputs status

data. After completing a programming operation in the

Erase Suspend mode, the system may once again

read array data with the same exception. See “Erase

Suspend/Erase Resume Commands” for more infor-

mation on this mode.

mers and requires V on address bit A9.

The autoselect command sequence is initiated by writ-

ing two unlock cycles, followed by the autoselect

command. The device then enters the autoselect

mode, and the system may read at any address any

number of times, without initiating another command

sequence.

A read cycle at address XX00h or retrieves the manu-

facturer code. A read cycle at address XX01h returns

the device code. A read cycle containing a sector ad-

dress (SA) and the address 02h in returns 01h if that

sector is protected, or 00h if it is unprotected. Refer to

the Sector Address tables for valid sector addresses.

The system must issue the reset command to re-en-

able the device for reading array data if DQ5 goes high,

or while in the autoselect mode. See the “Reset Com-

mand” section, next.

The system must write the reset command to exit the

autoselect mode and return to reading array data.

See also “Requirements for Reading Array Data” in the

“Device Bus Operations” section for more information.

The Read Operations table provides the read parame-

ters, and Read Operation Timings diagram shows the

timing diagram.

Byte Program Command Sequence

Programming is a four-bus-cycle operation. The pro-

gram command sequence is initiated by writing two

unlock write cycles, followed by the program set-up

command. The program address and data are written

next, which in turn initiate the Embedded Program al-

gorithm. The system is not required to provide further

controls or timings. The device automatically provides

internally generated program pulses and verify the pro-

grammed cell margin. The Command Definitions take

shows the address and data requirements for the byte

program command sequence.

Reset Command

Writing the reset command to the device resets the de-

vice to reading array data. Address bits are don’t care

for this command.

The reset command may be written between the se-

quence cycles in an erase command sequence before

erasing begins. This resets the device to reading array

data. Once erasure begins, however, the device ig-

nores reset commands until the operation is complete.

When the Embedded Program algorithm is complete,

the device then returns to reading array data and ad-

dresses are no longer latched. The system can

determine the status of the program operation by using

DQ7 or DQ6. See “Write Operation Status” for informa-

tion on these status bits.

The reset command may be written between the se-

quence cycles in a program command sequence

before programming begins. This resets the device to

reading array data (also applies to programming in

Erase Suspend mode). Once programming begins,

Rev 2

Page 10 of 36

FT29F040B

Table 4.

Command Definitions

Bus Cycles (Notes 2– 4)

Third Fourth

Addr Data Addr Data Addr Data Addr Data

Command

Sequence

(Note 1)

First

Second

Fifth

Sixth

Addr Data Addr Data

Read (Note 5)

XXX

555

Reset (Note 6)

Manufacturer ID

Device ID

2AA

555

X00

X01

Autoselect

(Note 7)

Sector Protect Verify

(Note 8)

X02

555

2AA

555

Program

555

2AA

555

Chip Erase

Sector Erase

2AA

555

Erase Suspend (Note 9)

Erase Resume (Note 10)

XXX

Legend:

X = Don’t care

PD = Data to be programmed at location PA. Data latches on the

rising edge of WE# or CE# pulse, whichever happens first.

RA = Address of the memory location to be read.

SA = Address of the sector to be verified (in autoselect mode) or

erased. Address bits A18–A16 select a unique sector.

RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed.

Addresses latch on the falling edge of the WE# or CE# pulse,

whichever happens later.

Notes:

1. See Table 1 for description of bus operations.

7. The fourth cycle of the autoselect command sequence is a

read cycle.

2. All values are in hexadecimal.

8. The data is 00h for an unprotected sector and 01h for a

protected sector.See “Autoselect Command Sequence” for

more information.

3. Except when reading array or autoselect data, all bus cycles

are write operations.

4. Address bits A18–A11 are don’t cares for unlock and

command cycles, unless SA or PA required.

9. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend

mode. The Erase Suspend command is valid only during a

sector erase operation.

5. No unlock or command cycles required when reading array data.

6. The Reset command is required to return to reading array

data when device is in the autoselect mode, or if DQ5 goes

high (while the device is providing status data).

10. The Erase Resume command is valid only during the Erase

Suspend mode.

Rev 2

Page 11 of 36

FT29F040B

Any commands written to the device during the Em-

bedded Program Algorithm are ignored.

rithm automatically preprograms and verifies the entire

memory for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings during these operations. The Command

Definitions table shows the address and data require-

ments for the chip erase command sequence.

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed

from a “0” back to a “1”. Attempting to do so may halt

the operation and set DQ5 to “1”, or cause the Data#

Polling algorithm to indicate the operation was suc-

cessful. However, a succeeding read shows that the

data is still “0”. Only erase operations can convert a “0”

to a “1”.

Any commands written to the chip during the Embed-

ded Erase algorithm are ignored.

The system can determine the status of the erase op-

eration by using DQ7, DQ6, or DQ2. See “Write

Operation Status” for information on these status bits.

When the Embedded Erase algorithm is complete, the

device returns to reading array data and addresses are

no longer latched.

START

Figure 2 illustrates the algorithm for the erase opera-

tion. See the Erase and Program Operations tables in

“AC Characteristics” for parameters, and to the Chip/

Sector Erase Operation Timings for timing waveforms.

Write Program

Command Sequence

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two un-

lock cycles, followed by a set-up command. Two

additional unlock write cycles are then followed by the

address of the sector to be erased, and the sector

erase command. The Command Definitions table

shows the address and data requirements for the sec-

tor erase command sequence.

Data Poll

from System

Embedded

Program

algorithm

in progress

Verify Data?

The device does not require the system to preprogram

the memory prior to erase. The Embedded Erase algo-

rithm automatically programs and verifies the sector for

an all zero data pattern prior to electrical erase. The

system is not required to provide any controls or tim-

ings during these operations.

Yes

Increment Address

Last Address?

Yes

After the command sequence is written, a sector erase

time-out of 50 µs begins. During the time-out period,

additional sector addresses and sector erase com-

mands may be written. Loading the sector erase buffer

may be done in any sequence, and the number of sec-

tors may be from one sector to all sectors. The time

between these additional cycles must be less than 50

µs, otherwise the last address and command might not

be accepted, and erasure may begin. It is recom-

mended that processor interrupts be disabled during

this time to ensure all commands are accepted. The in-

terrupts can be re-enabled after the last Sector Erase

command is written. If the time between additional sec-

tor erase commands can be assumed to be less than

50 µs, the system need not monitor DQ3. Any com-

mand other than Sector Erase or Erase Suspend

during the time-out period resets the device to

reading array data. The system must rewrite the com-

mand sequence and any additional sector addresses

and commands.

Programming

Completed

Note: See the appropriate Command Definitions table for

program command sequence.

Figure 1. Program Operation

Chip Erase Command Sequence

Chip erase is a six-bus-cycle operation. The chip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional

unlock write cycles are then followed by the chip erase

command, which in turn invokes the Embedded Erase

algorithm. The device does not require the system to

preprogram prior to erase. The Embedded Erase algo-

Rev 2

Page 12 of 36

FT29F040B

The system can monitor DQ3 to determine if the sector

erase timer has timed out. (See the “DQ3: Sector Erase

Timer” section.) The time-out begins from the rising

edge of the final WE# pulse in the command sequence.

non-suspended sectors. The system can determine

the status of the program operation using the DQ7 or

DQ6 status bits, just as in the standard program oper-

ation. See “Write Operation Status” for more

information.

Once the sector erase operation has begun, only the

Erase Suspend command is valid. All other commands

are ignored.

The system may also write the autoselect command

sequence when the device is in the Erase Suspend

mode. The device allows reading autoselect codes

even at addresses within erasing sectors, since the

codes are not stored in the memory array. When the

device exits the autoselect mode, the device reverts to

the Erase Suspend mode, and is ready for another

valid operation. See “Autoselect Command Sequence”

for more information.

When the Embedded Erase algorithm is complete, the

device returns to reading array data and addresses are

no longer latched. The system can determine the sta-

tus of the erase operation by using DQ7, DQ6, or DQ2.

Refer to “Write Operation Status” for information on

these status bits.

Figure 2 illustrates the algorithm for the erase opera-

tion. Refer to the Erase/Program Operations tables in

the “AC Characteristics” section for parameters, and to

the Sector Erase Operations Timing diagram for timing

waveforms.

The system must write the Erase Resume command

(address bits are “don’t care”) to exit the erase suspend

mode and continue the sector erase operation. Further

writes of the Resume command are ignored. Another

Erase Suspend command can be written after the de-

vice has resumed erasing.

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows the system to in-

terrupt a sector erase operation and then read data

from, or program data to, any sector not selected for

erasure. This command is valid only during the sector

erase operation, including the 50 µs time-out period

during the sector erase command sequence. The

Erase Suspend command is ignored if written during

the chip erase operation or Embedded Program algo-

rithm. Writing the Erase Suspend command during the

Sector Erase time-out immediately terminates the

time-out period and suspends the erase operation. Ad-

dresses are “don’t-cares” when writing the Erase

Suspend command.

START

Write Erase

Command Sequence

Data Poll

from System

Embedded

When the Erase Suspend command is written during a

sector erase operation, the device requires a maximum

of 20 µs to suspend the erase operation. However,

when the Erase Suspend command is written during

the sector erase time-out, the device immediately ter-

minates the time-out period and suspends the erase

operation.

Erase

algorithm

in progress

Data = FFh?

Yes

After the erase operation has been suspended, the

system can read array data from or program data to

any sector not selected for erasure. (The device “erase

suspends” all sectors selected for erasure.) Normal

read and write timings and command definitions apply.

Reading at any address within erase-suspended sec-

tors produces status data on DQ7–DQ0. The system

can use DQ7, or DQ6 and DQ2 together, to determine

if a sector is actively erasing or is erase-suspended.

See “Write Operation Status” for information on these

status bits.

Erasure Completed

Notes:

1. See the appropriate Command Definitions table for erase

command sequence.

2. See “DQ3: Sector Erase Timer” for more information.

After an erase-suspended program operation is com-

plete, the system can once again read array data within

Figure 2. Erase Operation

Rev 2

Page 13 of 36

FT29F040B

COMMAND DEFINITIONS

Writing specific address and data commands or se-

quences into the command register initiates device

operations. The Command Definitions table defines the

valid register command sequences. Writing incorrect

address and data values or writing them in the im-

proper sequence resets the device to reading array

data.

however, the device ignores reset commands until the

operation is complete.

The reset command may be written between the se-

quence cycles in an autoselect command sequence.

Once in the autoselect mode, the reset command must

be written to return to reading array data (also applies

to autoselect during Erase Suspend).

All addresses are latched on the falling edge of WE# or

CE#, whichever happens later. All data is latched on

the rising edge of WE# or CE#, whichever happens

first. Refer to the appropriate timing diagrams in the

“AC Characteristics” section.

If DQ5 goes high during a program or erase operation,

writing the reset command returns the device to read-

ing array data (also applies during Erase Suspend).

Autoselect Command Sequence

The autoselect command sequence allows the host

system to access the manufacturer and devices codes,

and determine whether or not a sector is protected.

The Command Definitions table shows the address

and data requirements. This method is an alternative to

that shown in the Autoselect Codes (High Voltage

Method) table, which is intended for PROM program-

mers and requires V_IDon address bit A9.

Reading Array Data

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data. The device is also ready to read array

data after completing an Embedded Program or Em-

bedded Erase algorithm.

After the device accepts an Erase Suspend command,

the device enters the Erase Suspend mode. The sys-

tem can read array data using the standard read

timings, except that if it reads at an address within

erase-suspended sectors, the device outputs status

data. After completing a programming operation in the

Erase Suspend mode, the system may once again

read array data with the same exception. See “Erase

Suspend/Erase Resume Commands” for more infor-

mation on this mode.

The autoselect command sequence is initiated by writ-

ing two unlock cycles, followed by the autoselect

command. The device then enters the autoselect

mode, and the system may read at any address any

number of times, without initiating another command

sequence.

A read cycle at address XX00h or retrieves the manu-

facturer code. A read cycle at address XX01h returns

the device code. A read cycle containing a sector ad-

dress (SA) and the address 02h in returns 01h if that

sector is protected, or 00h if it is unprotected. Refer to

the Sector Address tables for valid sector addresses.

The system must issue the reset command to re-en-

able the device for reading array data if DQ5 goes high,

or while in the autoselect mode. See the “Reset Com-

mand” section, next.

The system must write the reset command to exit the

autoselect mode and return to reading array data.

See also “Requirements for Reading Array Data” in the

“Device Bus Operations” section for more information.

The Read Operations table provides the read parame-

ters, and Read Operation Timings diagram shows the

timing diagram.

Byte Program Command Sequence

Programming is a four-bus-cycle operation. The pro-

gram command sequence is initiated by writing two

unlock write cycles, followed by the program set-up

command. The program address and data are written

next, which in turn initiate the Embedded Program al-

gorithm. The system is not required to provide further

controls or timings. The device automatically provides

internally generated program pulses and verify the pro-

grammed cell margin. The Command Definitions take

shows the address and data requirements for the byte

program command sequence.

Reset Command

Writing the reset command to the device resets the de-

vice to reading array data. Address bits are don’t care

for this command.

The reset command may be written between the se-

quence cycles in an erase command sequence before

erasing begins. This resets the device to reading array

data. Once erasure begins, however, the device ig-

nores reset commands until the operation is complete.

When the Embedded Program algorithm is complete,

the device then returns to reading array data and ad-

dresses are no longer latched. The system can

determine the status of the program operation by using

DQ7 or DQ6. See “Write Operation Status” for informa-

tion on these status bits.

The reset command may be written between the se-

quence cycles in a program command sequence

before programming begins. This resets the device to

reading array data (also applies to programming in

Erase Suspend mode). Once programming begins,

Rev 2

Page 14 of 36

FT29F040B

WRITE OPERATION STATUS

The device provides several bits to determine the sta-

tus of a write operation: DQ2, DQ3, DQ5, DQ6, and

DQ7. Table 5 and the following subsections describe

the functions of these bits. DQ7 and DQ6 each offer a

method for determining whether a program or erase

operation is complete or in progress. These three bits

are discussed first.

rithms) figure in the “AC Characteristics” section

illustrates this.

Table 5 shows the outputs for Data# Polling on DQ7.

Figure 3 shows the Data# Polling algorithm.

START

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host sys-

tem whether an Embedded Algorithm is in progress or

completed, or whether the device is in Erase Suspend.

Data# Polling is valid after the rising edge of the final

WE# pulse in the program or erase command

sequence.

Read DQ7–DQ0

Addr = VA

During the Embedded Program algorithm, the device

outputs on DQ7 the complement of the datum pro-

grammed to DQ7. This DQ7 status also applies to

programming during Erase Suspend. When the Em-

bedded Program algorithm is complete, the device

outputs the datum programmed to DQ7. The system

must provide the program address to read valid status

information on DQ7. If a program address falls within a

protected sector, Data# Polling on DQ7 is active for ap-

proximately 2 µs, then the device returns to reading

array data.

Yes

DQ7 = Data?

DQ5 = 1?

Yes

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase al-

gorithm is complete, or if the device enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7.

This is analogous to the complement/true datum output

described for the Embedded Program algorithm: the

erase function changes all the bits in a sector to “1”;

prior to this, the device outputs the “complement,” or

“0.” The system must provide an address within any of

the sectors selected for erasure to read valid status in-

formation on DQ7.

Read DQ7–DQ0

Addr = VA

Yes

DQ7 = Data?

After an erase command sequence is written, if all sec-

tors selected for erasing are protected, Data# Polling

on DQ7 is active for approximately 100 µs, then the de-

vice returns to reading array data. If not all selected

sectors are protected, the Embedded Erase algorithm

erases the unprotected sectors, and ignores the se-

lected sectors that are protected.

PASS

FAIL

Notes:

1. VA = Valid address for programming. During a sector

erase operation, a valid address is an address within any

sector selected for erasure. During chip erase, a valid

address is any non-protected sector address.

When the system detects DQ7 has changed from the

complement to true data, it can read valid data at

DQ7–DQ0 on the following read cycles. This is be-

cause DQ7 may change asynchronously with

DQ0–DQ6 while Output Enable (OE#) is asserted low.

The Data# Polling Timings (During Embedded Algo-

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

Figure 3. Data# Polling Algorithm

Rev 2

Page 15 of 36

FT29F040B

sure. (The system may use either OE# or CE# to

control the read cycles.) But DQ2 cannot distinguish

whether the sector is actively erasing or is erase-sus-

pended. DQ6, by comparison, indicates whether the

device is actively erasing, or is in Erase Suspend, but

cannot distinguish which sectors are selected for era-

sure. Thus, both status bits are required for sector and

mode information. Refer to Table 5 to compare outputs

for DQ2 and DQ6.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded

Program or Erase algorithm is in progress or complete,

or whether the device has entered the Erase Suspend

mode. Toggle Bit I may be read at any address, and is

valid after the rising edge of the final WE# pulse in the

command sequence (prior to the program or erase op-

eration), and during the sector erase time-out.

During an Embedded Program or Erase algorithm op-

eration, successive read cycles to any address cause

DQ6 to toggle. (The system may use either OE# or

CE# to control the read cycles.) When the operation is

complete, DQ6 stops toggling.

Figure 4 shows the toggle bit algorithm in flowchart

form, and the section “DQ2: Toggle Bit II” explains the

algorithm. See also the “DQ6: Toggle Bit I” subsection.

Refer to the Toggle Bit Timings figure for the toggle bit

timing diagram. The DQ2 vs. DQ6 figure shows the dif-

ferences between DQ2 and DQ6 in graphical form.

After an erase command sequence is written, if all sec-

tors selected for erasing are protected, DQ6 toggles for

approximately 100 µs, then returns to reading array

data. If not all selected sectors are protected, the Em-

bedded Erase algorithm erases the unprotected

sectors, and ignores the selected sectors that are

protected.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 4 for the following discussion. When-

ever the system initially begins reading toggle bit

status, it must read DQ7–DQ0 at least twice in a row to

determine whether a toggle bit is toggling. Typically, a

system would note and store the value of the toggle bit

after the first read. After the second read, the system

would compare the new value of the toggle bit with the

first. If the toggle bit is not toggling, the device has com-

pleted the program or erase operation. The system can

read array data on DQ7–DQ0 on the following read

cycle.

The system can use DQ6 and DQ2 together to deter-

mine whether a sector is actively erasing or is erase-

suspended. When the device is actively erasing (that is,

the Embedded Erase algorithm is in progress), DQ6

toggles. When the device enters the Erase Suspend

mode, DQ6 stops toggling. However, the system must

also use DQ2 to determine which sectors are erasing

or erase-suspended. Alternatively, the system can use

DQ7 (see the subsection on “DQ7: Data# Polling”).

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the sys-

tem also should note whether the value of DQ5 is high

(see the section on DQ5). If it is, the system should

then determine again whether the toggle bit is toggling,

since the toggle bit may have stopped toggling just as

DQ5 went high. If the toggle bit is no longer toggling,

the device has successfully completed the program or

erase operation. If it is still toggling, the device did not

complete the operation successfully, and the system

must write the reset command to return to reading

array data.

If a program address falls within a protected sector,

DQ6 toggles for approximately 2 µs after the program

command sequence is written, then returns to reading

array data.

DQ6 also toggles during the erase-suspend-program

mode, and stops toggling once the Embedded Pro-

gram algorithm is complete.

The Write Operation Status table shows the outputs for

Toggle Bit I on DQ6. Refer to Figure 4 for the toggle bit

algorithm, and to the Toggle Bit Timings figure in the

“AC Characteristics” section for the timing diagram.

The DQ2 vs. DQ6 figure shows the differences be-

tween DQ2 and DQ6 in graphical form. See also the

subsection on “DQ2: Toggle Bit II”.

The remaining scenario is that the system initially de-

termines that the toggle bit is toggling and DQ5 has not

gone high. The system may continue to monitor the

toggle bit and DQ5 through successive read cycles, de-

termining the status as described in the previous

paragraph. Alternatively, it may choose to perform

other system tasks. In this case, the system must start

at the beginning of the algorithm when it returns to de-

termine the status of the operation (top of Figure 4).

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indi-

cates whether a particular sector is actively erasing

(that is, the Embedded Erase algorithm is in progress),

or whether that sector is erase-suspended. Toggle Bit

II is valid after the rising edge of the final WE# pulse in

the command sequence.

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has

exceeded a specified internal pulse count limit. Under

these conditions DQ5 produces a “1.” This is a failure

condition that indicates the program or erase cycle was

DQ2 toggles when the system reads at addresses

within those sectors that have been selected for era-

not successfully completed.

Rev 2

Page 16 of 36

FT29F040B

The DQ5 failure condition may appear if the system

tries to program a “1” to a location that is previously pro-

grammed to “0.” Only an erase operation can change

a “0” back to a “1.” Under this condition, the device

halts the operation, and when the operation has ex-

ceeded the timing limits, DQ5 produces a “1.”

START

Under both these conditions, the system must issue the

reset command to return the device to reading array

data.

Read DQ7–DQ0

(Note 1)

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the

system may read DQ3 to determine whether or not an

erase operation has begun. (The sector erase timer

does not apply to the chip erase command.) If addi-

tional sectors are selected for erasure, the entire time-

out also applies after each additional sector erase com-

mand. When the time-out is complete, DQ3 switches

from “0” to “1.” The system may ignore DQ3 if the sys-

tem can guarantee that the time between additional

sector erase commands is always less than 50 µs. See

also the “Sector Erase Command Sequence” section.

Toggle Bit

= Toggle?

Yes

DQ5 = 1?

Yes

After the sector erase command sequence is written,

the system should read the status on DQ7 (Data# Poll-

ing) or DQ6 (Toggle Bit I) to ensure the device has

accepted the command sequence, and then read DQ3.

If DQ3 is “1”, the internally controlled erase cycle has

begun; all further commands (other than Erase Sus-

pend) are ignored until the erase operation is complete.

If DQ3 is “0”, the device accepts additional sector erase

commands. To ensure the command has been ac-

cepted, the system software should check the status of

DQ3 prior to and following each subsequent sector

erase command. If DQ3 is high on the second status

check, the last command might not have been ac-

cepted. Table 5 shows the outputs for DQ3.

Read DQ7–DQ0

Twice

(Notes 1,

Toggle Bit

= Toggle?

Yes

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Notes:

1. Read toggle bit twice to determine whether or not it is

toggling. See text.

2. Recheck toggle bit because it may stop toggling as DQ5

changes to “1”. See text.

Figure 4. Toggle Bit Algorithm

Rev 2

Page 17 of 36

FT29F040B

Table 5. Write Operation Status

DQ7

DQ5

DQ2

Operation

(Note 1)

DQ7#

DQ6

(Note 2)

DQ3

N/A

(Note 1)

No toggle

Toggle

Embedded Program Algorithm

Embedded Erase Algorithm

Toggle

Standard

Mode

Reading within Erase

Suspended Sector

No toggle

N/A

Toggle

Erase

Suspend Reading within Non-Erase

Data

N/A

Data

N/A

Mode

Suspended Sector

Erase-Suspend-Program

DQ7#

Toggle

Notes:

1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

2. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See “DQ5: Exceeded Timing Limits” for more information.

Rev 2

Page 18 of 36

FT29F040B

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +125°C

20 ns

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –55°C to +125°C

+0.8 V

Voltage with Respect to Ground

–0.5 V

–2.0 V

(Note 1) . . . . . . . . . . . . . . . . .–2.0 V to 7.0 V

A9, OE# (Note 2). . . . . . . . . . . . .–2.0 V to 12.5 V

All other pins (Note 1) . . . . . . . . . .–2.0 V to 7.0 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

20 ns

Figure 5. Maximum Negative

Overshoot Waveform

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V. During

voltage transitions, inputs may undershoot V to –2.0 V

for periods of up to 20 ns. See Figure 5. Maximum DC

voltage on input and I/O pins is V

+ 0.5 V. During

voltage transitions, input and I/O pins may overshoot to

+ 2.0 V for periods up to 20 ns. See Figure 6.

20 ns

2. Minimum DC input voltage on A9 pin is –0.5 V. During

voltage transitions, A9 and OE# may undershoot V to

+2.0 V

–2.0 V for periods of up to 20 ns. See Figure 5. Maximum

DC input voltage on A9 and OE# is 12.5 V which may

overshoot to 13.5 V for periods up to 20 ns.

+0.5 V

2.0 V

3. No more than one output shorted to ground at a time.

Duration of the short circuit should not be greater than

one second.

20 ns

Figure 6. Maximum Positive

Overshoot Waveform

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This is

a stress rating only; functional operation of the device at

these or any other conditions above those indicated in the op-

erational sections of this specification is not implied. Expo-

sure of the device to absolute maximum rating conditions for

extended periods may affect device reliability.

for ± 10% devices . . . . . . . . . . . +4.5 V to +5.5 V

OPERATING RANGES

Operating ranges define those limits between which the

functionality of the device is guaranteed.

Commercial (C) Devices

Ambient Temperature (T ) . . . . . . . . . . . 0°C to +70°C

Industrial (I) Devices

Ambient Temperature (T ) . . . . . . . . . –40°C to +85°C

Extended (E) Devices

Ambient Temperature (T ) . . . . . . . . –55°C to +125°C

Supply Voltages

for ± 5% devices. . . . . . . . . . .+4.75 V to +5.25 V

Rev 2

Page 19 of 36

FT29F040B

DC CHARACTERISTICS

TTL/NMOS Compatible

Parameter

Symbol

Parameter Description

Test Description

= V to V , V = V Max

Min

Typ

Max

±1.0

Unit

µA

Input Load Current

A9 Input Load Current

Output Leakage Current

= V Max, A9 = 12.5 V

µA

LIT

OUT

= V to V , V = V Max

±1.0

µA

CC CC

Active Read Current (Notes 1, 2) CE# = V , OE# = V

CC1

Active Write (Program/Erase)

Current (Notes 2, 3, 4)

CE# = V , OE# = V

CC2

Standby Current (Note 2)

CE# = V

0.4

1.0

0.8

CC3

Input Low Level

Input High Level

–0.5

2.0

+ 0.5

Voltage for Autoselect

and Sector Protect

= 5.25 V

10.5

12.5

0.45

Output Low Voltage

Output High Voltage

= 12 mA, V = V Min

= –2.5 mA, V = V Min

2.4

3.2

Low V Lock-Out Voltage

4.2

LKO

CMOS Compatible

Parameter

Symbol

Parameter Description

Test Description

Min

Typ

Max

±1.0

Unit

µA

Input Load Current

= V to V , V = V Max

A9 Input Load Current

Output Leakage Current

= V Max, A9 = 12.5 V

µA

LIT

= V to V , V = V Max

±1.0

µA

OUT

CC CC

Active Read Current

CE# = V , OE# = V

CC1

(Notes 1, 2)

Active Program/Erase Current

CE# V , OE#

= VIH

CC2

CC3

(Notes 2, 3, 4)

Standby Current (Notes 2, 5)

CE# = V ± 0.5 V

µA

Input Low Level

Input High Level

–0.5

0.8

0.7 x V

V + 0.3

Voltage for Autoselect and Sector

Protect

= 5.25 V

10.5

12.5

0.45

Output Low Voltage

Output High Voltage

= 12.0 mA, V = V Min

= –2.5 mA, V = V Min

0.85 V

OH1

OH2

= –100 μA, V = V Min

–0.4

Low V Lock-out Voltage

3.2

4.2

LKO

Notes for DC Characteristics (both tables):

1. The I current listed includes both the DC operating current and the frequency dependent component (at 6 MHz).

The frequency component typically is less than 2 mA/MHz, with OE# at V .

2. Maximum I specifications are tested with V = V .

CCmax

3. I active while Embedded Algorithm (program or erase) is in progress.

4. Not 100% tested.

5. For CMOS mode only, I

= 20 µA max at extended temperatures (> +85°C).

CC3

Rev 2

Page 20 of 36

FT29F040B

TEST CONDITIONS

Table 6. Test Specifications

5.0 V

Test Condition

Output Load

-55

All others Unit

2.7 kΩ

1 TTL gate

100

Device

Under

Test

Output Load Capacitance, C

(including jig capacitance)

6.2 kΩ

Input Rise and Fall Times

Input Pulse Levels

0.0–3.0 0.45–2.4

Input timing measurement

reference levels

1.5

0.8, 2.0

Note: Diodes are IN3064 or equivalent

Output timing measurement

reference levels

Figure 7. Test Setup

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State (High Z)

Rev 2

Page 21 of 36

FT29F040B

AC CHARACTERISTICS

Read Only Operations

Parameter Symbols

Speed Options (Note 1)

JEDEC

Std

Description

Test Setup

-55

-70

-90 -120 -150 Unit

Read Cycle Time (Note 3)

Min

120

150

AVAV

CE# = V

OE# = V

IL,

Address to Output Delay

Max

AVQV

ACC

Chip Enable to Output Delay

Output Enable to Output Delay

OE# = V

Max

Min

120

150

ELQV

GLQV

Read

Output Enable Hold

OEH

Toggle and

Data# Polling

Time (Note 3)

Min

Chip Enable to Output High Z

(Notes 2, 3)

Max

EHQZ

GHQZ

Output Enable to Output High Z

(Notes 2, 3)

Output Hold Time from Addresses, CE#

or OE#, Whichever Occurs First

Min

AXQX

Notes:

1. See Figure 7 and Table 6 for test conditions.

2. Output driver disable time.

3. Not 100% tested.

t_RC

Addresses Stable

t_ACC

Addresses

CE#

t_DF

t_OE

OE#

WE#

t_OEH

t_CE

t_OH

HIGH Z

Output Valid

Outputs

0 V

Figure 8. Read Operation Timings

Rev 2

Page 22 of 36

FT29F040B

AC CHARACTERISTICS

Erase and Program Operations

Parameter Symbols

Speed Options

-70 -90 -120

JEDEC

Std

Description

Write Cycle Time (Note 1)

Address Setup Time

Address Hold Time

-55

-150

Unit

Min

120

150

AVAV

AVWL

WLAX

DVWH

WHDX

Data Setup Time

Data Hold Time

Output Enable Setup Time

OES

Read Recover Time Before Write

(OE# high to WE# low)

Min

GHWL

CE# Setup Time

Min

ELWL

WHEH

WLWH

WHWL

CE# Hold Time

Write Pulse Width

Write Pulse Width High

WPH

Byte Programming Operation

(Note 2)

Typ

µs

WHWH1

WHWH2

WHWH1

WHWH2

Sector Erase Operation

(Note 2))

Typ

Min

sec

µs

Set Up Time (Note 1))

VCS

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

Rev 2

Page 23 of 36

FT29F040B

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

Read Status Data (last two cycles)

t_AS

t_WC

Addresses

555h

t_AH

CE#

OE#

t_CH

t_WHWH1

t_WP

WE#

t_WPH

t_CS

t_DS

t_DH

D_OUT

A0h

Status

Data

V_CC

t_VCS

Note: PA = program address, PD = program data, D

is the true data at the program address.

OUT

Figure 9. Program Operation Timings

Erase Command Sequence (last two cycles)

Read Status Data

t_AS

t_WC

Addresses

CE#

2AAh

555h for chip erase

t_AH

t_CH

OE#

t_WP

WE#

t_WPH

t_WHWH2

t_CS

t_DS

t_DH

Data

V_CC

Complete

55h

30h

Progress

10 for Chip Erase

t_VCS

Note:

SA = Sector Address. VA = Valid Address for reading status data.

Figure 10. Chip/Sector Erase Operation Timings

Rev 2

Page 24 of 36

FT29F040B

AC CHARACTERISTICS

t_RC

Addresses

t_ACC

t_CE

CE#

t_CH

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

High Z

DQ7

Valid Data

Complement

True

High Z

DQ0–DQ6

Status Data

True

Valid Data

Status Data

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data

read cycle .

Figure 11. Data# Polling Timings (During Embedded Algorithms)

t_RC

Addresses

CE#

t_ACC

t_CE

t_CH

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

High Z

DQ6/DQ2

Valid Status

(first read)

Valid Status

Valid Data

(second read)

(stops toggling)

Note:

VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle,

and array data read cycle.

Figure 12. Toggle Bit Timings (During Embedded Algorithms)

Rev 2

Page 25 of 36

FT29F040B

AC CHARACTERISTICS

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

Erase

Erase Suspend

Read

Erase

Suspend

Program

Erase

Complete

WE#

Erase

Erase Suspend

Read

DQ6

DQ2

DQ2 and DQ6 toggle with OE# and CE#

Note: Both DQ6 and DQ2 toggle with OE# or CE#. See the text on DQ6 and DQ2 in the section “Write Operation Status” for more

information.

Figure 13. DQ2 vs. DQ6

Rev 2

Page 26 of 36

FT29F040B

AC CHARACTERISTICS

Erase and Program Operations

Alternate CE# Controlled Writes

Parameter Symbols

Speed Options

-70 -90 -120

JEDEC

Std

Description

Write Cycle Time (Note 1))

Address Setup Time

Address Hold Time

-55

-150

Unit

Min

120

150

AVAV

AVEL

ELAX

DVEH

EHDX

Data Setup Time

Data Hold Time

Read Recover Time Before Write

CE# Setup Time

GHEL

WLEL

CE# Hold Time

EHWH

Write Pulse Width

ELEH

EHEL

Write Pulse Width High

CPH

Byte Programming Operation

(Note 2))

Typ

µs

WHWH1

WHWH2

WHWH1

WHWH2

Sector Erase Operation

(Note 2))

sec

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

Rev 2

Page 27 of 36

FT29F040B

AC CHARACTERISTICS

555 for program

PA for program

2AA for erase

SA for sector erase

555 for chip erase

Data# Polling

Addresses

t_WC

t_WH

t_AS

t_AH

WE#

OE#

t_GHEL

t_{WHWH1 or 2}

t_CP

CE#

Data

t_WS

t_CPH

t_DS

t_BUSY

t_DH

DQ7#

D_OUT

t_RH

A0 for program

55 for erase

PD for program

30 for sector erase

10 for chip erase

Notes:

1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, D

= Array Data.

OUT

2. Figure indicates the last two bus cycles of the command sequence.

Figure 14. Alternate CE# Controlled Write Operation Timings

Rev 2

Page 28 of 36

FT29F040B

ERASE AND PROGRAMMING PERFORMANCE

Typ

Max

Parameter

Sector Erase Time

(Note 1) (Note 2) Unit

Comments

sec

µs

Excludes 00h programming prior to erasure (Note 4)

Chip Erase Time

Byte Programming Time

Chip Programming Time (Note 3)

300

10.8

Excludes system-level overhead (Note 5)

3.6

sec

Notes:

1. Typical program and erase times assume the following conditions: 25°C, 5.0 V V , 1,000,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V = 4.5 V (4.75 V for -55), 1,000,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then

does the device set DQ5 = 1. See the section on DQ5 for further information.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 4

for further information on command definitions.

6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTICS

Min

Max

+ 1.0 V

Input Voltage with respect to V on all I/O pins

–1.0 V

Current

–100 mA

+100 mA

Includes all pins except V . Test conditions: V = 5.0 V, one pin at a time.

TSOP PIN CAPACITANCE

Parameter Symbol

Parameter Description

Input Capacitance

Test Setup

= 0

Typ

Max

Unit

7.5

Output Capacitance

= 0

8.5

7.5

OUT

Control Pin Capacitance

= 0

IN2

Notes:

1. Sampled, not 100% tested.

2. Test conditions T = 25°C, f = 1.0 MHz.

Rev 2

Page 29 of 36

FT29F040B

PLCC AND PDIP PIN CAPACITANCE

Parameter Symbol

Parameter Description

Test Setup

= 0

Typ

Max

Unit

Input Capacitance

Output Capacitance

Control Pin Capacitance

= 0

OUT

= 0

IN2

Notes:

1. Sampled, not 100% tested.

2. Test conditions T = 25°C, f = 1.0 MHz.

DATA RETENTION

Parameter

Test Conditions

150°C

Min

Unit

Years

Minimum Pattern Data Retention Time

125°C

Rev 2

Page 30 of 36

FT29F040B

PHYSICAL DIMENSIONS

PD 032—32-Pin Plastic DIP

Dwg rev AD; 10/99

Rev 2

Page 31 of 36

FT29F040B

PHYSICAL DIMENSIONS (continued)

PL 032—32-Pin Plastic Leaded Chip Carrier

Dwg rev AH; 10/99

Rev 2

Page 32 of 36

FT29F040B

PHYSICAL DIMENSIONS (continued)

TS 032—32-Pin Standard Thin Small Package

Dwg rev AA; 10/99

Rev 2

Page 33 of 36

FT29F040B

PHYSICAL DIMENSIONS (continued)

TSR032—32-Pin Reversed Thin Small Outline Package

Dwg rev AA; 10/99

Rev 2

Page 34 of 36

32 Lead Cerquad "K" (CQ032)

Rev 2

Page 35 of 36

32 Lead Cerquad "K" Lid (CQ032L)

Rev 2

Page 36 of 36

FT29F040B-150EK [FORCE]

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