FTC41041-10JCLF [FORCE]
HIGH SPEED 256K x 16 (4 MEG) STATIC CMOS RAM;型号: | FTC41041-10JCLF |
厂家: | Force Technologies |
描述: | HIGH SPEED 256K x 16 (4 MEG) STATIC CMOS RAM |
文件: | 总11页 (文件大小:1528K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
FTC41041
HIGH SPEED 256K x 16 (4 MEG)
STATIC CMOS RAM
FEATURES
Easy Memory Expansion Using CE and OE
Inputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Fast tOE
Automatic Power Down when deselected
Package: 44-Pin SOJ
High Speed (Equal Access and Cycle Times)
— 10/12/15/20 ns (Commercial)
— 12/15/20 ns (Industrial/Military)
Low Power
Single 5.0V ± 10% Power Supply
2.0V Data Retention
DESCRIPTION
The FTC41041 device provides asynchronous operation
with matching access and cycle times. Memory loca-
tions are specified on address pins A0 to A17. Reading
is accomplished by device selection (CE and output
enabling (OE) while write enable (WE) remains HIGH.
By presenting the address under these conditions, the
data in the addressed memory location is presented on
the data input/output pins. The input/output pins stay
in the HIGH Z state when either CE or OE is HIGH or
WE is LOW.
The FTC41041 is a 262,144 words by 16 bits high-speed
CMOS static RAM. The CMOS memory requires no
clocks or refreshing, and has equal access and cycle
times. Inputs are fully TTL-compatible. The RAM
operates from a single 5.0V ± 10% tolerance power
supply.
Access times as fast as 10 nanoseconds permit greatly
enhanced system operating speeds. CMOS is utilised
to reduce power consumption to a low level.
The FTC41041 is a member of a family of FTSRAM
products offering fast access times.
PIN CONFIGURATION
FUNCTIONAL BLOCK DIAGRAM
SOJ
2013
1 of 11
Rev C
FTC41041
HIGH SPEED 256K x 16 (4 MEG)
STATIC CMOS RAM
RECOMMENDED OPERATING
MAXIMUM RATINGS (1)
TEMPERATURE AND SUPPLY VOLTAGE
Grade(2)
Ambient Temperature GND
VCC
Sym
Parameter
Value
Unit
VCC
Power Supply Pin with
Respect to GND
-0.5 to 7.0
V
Commercial
0 - 70°C
-40 - 85°C
-55 - 125°C
0V
0V
0V
5.0V ± 10%
Industrial
Military
5.0V ± 10%
5.0V ± 10%
VTERM
Terminal Voltage with
Respect to GND
-0.5 to VCC+0.5
V
TA
Operating Temperature
Temperature Under Bias
Storage Temperature
DC Output Current
-55 to 125
-55 to 125
-65 to 150
20
°C
°C
CAPACITANCES (4)
TBIAS
TSTG
IOUT
VCC = 5.0V, TA = 25°C, f = 1.0MHz
°C
Sym Parameter
Conditions Typ. Unit
mA
CIN
Input Capacitance
VIN = 0V
8
8
pF
pF
COUT Output Capacitance
VOUT = 0V
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage (2)
FTC41041
Sym Parameter
Test Conditions
Unit
Min
2.2
Max
VCC +0.5
0.8
VIH
VIL
VOL
VOH
ILI
Input High Voltage
V
V
Input Low Voltage
-0.5(3)
Output Low Voltage (TTL Load)
Output High Voltage (TTL Load)
Input Leakage Current
0.4
V
IOL = +8 mA, VCC = Min.
IOH = –4 mA, VCC = Min.
2.4
-2
V
+2
+1
µA
VCC = Max.
VIN = GND to VCC
ILO
Output Leakage Current
-1
µA
VCC = Max.,
CE = VIH,
VOUT = GND to VCC
ISB
Standby Power Supply Current (TTL Input Levels)
—
40
mA
CE ≥ VIH
VCC= Max,
f = Max., Outputs Open
VIN ≥ VIH orVIN ≤ VIL
ISB1
Standby Power Supply Current (CMOS Input Levels)
—
6
mA
CE ≥ VCC - 0.2V
VCC= Max,
f = 0, Outputs Open
VIN ≥ VCC - 0.3V or
VIN ≤ 0.3V
2013
2 of 11
Rev C
FTC41041
HIGH SPEED 256K x 16 (4 MEG)
STATIC CMOS RAM
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Sym
Parameter
Temperature Range
Commercial
Industrial
-10
100
100
N/A
-12
90
-15
80
-20
70
70
90
Unit
mA
mA
mA
ICC
Dynamic Operating Current*
90
80
Military
110
100
*VCC = 3.6V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = VIL, OE = VIH.
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(VCC = 5.0V ± 10%, All Temperature Ranges) (2)
-10
-12
-15
-20
Sym
Parameter
Read Cycle Time
Unit
Min
Max
Min
Max
Min
Max
Min
Max
tRC
tAA
10
12
15
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
10
10
12
12
15
15
20
20
tAC
Chip Enable Access Time
tOH
tLZ
Output Hold from Address Change
Chip Enable to Output in Low Z
Chip Disable to Output in High Z
Output Enable Low to Data Valid
Output Enable Low to Low Z
Output Enable High to High Z
Chip Enable to Power Up Time
Chip Disable to Power Down Time
Byte Enable to Data Valid
3
3
3
3
3
3
3
3
tHZ
5
5
6
6
7
7
8
8
tOE
tOLZ
tOHZ
tPU
0
0
0
0
0
0
0
0
5
6
7
8
tPD
10
5
12
6
15
7
20
8
tBE
tLZBE
tHZBE
Byte Enable to Low Z
0
0
0
0
Byte Disable to High Z
6
6
7
8
2013
3 of 11
Rev C
FTC41041
HIGH SPEED 256K x 16 (4 MEG)
STATIC CMOS RAM
TIMING WAVEFORM OF READ CYCLE NO. 1
TIMING WAVEFORM OF READ CYCLE NO. 2 (OE CONTROLLED)(5,6)
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
4. This parameter is sampled and not 100% tested.
5. WE is HIGH for READ cycle.
6. CE is LOW and OE is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with CE transition
LOW.
8. Transition is measured ± 200 mV from steady state voltage prior
to change, with loading as specified in Figure 1. This parameter is
sampled and not 100% tested.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
9. Read Cycle Time is measured from the last valid address to the first
transitioning address.
3. Transient inputs with VIL not more negative than –2.0V and
VIH ≤ VCC + 0.5V, are permissible for pulse widths up to 20ns.
2013
4 of 11
Rev C
FTC41041
HIGH SPEED 256K x 16 (4 MEG)
STATIC CMOS RAM
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Value
Output Load
3ns
1.5V
1.5V
See Figures 1 & 2
Figure 1. Output Load
Figure 2. Thevenin Equivalent
* including scope and test fixture.
Note:
Becauseoftheultra-highspeedofthe FTC41041,caremustbetakenwhen
testing this device; an inadequate setup can cause a normal functioning
part to be rejected as faulty. Long high-inductance leads that cause
supply bounce must be avoided by bringing the VCC and ground planes
directly up to the contactor fingers. A 0.01 µF high frequency capacitor
is also required between VCC and ground. To avoid signal reflections,
proper termination must be used; for example, a 50Ω test environment
should be terminated into a 50Ω load with 1.73V (Thevenin Voltage) at
the comparator input, and a 116Ω resistor must be used in series with
DOUT to match 166Ω (Thevenin Resistance).
TRUTH TABLE
Mode
CE
H
L
OE
X
L
WE
X
BLE
X
BHE
X
I/O0 - I/O7
High Z
DOUT
I/O8 - I/O15
High Z
DOUT
Power
Standby
Active
Active
Active
Active
Active
Active
Active
Powerdown
Read All Bits
H
H
H
L
L
L
Read Lower Bits Only
Read Upper Bits Only
Write All Bits
L
L
L
H
L
DOUT
High Z
DOUT
L
L
H
L
High Z
DIN
L
X
X
X
H
L
DIN
Write Lower Bits Only
Write Upper Bits Only
Selected, Outputs Disabled
L
L
L
H
L
DIN
High Z
DIN
L
L
H
X
High Z
High Z
L
H
X
High Z
2013
7 of 11
Rev C
FTC41041
HIGH SPEED 256K x 16 (4 MEG)
STATIC CMOS RAM
SOJ SMALL OUTLINE IC PACKAGE
Pkg #
J8
# Pins
44 (400 mil)
Symbol
Min
Max
0.148
-
A
A1
b
0.128
0.082
0.013
0.007
1.120
0.023
0.013
1.130
C
D
e
0.050 BSC
E
0.435
0.395
0.445
0.405
E1
E2
Q
0.370 BSC
0.025
-
2013
9 of 11
Rev C
FTC41041
HIGH SPEED 256K x 16 (4 MEG)
STATIC CMOS RAM
REVISIONS
DOCUMENT NUMBER SRAM 1478
DOCUMENT TITLE
FTC41041 HIGH SPEED 256K X 16 (4 MEG) STATIC CMOS RAM
REV ISSUE DATE
ORIGINATOR DESCRIPTION OF CHANGE
OR
A
Jan-2007
July-2008
Sept-2009
Nov-2013
BS
BS
BS
JC
New Data Sheet
Added Military processing, lead-free designation
Updated TSOP II Package Drawing
B
Removed TSOP II Package Drawing
C
2013
10 of 11
Rev C
FTC41041
HIGH SPEED 256K x 16 (4 MEG)
STATIC CMOS RAM
ORDERING INFORMATION
FTC41041
XX
X
X
X
-
Device Type
Speed
Package
Processing
Lead-Free
LF
(Blank)
RoHS Compliant
Standard
C
I
M
0°C to +70°C
-40°C to +85°C
-55°C to +125°C
J
Plastic SOJ, 400 Mil
10, 12, 15, 20 ns
256K x 16 SRAM
2013
8 of 11
Rev C
FTC41041
HIGH SPEED 256K x 16 (4 MEG)
STATIC CMOS RAM
SOJ SMALL OUTLINE IC PACKAGE
Pkg #
J8
# Pins
44 (400 mil)
Symbol
Min
Max
0.148
-
A
A1
b
0.128
0.082
0.013
0.007
1.120
0.023
0.013
1.130
C
D
e
0.050 BSC
E
0.435
0.395
0.445
0.405
E1
E2
Q
0.370 BSC
0.025
-
2013
9 of 11
Rev C
FTC41041
HIGH SPEED 256K x 16 (4 MEG)
STATIC CMOS RAM
REVISIONS
DOCUMENT NUMBER SRAM 1478
DOCUMENT TITLE
FTC41041 HIGH SPEED 256K X 16 (4 MEG) STATIC CMOS RAM
REV ISSUE DATE
ORIGINATOR DESCRIPTION OF CHANGE
OR
A
Jan-2007
July-2008
Sept-2009
Nov-2013
BS
BS
BS
JC
New Data Sheet
Added Military processing, lead-free designation
Updated TSOP II Package Drawing
B
Removed TSOP II Package Drawing
C
2013
10 of 11
Rev C
Ashley Crt, Henley,
Marlborough, Wilts, SN8 3RH UK
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Fax:+44(0)1264 731444
E-mail
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sales@forcetechnologies.co.uk
www.forcetechnologies.co.uk
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Copyright Force Technologies Ltd 2010
All trademarks acknowledged
2013
11 of 11
Rev C
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