FTC41041-20JILF [FORCE]

HIGH SPEED 256K x 16 (4 MEG) STATIC CMOS RAM;


型号：	FTC41041-20JILF
厂家：	Force Technologies
描述：	HIGH SPEED 256K x 16 (4 MEG) STATIC CMOS RAM
文件：	总11页 (文件大小：1528K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FTC41041

HIGH SPEED 256K x 16 (4 MEG)

STATIC CMOS RAM

FEATURES

Easy Memory Expansion Using CE and OE

Inputs

Fully TTL Compatible Inputs and Outputs

Advanced CMOS Technology

Fast t_OE

Automatic Power Down when deselected

Package: 44-Pin SOJ

High Speed (Equal Access and Cycle Times)

— 10/12/15/20 ns (Commercial)

— 12/15/20 ns (Industrial/Military)

Low Power

Single 5.0V ± 10% Power Supply

2.0V Data Retention

DESCRIPTION

The FTC41041 device provides asynchronous operation

with matching access and cycle times. Memory loca-

tions are speciﬁed on address pins A₀to A₁₇. Reading

is accomplished by device selection (CE and output

enabling (OE) while write enable (WE) remains HIGH.

By presenting the address under these conditions, the

data in the addressed memory location is presented on

the data input/output pins. The input/output pins stay

in the HIGH Z state when either CE or OE is HIGH or

WE is LOW.

The FTC41041 is a 262,144 words by 16 bits high-speed

CMOS static RAM. The CMOS memory requires no

clocks or refreshing, and has equal access and cycle

times. Inputs are fully TTL-compatible. The RAM

operates from a single 5.0V ± 10% tolerance power

supply.

Access times as fast as 10 nanoseconds permit greatly

enhanced system operating speeds. CMOS is utilised

to reduce power consumption to a low level.

The FTC41041 is a member of a family of FTSRAM

products offering fast access times.

PIN CONFIGURATION

FUNCTIONAL BLOCK DIAGRAM

SOJ

2013

1 of 11

Rev C

FTC41041

HIGH SPEED 256K x 16 (4 MEG)

STATIC CMOS RAM

RECOMMENDED OPERATING

MAXIMUM RATINGS ⁽¹⁾

TEMPERATURE AND SUPPLY VOLTAGE

Grade⁽²⁾

Ambient Temperature GND

V_CC

Sym

Parameter

Value

Unit

V_CC

Power Supply Pin with

Respect to GND

-0.5 to 7.0

Commercial

0 - 70°C

-40 - 85°C

-55 - 125°C

5.0V ± 10%

Industrial

Military

5.0V ± 10%

V_TERM

Terminal Voltage with

Respect to GND

-0.5 to VCC+0.5

T_A

Operating Temperature

Temperature Under Bias

Storage Temperature

DC Output Current

-55 to 125

-65 to 150

°C

CAPACITANCES ⁽⁴⁾

T_BIAS

T_STG

I_OUT

V_CC= 5.0V, T_A= 25°C, f = 1.0MHz

°C

Sym Parameter

Conditions Typ. Unit

C_IN

Input Capacitance

V_IN= 0V

C_OUTOutput Capacitance

V_OUT= 0V

DC ELECTRICAL CHARACTERISTICS

Over recommended operating temperature and supply voltage ⁽²⁾

FTC41041

Sym Parameter

Test Conditions

Unit

Min

2.2

Max

V_CC+0.5

0.8

V_IH

V_IL

V_OL

V_OH

I_LI

Input High Voltage

Input Low Voltage

-0.5⁽³⁾

Output Low Voltage (TTL Load)

Output High Voltage (TTL Load)

Input Leakage Current

0.4

I_OL= +8 mA, V_CC= Min.

I_OH= –4 mA, V_CC= Min.

2.4

-2

µA

V_CC= Max.

V_IN= GND to V_CC

I_LO

Output Leakage Current

-1

µA

V_CC= Max.,

CE = V_IH,

V_OUT= GND to V_CC

I_SB

Standby Power Supply Current (TTL Input Levels)

—

CE ≥ V_IH

V_CC= Max,

f = Max., Outputs Open

V_IN≥ V_IHorV_IN≤ V_IL

I_SB1

Standby Power Supply Current (CMOS Input Levels)

—

CE ≥ V_CC- 0.2V

V_CC= Max,

f = 0, Outputs Open

V_IN≥ V_CC- 0.3V or

V_IN≤ 0.3V

2013

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Rev C

FTC41041

HIGH SPEED 256K x 16 (4 MEG)

STATIC CMOS RAM

POWER DISSIPATION CHARACTERISTICS VS. SPEED

Sym

Parameter

Temperature Range

Commercial

Industrial

-10

100

N/A

-12

-15

-20

Unit

I_CC

Dynamic Operating Current*

Military

110

100

*V_CC= 3.6V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = V_IL, OE = V_IH.

AC ELECTRICAL CHARACTERISTICS—READ CYCLE

(V_CC= 5.0V ± 10%, All Temperature Ranges) ⁽²⁾

-10

-12

-15

-20

Sym

Parameter

Read Cycle Time

Unit

Min

Max

Min

Max

Min

Max

Min

Max

t_RC

t_AA

Address Access Time

t_AC

Chip Enable Access Time

t_OH

t_LZ

Output Hold from Address Change

Chip Enable to Output in Low Z

Chip Disable to Output in High Z

Output Enable Low to Data Valid

Output Enable Low to Low Z

Output Enable High to High Z

Chip Enable to Power Up Time

Chip Disable to Power Down Time

Byte Enable to Data Valid

t_HZ

t_OE

t_OLZ

t_OHZ

t_PU

t_PD

t_BE

t_LZBE

t_HZBE

Byte Enable to Low Z

Byte Disable to High Z

2013

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Rev C

FTC41041

HIGH SPEED 256K x 16 (4 MEG)

STATIC CMOS RAM

TIMING WAVEFORM OF READ CYCLE NO. 1

TIMING WAVEFORM OF READ CYCLE NO. 2 (OE CONTROLLED)^(5,6)

Notes:

1. Stresses greater than those listed under MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any other conditions

above those indicated in the operational sections of this speciﬁcation

is not implied. Exposure to MAXIMUM rating conditions for extended

periods may affect reliability.

4. This parameter is sampled and not 100% tested.

5. WE is HIGH for READ cycle.

6. CE is LOW and OE is LOW for READ cycle.

7. ADDRESS must be valid prior to, or coincident with CE transition

LOW.

8. Transition is measured ± 200 mV from steady state voltage prior

to change, with loading as speciﬁed in Figure 1. This parameter is

sampled and not 100% tested.

2. Extended temperature operation guaranteed with 400 linear feet per

minute of air ﬂow.

9. Read Cycle Time is measured from the last valid address to the ﬁrst

transitioning address.

3. Transient inputs with V_ILnot more negative than –2.0V and

^V_IH≤ V_CC+ 0.5V, are permissible for pulse widths up to 20ns.

2013

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Rev C

FTC41041

HIGH SPEED 256K x 16 (4 MEG)

STATIC CMOS RAM

AC TEST CONDITIONS

Input Pulse Levels

GND to 3.0V

Input Rise and Fall Times

Input Timing Reference Level

Output Timing Reference Value

Output Load

3ns

1.5V

See Figures 1 & 2

Figure 1. Output Load

Figure 2. Thevenin Equivalent

* including scope and test ﬁxture.

Note:

Becauseoftheultra-highspeedofthe FTC41041,caremustbetakenwhen

testing this device; an inadequate setup can cause a normal functioning

part to be rejected as faulty. Long high-inductance leads that cause

supply bounce must be avoided by bringing the V_CCand ground planes

directly up to the contactor ﬁngers. A 0.01 µF high frequency capacitor

is also required between V_CCand ground. To avoid signal reﬂections,

proper termination must be used; for example, a 50Ω test environment

should be terminated into a 50Ω load with 1.73V (Thevenin Voltage) at

the comparator input, and a 116Ω resistor must be used in series with

D_OUTto match 166Ω (Thevenin Resistance).

TRUTH TABLE

Mode

BLE

BHE

I/O₀- I/O₇

High Z

D_OUT

I/O₈- I/O₁₅

High Z

D_OUT

Power

Standby

Active

Powerdown

Read All Bits

Read Lower Bits Only

Read Upper Bits Only

Write All Bits

D_OUT

High Z

D_OUT

High Z

D_IN

Write Lower Bits Only

Write Upper Bits Only

Selected, Outputs Disabled

D_IN

High Z

D_IN

High Z

2013

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Rev C

FTC41041

HIGH SPEED 256K x 16 (4 MEG)

STATIC CMOS RAM

SOJ SMALL OUTLINE IC PACKAGE

Pkg #

# Pins

44 (400 mil)

Symbol

Min

Max

0.148

0.128

0.082

0.013

0.007

1.120

0.023

0.013

1.130

0.050 BSC

0.435

0.395

0.445

0.405

0.370 BSC

0.025

2013

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Rev C

FTC41041

HIGH SPEED 256K x 16 (4 MEG)

STATIC CMOS RAM

REVISIONS

DOCUMENT NUMBER SRAM 1478

DOCUMENT TITLE

FTC41041 HIGH SPEED 256K X 16 (4 MEG) STATIC CMOS RAM

REV ISSUE DATE

ORIGINATOR DESCRIPTION OF CHANGE

Jan-2007

July-2008

Sept-2009

Nov-2013

New Data Sheet

Added Military processing, lead-free designation

Updated TSOP II Package Drawing

Removed TSOP II Package Drawing

2013

10 of 11

Rev C

FTC41041

HIGH SPEED 256K x 16 (4 MEG)

STATIC CMOS RAM

ORDERING INFORMATION

FTC41041

Device Type

Speed

Package

Processing

Lead-Free

(Blank)

RoHS Compliant

Standard

0°C to +70°C

-40°C to +85°C

-55°C to +125°C

Plastic SOJ, 400 Mil

10, 12, 15, 20 ns

256K x 16 SRAM

2013

8 of 11

Rev C

FTC41041

HIGH SPEED 256K x 16 (4 MEG)

STATIC CMOS RAM

SOJ SMALL OUTLINE IC PACKAGE

Pkg #

# Pins

44 (400 mil)

Symbol

Min

Max

0.148

0.128

0.082

0.013

0.007

1.120

0.023

0.013

1.130

0.050 BSC

0.435

0.395

0.445

0.405

0.370 BSC

0.025

2013

9 of 11

Rev C

FTC41041

HIGH SPEED 256K x 16 (4 MEG)

STATIC CMOS RAM

REVISIONS

DOCUMENT NUMBER SRAM 1478

DOCUMENT TITLE

FTC41041 HIGH SPEED 256K X 16 (4 MEG) STATIC CMOS RAM

REV ISSUE DATE

ORIGINATOR DESCRIPTION OF CHANGE

Jan-2007

July-2008

Sept-2009

Nov-2013

New Data Sheet

Added Military processing, lead-free designation

Updated TSOP II Package Drawing

Removed TSOP II Package Drawing

2013

10 of 11

Rev C

Ashley Crt, Henley,

Marlborough, Wilts, SN8 3RH UK

Tel: +44(0)1264 731200

Fax:+44(0)1264 731444

E-mail

info@forcetechnologies.co.uk

tech@forcetechnologies.co.uk

sales@forcetechnologies.co.uk

www.forcetechnologies.co.uk

Unless otherwise stated in this SCD/Data sheet, Force Technologies Ltd reserve the right to make changes, without notice, in the products, Includ

-ing circuits, cells and/or software, described or contained herein in order to improve design and/or performance. Force Technologies resumes no

responsibility or liability for the use of any of these products, conveys no licence or any title under patent, copyright, or mask work to these

products, and makes no representation or warranties that that these products are free from patent, copyright or mask work infringement, unless

otherwise specified.

Life Support Applications

Force Technologies products are not designed for use in life support appliances, devices or systems where malfunction of a Force Technologies

product can reasonably be expected to result in a personal injury. Force Technologies customers using or selling Force Technologies products

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improper use or sale.

All trademarks acknowledged

2013

11 of 11

Rev C

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