HFBR-57E0PZ-XXX [FOXCONN]
FIBER OPTIC TRANSCEIVER,MODULE;
| 型号： | HFBR-57E0PZ-XXX |
| 厂家： | 
FOXCONN |
| 描述： | FIBER OPTIC TRANSCEIVER,MODULE |
| 文件： | 总17页 (文件大小：338K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HFBR-57E0LZ/ALZ/PZ/APZ
Multimode Small Form Factor PluggableTransceivers with LC
connector for ATM, FDDI, Fast Ethernet and SONET OC-3/SDH STM-1
Datasheet
Description
Features
The HFBR-57E0 Small Form Factor Pluggable LC • RoHScompliant
transceivers provide the system designer with a
• Full compliance with ATM Forum UNI SONET OC-3
product to implement a range of solutions for
multimode fiber Fast Ethernet and SONET OC-3
(SDH STM-1) physical layers for ATM and other
services.
multimode fiber physical layer specification
• Full compliance with the optical performance
requirements of the FDDI PMD Standard
• Full compliance with the optical performance
requirementsof100Base-FXversionofIEEE802.3u
• Industry standard Small Form Pluggable (SFP) package
• LCduplexconnectoropticalinterface
• Operates with 62.5/125 µm and 50/125 µm multimode
fiber
This transceiver operates at a nominal wavelength
of1300nmwithanLCfiberconnectorinterfacewith
an external connector shield (HFBR-57E0).
TransmitterSection
The transmitter section of the HFBR-57E0 utilizes
a 1300 nm InGaAsP LED. This LED is packaged in
the optical subassemblyportionofthe transmitter
section. It is driven by a custom silicon IC which
converts differential PECL logic signals, ECL
referenced (shifted) to a +3.3 V supply, into an
analog LED drive current.
• Single +3.3 V power supply
• +3.3 V TTL LOS output
• Receiveroutputsaresquelchenabled
• Manufactured in an ISO 9001 certified facility
• Temperaturerange:
0 °C to +70° C
-40 °C to +85 °C
HFBR-57E0LZ/PZ:
HFBR-57E0ALZ/APZ:
ReceiverSection
• Bailde-latchoption
The receiver section of the HFBR-57E0 utilizes an
InGaAsPINphotodiodecoupledtoacustomsilicon
transimpedance preamplifier IC. It is packaged in
the optical subassembly portion of the receiver.
Applications
• OC-3 SFP transceivers are designed for ATM LAN and
WAN applications such as:
ATMswitchesandrouters
SONET/SDHswitchinfrastructure
This PIN/preamplifier combination is coupled to a
custom quantizer IC which provides the final pulse
shaping for the logic output and the Loss of Signal • Multimode fiber ATM backbone links
(LOS) function. The data output is differential. The
• FastEthernet
data output is PECL compatible, ECL referenced
(shifted) to a +3.3 V power supply. This circuit also
includes a loss of signal (LOS) detection circuit
which provides an open collector logic high output
in the absence of a usable input optical signal. The
LOS output is +3.3 V TTL.
Loss of Signal
20
19
18
17
16
15
14
13
12
11
VEET
TD-
The Loss of Signal (LOS) output indicates that the
optical input signal to the receiver does not meet
the minimum detectablelevel for FDDI and OC-3
compliantsignals.WhenLOSishighitindicatesloss
of signal. When LOS is low it indicates normal
operation. The LOS thresholds are set to indicate a
definiteopticalfaulthasoccurred(e.g.,disconnected
or broken fiber connection to receiver, failed
transmitter).
1
2
VEET
NC**
TD+
VEET
3
Tx Disable
MOD-DEF(2)
MOD-DEF(1)
MOD-DEF(0)
NC
4
VCCT
5
VCCR
6
VEER
RD+
RD-
7
8
LOS
ModulePackage
The transceiver meets the Small Form Pluggable
(SFP) industry standard package utilizing an
integralLCduplexopticalinterfaceconnector. The
hot-pluggable capability of the SFP package allows
the module to be installed at any time – even with
the host system operating and on-line. This allows
for system configuration changes or maintenance
without system down time. The HFBR-57E0 uses a
reliable 1300 nm LED source and requires a 3.3 V
dc power supply for optimal design.
9
VEER
VEER
10
VEER
BOTTOM OF BOARD
TOP OF BOARD
(AS VIEWED THROUGH TOP OF BOARD)
** Connect to Internal Ground.
Figure 2. Connection diagram of module printed circuit board.
host equipment is operating or not. The module is
simply inserted, electrical interface first, under
fingerpressure.Controlledhot-pluggingisensured
by design and by 3-stage pin sequencing at the
electrical interface. The module housing makes
initial contact with the host board EMI shield
mitigating potential damage due to Electro-Static
Discharge(ESD).The3-stagepincontactsequencing
involves (1) Ground, (2) Power, and then (3) Signal
pins, making contact with the host board surface
mount connector in that order. This printed circuit
board card-edge connector is depicted in Figure 2.
ModuleDiagrams
Figure1illustratesthemajorfunctionalcomponents
of the HFBR-57E0. The connection diagram of the
moduleisshowninFigure2. Figures5and7depict
the external configuration and dimensions of the
module.
Installation
TheHFBR-57E0canbeinstalledinorremovedfrom
any MultiSource Agreement (MSA) – compliant
SmallFormPluggableportregardlessofwhetherthe
OPTICAL INTERFACE
RECEIVER
ELECTRICAL INTERFACE
RD+ (Receive Data)
Amplification &
Quantizattion
Light from Fiber
Photodetector
RD- (Receive Data)
Loss of Signal
TRANSMITTER
TD+ (Transmit Data)
TD- (Transmit Data)
Light to Fiber
LED
LED DRIVER
TX Disable
MOD-DEF2
MOD-DEF1
MOD-DEF0
EEPROM
Figure 1. Transceiver functional diagram
2
SerialIdentification(EEPROM)
ElectrostaticDischarge(ESD)
TheHFBR-57E0complieswiththeindustrystandard TherearetwoconditionsinwhichimmunitytoESD
MSA that defines the serial identification protocol. damage is important. Table 1 documents our
Thisprotocolusesthe2-wireserialCMOSE2PROM immunity to both of these conditions. The first
protocol of the ATMEL AT24C01A or equivalent. conditionisduringhandlingofthetransceiverprior
The contents of the HFBR-57E0 serial ID memory toinsertionintothetransceiverport.Toprotectthe
are defined in Table 3 as specified in the SFP MSA. transceiver, it is important to use normal ESD
handling precautions.
FunctionalDataI/O
The HFBR-57E0 fiberoptic transceiver is designed These precautions include using grounded wrist
to accept industry standard differential signals. In straps, workbenches, and floor mats in ESD
order to reduce the number of passive components controlled areas. The ESD sensitivity of the HFBR-
required on the customer’s board, Avago has 57E0iscompatiblewithtypicalindustryproduction
included the functionality of the transmitter bias environments. The second condition is static
resistorsandcouplingcapacitorswithinthefiberoptic discharges to the exterior of the host equipment
module. The transceiver is compatible with an “ac- chassis after installation. To the extent that the
coupled”configurationandisinternallyterminated. duplexLCopticalinterfaceisexposedtotheoutside
Figure 5 depicts the functional diagram of the of the host equipment chassis, it may be subject to
HFBR-57E0.
system-levelESDrequirements.TheESDperformance
oftheHFBR-57E0exceedstypicalindustrystandards.
RegulatoryCompliance
See Table 1 for transceiver Regulatory Compliance Immunity
performance. The overall equipment design will EquipmenthostingtheHFBR-57E0moduleswillbe
determine the certification level. The transceiver subjectedtoradio-frequencyelectromagneticfields
performanceisofferedasafigureofmerittoassist insomeenvironments.Thesetransceivershavegood
the designer.
immunitytosuchfieldsduetotheirshieldeddesign.
Table1. RegulatoryCompliance
Feature
Test Method
Performance
Electrostatic Discharge (ESD)
to the Electrical Pins
MIL-STD-883C
Meets Class 2 (2000 to 3999 Volts).
Withstand up to 2200 V applied between electrical pins.
Electrostatic Discharge (ESD)
to the Duplex LC Receptacle
Variation of IEC 61000-4-2
Typically withstand at least 25 kV without damage when
the LC connector receptacle is contacted by a Human
Body Model probe.
Electromagnetic Interference (EMI)
FCC Class B
System margins are dependent on customer board and
chassis design.
CENELEC CEN55022
Class B (CISPR 21)
VCCI Class 1
Immunity
Variation of IEC 61000-4-3
Typically shows a negligible effect from a 10 V/m field
swept from 80 to 450 MHz applied to the transceiver
without a chassis enclosure.
Eye Safety
AEL Class 1
EN60825-1 (+A11)
Compliant per Avago testing under single fault conditions.
TUV Certification: R 72042022
Component Recognition
Underwriters Laboratories and Canadian
Standard Associations Joint Component
Recognition for Information Technology
Equipment Including Electrical Business
Equipment
UL File#: E173874
3
ElectromagneticInterference(EMI)
OrderingInformation
Most equipment designs utilizing these high-speed The HFBR-57E0 1300 nm product is available for
transceiversfromAvagowillberequiredtomeetthe production orders through the Avago Component
requirementsofFCCintheUnitedStates,CENELEC Field Sales Offices and Authorized Distributors
EN55022 (CISPR 22) in Europe and VCCI in Japan. worldwide.
ThemetalhousingandshieldeddesignoftheHFBR- For technical information regarding this product,
57E0 minimize the EMI challenge facing the host pleasevisittheAvagowebsiteatwww.avagotech.com.
equipment designer. These transceivers provide
Use the quick search feature to search for this part
superior EMI performance. This greatly assists the
number. You may also contact the Avago Products
designer in the management of the overall system
Customer Response Centre.
EMI performance.
ApplicationsSupportMaterials
Eye Safety
Contact your local Avago Component Field Sales
These transceivers provide Class 1 eye safety by
OfficeforinformationonhowtoobtainPCBlayouts
design. Avago has tested the transceiver design for
and evaluation boards for the transceivers.
compliance with the requirements listed in Table 1
200
under normal operating conditions and under a
single fault condition.
3.0
180
1.0
Flammability
The HFBR-57E0 transceiver housing is made of
160
1.5
metal and high strength, heat resistant, chemically
resistant, and UL 94V-0 flame retardant plastic.
140
2.0
tr/f – TRANSMITTER
2.5
ShippingContainer
OUTPUT OPTICAL RISE/
120
FALL TIMES – ns
Thetransceiverispackagedinashippingcontainer
designed to protect it from mechanical and ESD
damage during shipment or storage.
3.0
100
1260
1280
1300
1320
1340
1360
λ
C – TRANSMITTER OUTPUT OPTICAL RISE/FALL
TIMES – ns
TransceiverOpticalPowerBudgetversusLinkLength
OpticalPowerBudget(OPB)istheavailableoptical
power for a fiberoptic link to accommodate fiber
cable loses plus losses due to in-line connectors,
splices, optical switches, and to provide margin for
link aging and unplanned losses due to cable plant
reconfiguration or repair.
HFBR-57E0 TRANSMITTER TEST RESULTS
OF λ , ∆λ AND tr/f ARE CORRELATED AND COMPLY
C
WITH THE ALLOWED SPECTRAL WIDTH AS A FUNCTION
OF CENTER WAVELENGTH FOR VARIOUS RISE AND
FALL TIMES.
Figure 3. Transmitter Output Optical Spectral Width (FWHM) vs.
Transmitter Output Optical Center Wavelength and Rise/Fall Times
6
5
4
3
2
1
0
Avago LED technology has produced 1300 nm LED
devices with lower aging characteristics than
normally associated with these technologies in the
industry. The industry convention is 1.5 db aging
for 1300 nm LEDs. The 1300 nm Avago LEDs are
specified to experience less than 1 db of aging over
normalcommercialequipmentmissionlifeperiods.
ContactyourAvagosalesrepresentativeforadditional
details.
-3
-2
-1
0
1
2
3
EYE SAMPLING TIME POSITION (ns)
CONDITIONS:
1. TA = +25 C
2. VCC= 3.3 V dc
3. INPUT OPTICAL RISE/FALL TIMES = 1.0/2.1 ns.
4. INPUT OPTICAL POWER IS NORMALIZED TO
CENTER OF DATA SYMBOL.
5. NOTE 13 AND 14 APPLY.
Figure 4. Relative Input Optical Power vs. Eye Sampling Time Position
4
1 µH
1 µH
3.3 V
10 µF
0.1 µF
0.1 µF
3.3 V
VccT
4.7 K to 10 K
HFBR-57E0
Tx Dis
3.3 V
82
82
0.1 µF
TD+
50
50
SO+
LED DRIVER
& SAFETY
CIRCUITRY
TD–
SO–
TX GND
0.1 µF
130
VccR
130 W
3.3 V
4.7 K to 10 K
SerDes
0.1
µF
PROTOCOL
IC
10 µF
130
130
0.1 µF
RD+
50
50
SI+
SI–
AMPLIFICATION
RD–
&
QUANTIZATION
0.1 µF
82
Rx_LOS
RX GND
Rx_LOS
82
MOD_DEF2
MOD_DEF1
MOD_DEF0
GPIO(X)
GPIO(X)
GP14
EEPROM
4.7 K to 4.7 K to
10 K 10 K
4.7 K to
10 K
3.3 V
Figure 5. Recommended application configuration
1 µH
1 µH
VCC
T
0.1 µF
0.1 µF
VCCR
3.3 V
10 µF
0.1 µF
10 µF
SFP MODULE
HOST BOARD
Note: Inductors must have less than 1 ohm series resistance per MSA.
Figure 6. MSA required power supply filter
5
Table 2. Pin Description
Pin
Name
Function/Description
MSA Notes
1
VEET
Transmitter Ground
2
NC
NC
1
3
Tx Disable
MOD-DEF2
MOD-DEF1
MOD-DEF0
NC
Transmitter Disable- Module disables on high or open
Module Definition 2 - Two Wire Serial ID Interface
Module Definition 1 - Two Wire Serial ID Interface
Module Definition 0 - grounded in module
NC
4
2
2
2
5
6
7
8
LOS
Loss of Signal - high indicates loss of signal
Receiver Ground
3
9
VEER
10
11
12
13
14
15
16
17
18
19
20
VEER
Receiver Ground
VEER
Receiver Ground
RD-
Inverse Received Data Out
Received Data Out
4
4
RD+
VEER
Receiver Ground
V
V
CCR
Receiver Power -3.3 V 10%
Transmitter Power -3.3 V 10%
Transmitter Ground
5
5
CCT
VEET
TD+
TD-
Transmitter Data In
6
6
Inverse Transmitter Data In
Transmitter Ground
VEET
Notes:
1. Pin2connectedtointernalground.
2. Mod-Def 0, 1, 2. are the module definition pins. They should be pulled up with a 4.7 K - 10 KW resistor on the host board to a supply less than V T +0.3
CC
V or V R +0.3 V.
CC
Mod-Def 0 is grounded by the module to indicate that the module is present.
Mod-Def 1 is clock line of two wire serial interface for optional serial ID.
Mod-Def 2 is data line of two wire serial interface for optional serial ID.
3. LOS (Loss of Signal) is an open collector/drain output which should be pulled up externally with a 4.7 - 10 KW resistor on the host board to a supply <
V
T, R +0.3 V. When high, this output indicates the received optical power is below the worst case receiver sensitivity (as defined by the standard in
CC
use). Low indicates normal operation. In the low state, the output will be pulled to <0.8 V.
4. RD-/+: These are the differential receiver outputs. They are ac coupled 100 W differential lines which should be terminated with 100 W differential at
the SERDES. The ac coupling is done inside the module and is thus not required on the host board. The voltage swing on these lines will be between
400 and 2000 mV differential (200 - 1000 mV single ended) when properly terminated.
5.
V R and V T are the receiver and transmitter power supplies. They are defined as 2.97 - 3.63 V at the SFP connector pin. The maximum supply
CC CC
current is 230 mA and the associated in-rush current will typically be no more than 30 mA above steady state after 500 nanoseconds.
6. TD-/+: These are the differential transmitter inputs. They are ac coupled differential lines with 100Wdifferential termination inside the module. The
ac coupling is done inside the module and is thus not required on the host board. The inputs will accept differential swings of 400 - 2000 mV
(200 - 1000 mV single ended), though it is recommended that values between 400 and 1200 mV differential (200 - 600 mV single ended) be used for
best EMI performance. These levels are compatible with CML and LVPECL voltage swings.
6
Table 3. EEPROM Serial ID Memory Contents
Add
Hex
ASCII
Add
Hex
ASCII
Add
Hex
ASCII
Add
Hex
ASCII
0
1
2
3
4
5
03
04
07
00
00
40
41
42
43
44
45
48
46
42
52
2D
35
H
F
68
69
70
71
72
73
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
96
Note 5
Note 5
Note 5
Note 5
Note 5
Note 5
97
B
R
-
98
99
100
101
01
5
Note 6
6
20
46
37
7
74
Note 1
102
Note 5
Note 6
7
8
9
00
00
00
47
48
49
45
30
E
0
75
76
77
Note 1
Note 1
Note 1
103
104
105
Note 5
Note 5
Note 5
41
A
Note 4
10
11
12
13
00
50
51
52
53
50
Note 4
P
Z
78
79
80
81
Note 1
Note 1
Note 1
Note 1
106
107
108
109
Note 5
Note 5
Note 5
Note 5
03
Note 7
5A
Note 4
02
Note 8
20
Note 4
00
20
Note 4
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
00
00
C8
C8
00
00
41
47
49
4C
45
4E
54
20
20
20
20
20
20
20
54
55
56
57
58
59
60
61
62
63
64
65
66
67
20
82
83
84
85
86
87
88
89
90
91
92
93
94
95
Note 1
Note 1
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
00
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
Note 5
Note 5
Note 5
Note 5
Note 5
Note 5
Note 5
Note 5
Note 5
Note 5
Note 5
Note 5
Note 5
Note 5
Note 5
Note 5
Note 5
Note 5
20
30
0
0
0
0
30
30
30
A
G
I
05
1E
00
L
Note 3
00
E
N
T
12
00
00
00
00
Note 3
7
Table 3. EEPROM Serial ID Memory Contents (continued)
Add
34
Hex
20
ASCII
Add
Hex
ASCII
Add
Hex
ASCII
Add
Hex
ASCII
35
20
36
00
37
00
38
30
39
D3
Notes:
1. Addresses 68 - 83 specify a unique identifier.
2. Addresses 84 - 91 specify the date code.
3. Addresses 63 and 95 are check sums. Address 63 is the check sum for bytes 0 - 62 and address 95 is the check sum for bytes 64 - 94.
4. Part number options LZ, PZ, ALZ, APZ, etc. Example: for "AP" option, hexes in addresses 49, 50, 51, 52 and 52 will be 41, 50, 5A, 20 and 20
respectively.
5. Addresses 96-127 are vendor specific data.
6. Addresses 5 and 6 specify compliance code. Address 5 with Hex 01 for OC-3 and address 6 with Hex 20 for Fast Ethernet.
7. Address 11 specifies encoding code. Hex 03 for OC-3 and Hex 02 for Fast Ethernet.
8. Address 12 specifies bit rate. Hex 02 for OC-3 and Hex 01 for Fast Ethernet.
8
AGILENT HFBR-57E0xxZ
YYWW
Country of Origin
Tcase Reference Point
13.8 0.1
[0.541 0.004ꢀ
13.4 0.1
[0.528 0.004ꢀ
DEVICE SHOWN WITH
DUST CAP AND BAIL
WIRE DELATCH
2.60
[0.10ꢀ
55.2 0.2
[2.17 0.01ꢀ
FRONT EDGE OF SFP
TRANSCEIVER CAGE
0.7MAX. UNCOMPRESSED
[0.028ꢀ
6.25 0.05
[0.246 0.002ꢀ
13.0 0.2
[0.512 0.008ꢀ
8.5 0.1
[0.335 0.004ꢀ
TX
RX
AREA
FOR
PROCESS
PLUG
DIMENSIONS ARE IN MILLIMETERS (INCHES)
6.6
[0.261ꢀ
13.50
[0.53ꢀ
14.8MAX. UNCOMPRESSED
[0.583ꢀ
Figure 7. Module Drawing
9
X
Y
34.5
10
3x
7.2
7.1
10x ∅1.05 0.01
∅
0.1 L X A
S
2.5
∅ 0.85 0.05
16.25
MIN. PITCH
1
∅
Y
0.1 S X
1
2.5
B
A
PCB
EDGE
3.68
5.68
20
PIN 1
8.58
8.48
2x 1.7
11.08
14.25
11.93
16.25
REF .
9.6
4.8
11
10
SEE DET AIL 1
9x 0.95
0.05
2.0
11x
∅
0.1 L X A S
11x 2.0
5
26.8
2
10
3x
3
41.3
42.3
5
3.2
20x 0.5
0.03
0.9
0.06 L A S B S
LEGEND
20
PIN 1
10.53
10.93
1. PADS AND VIAS ARE CHASSIS GROUND
2. THR OUGH HOLES, PLATING OPTIONAL
11.93
9.6
0.8
TYP .
11
10
3. HATCHED AREA DENOTES COMPONENT
AND TRACE KEEPOUT (EXCEPT
CHASSIS GROUND)
4
4. AREA DENOTES COMPONENT
KEEPOUT (TRACES ALLOWED)
2
0.005 TYP .
0.06 A S B S
2x 1.55
0.05
L
∅ 0.1 L A S B S
DET AIL 1
DIMENSIONS ARE IN MILLIMETERS
Figure 8. SFP host board mechanical layout
10
1.7 0.9
[.07 .04ꢀ
3.5 0.3
[.14 .01ꢀ
41.73 0.5
[1.64 .02ꢀ
PCB
AREA
FOR
BEZEL
PROCESS
PLUG
15MAX
.59
Tcase REFERENCE POINT
CAGE
ASSEMBLY
15.25 0.1
[.60 0.004ꢀ
10.4 0.1
[.41 0.004ꢀ
12.4REF
.49
10REF
1.15REF
9.8MAX
.39
.39
TO PCB
.05
BELOW PCB
16.25 0.1MIN PITCH
[.64 0.004ꢀ
0.4 0.1
[.02 0.004ꢀ
BELOW PCB
MSA-SPECIFIED BEZEL
DIMENSIONS ARE IN MILLIMETERS [INCHESꢀ.
Figure 9. SFP Assembly Drawing
11
AbsoluteMaximumRatings
Stresses in excess of the absolute maximum ratings can cause catastrophic damage to the device. Limits apply to each
parameter in isolation, all other parameters having values within the recommended operating conditions. It should not be
assumed that limiting values of more than one parameter can be applied to the product at the same time. Exposure to the
absolute maximum ratings for extended periods can adversely affect device reliability.
Parameter
Symbol
Minimum
Typical
Maximum Units
Notes
Storage Temperature
TS
-40
+100
3.63
VCC
°C
Supply Voltage
VCC
VI
-0.5
-0.5
V
Data Input Voltage
Differential Input Voltage (p-p)
Output Current
V
VD
IO
2.4
V
1
50
mA
RecommendedOperatingConditions
Parameter
Symbol
Minimum
Typical
Maximum Units
Notes
Case Operating Temperature
HFBR-57E0LZ/PZ
TC
0
+70
+85
3.63
°C
°C
V
HFBR-57E0ALZ/APZ
TC
-40
2.97
Supply Voltage
VCC
3.3
0.8
Data Input: Transmitter Differential Input Voltage VI
(TD+/-)
0.5
2.4
V
W
Data and Loss of Signal Output Load
RL
50
2
TransmitterElectricalCharacteristics
HFBR-57E0LZ/PZ (T = 0 ºC to +70 ºC, V = 2.97 V to 3.63 V)
C
CC
HFBR-57E0ALZ/APZ (T = -40 ºC to +85 ºC, V = 2.97 V to 3.63 V)
C
CC
Parameter
Symbol
Minimum
Typical
Maximum Units
Notes
Supply Current
ICC
165
210
0.80
3.5
0.8
mA
W
V
3
Power Dissipation
PDISS
VIH
0.55
5a
Transmitter Disable (TX Disable) High
Transmitter Disable (TX Disable) Low
2.0
0
VIL
V
12
ReceiverElectricalCharacteristics
HFBR-57E0LZ/PZ (T = 0 ºC to +70 ºC, V = 2.97 V to 3.63 V)
C
CC
HFBR-57E0ALZ/APZ (T = -40 ºC to +85 ºC, V = 2.97 V to 3.63 V)
C
CC
Parameter
Symbol
Minimum
Typical
Maximum Units
Notes
Supply Current
ICC
95
150
0.55
2.0
mA
W
V
4
Power Dissipation
PDISS
0.35
5b
Data Output: Receiver Differential Output Voltage VO
(RD+/-)
Data Output Rise Time
0.4
6a
6b
7
tr
0.35
0.35
2.2
2.2
0.8
ns
ns
V
Data Output Fall Time
tf
7
Loss of Signal Output Voltage - Low
Loss of Signal Output Voltage - High
Power Supply Noise Rejection
LOSVOL
LOSVOH
PSNR
6a
6a
2.0
V
50
mV
TransmitterOpticalCharacteristics
HFBR-57E0LZ/PZ(T = 0 ºC to +70 ºC, V = 2.97 V to 3.63 V)
C
CC
HFBR-57E0ALZ/APZ (T = -40 ºC to +85 ºC, V = 2.97 V to 3.63 V)
C
CC
Parameter
Output Optical Power
Symbol
PO
Minimum
-19
Typical
-15.7
Maximum Units
Notes
8
BOL
-14
dBm avg
62.5/125 µm, NA = 0.275 Fiber EOL
-20
Output Optical Power
BOL
EOL
PO
-22.5
-14
dBm avg
8
50/125 µm, NA = 0.20 Fiber
Transmitter Disable (High)
-23.5
PO(off)
lC
-45
dBm
nm
Center Wavelength
1270
1308
1380
21, Figure 3
Dl
Spectral Width - FWHM
Spectral Width - RMS
Optical Rise Time
147
63
nm
9, 21
Figure 3
10, 21
tr
tf
0.6
0.6
1.2
3.0
3.0
ns
ns
Figure 3
10, 21
Optical Fall Time
2.0
Figure 3
Systematic Jitter Contributed by the Transmitter
OC-3
SJ
0.25
0.20
0.07
1.2
0.6
0.6
ns p-p
ns p-p
ns p-p
ns p-p
11a
11b
11c
Duty Cycle Distortion Contributed by the Transmitter
FE
DCD
DDJ
RJ
Data Dependen t Jitter Contributed by the
Transmitter FE
Random Jitter Contributed by the Transmitter
OC-3
FE
0.10
0.10
0.52
0.69
12a
12b
13
ReceiverOpticalandElectricalCharacteristics
HFBR-57E0LZ /PZ(T = 0 ºC to +70 ºC, V = 2.97 V to 3.63 V)
C
CC
HFBR-57E0ALZ/APZ (T = -40 ºC to +85 ºC, V = 2.97 V to 3.63 V)
C
CC
Parameter
Symbol
Minimum
Typical
Maximum Units
Notes
Input Optical Power minimum at Window Edge
OC-3
PIN MIN (W)
-30
-31
dBm avg
13a, Figure 4
13b
FE
Input Optical Power at Eye Center
OC-3
PIN MIN (C)
-31
dBm avg
14a, Figure 4
14b
FE
-31.8
Input Optical Power Maximum
OC-3
PIN MAX
-14
dBm avg
nm
13a
13b
FE
-14
1270
l
Operating Wavelength
1380
Systematic Jitter Contributed by the Receiver
OC-3
SJ
0.11
0.08
0.02
1.2
0.4
1.0
ns p-p
ns p-p
ns p-p
ns p-p
15a
15b
15c
Duty Cycle Distortion Contributed by the Receiver
FE
DCD
DDJ
RJ
Data Dependent Jitter Contributed by the Receiver
FE
Random Jitter Contributed by the Receiver
OC-3
0.14
0.14
1.91
2.14
16a
16b
FE
Loss of Signal - Deasserted
OC-3
PA
PD + 1.5 dB
-31
-33
dBm avg
17
18
FE
Loss of Signal - Asserted
PD
-45
1.5
0
dBm avg
Loss of Signal - Hysteresis
PA - PD
dB
µs
µs
Loss of Signal Deassert Time (on to off)
Loss of Signal Assert Time (off to on)
2
5
100
350
19
20
0
14
Notes:
13a. This specification is intended to indicate the performance of the receiver
sectionofthetransceiverwhenInputOpticalPowersignalcharacteristics
arepresentperthefollowingdefinitions.TheInputOpticalPowerdynamic
rangefromtheminimumlevel(withawindowtime-width)tothemaximum
level is the range over which the receiver is guaranteed to provide output
1. This is the maximum voltage that can be applied across the Differential
Transmitter Data Inputs to prevent damage to the input ESD protection
circuit.
2. The data outputs are terminated with 50W.
The Loss of Signal output is terminated with 50 W connected to a pull-up
-10.
data with a Bit Error Rate (BER) better than or equal to 1 x 10
resistor of 4.7 KW tied to V
.
-
-
-
At the Beginning of Life (BOL)
CC
3. Thepowersupplycurrentneededtooperatethetransmitterisprovidedto
differentialECLcircuitry.Thiscircuitrymaintainsanearlyconstantcurrent
flow from the power supply. Constant current operation helps to prevent
unwantedelectricalnoisefrombeinggeneratedandconductedoremitted
toneighboringcircuitry.
4. This is the receiver supply current measured in mA.
5a. The power dissipation of the transmitter is calculated as the sum of the
products of supply voltage and current.
5b. The power dissipation of the receiver is calculated as the sum of the
products of supply voltage and currents, minus the sum of the products
oftheoutputvoltagesandcurrents.
6a. DifferentialOutputVoltageisinternallyaccoupled. TheLossofSignallow
andhighvoltagesaremeasuredwithloadconditionasmentionedinnote
2.
6b. Data and Data-bar outputs are squelched at LOS assert level. When the
receivedlight dropsbelowLOSassertpoint,itwillforcereceiverdataand
data-bar to go to steady PECL levels High and Low respectively.
7. The data output rise and fall times are measured between 20% and 80%
levels.
Over the specified operating temperature and voltage ranges
23
Input is a 155.52 MBd, 2 -1 PRBS data pattern with 72 “1” s and 72
“0”s inserted per the CCITT (now ITU-T) recommendation G.958
Appendix I.
-
-
Receiver data window time-width is 1.23 ns or greater for the clock
recoverycircuittooperatein.Theactualtestdatawindowtime-widthis
settosimulatetheeffectofworstcaseopticalinputjitterbasedonthe
transmitterjittervaluesfromthespecificationtables.Thetestwindow
time-width is 3.32 ns.
Transmitteroperatingwitha155.52MBd,77.5MHzsquare-wave,input
signal to simulate any cross-talk present between the transmitter and
receiver sections of the transceiver.
13b. This specification is intended to indicate the performance of the receiver
sectionofthetransceiverwhenInputOpticalPowersignalcharacteristics
arepresentperthefollowingdefinitions.TheInputOpticalPowerdynamic
rangefromtheminimumlevel(withawindowtime-width)tothemaximum
level is the range over which the receiver is guaranteed to provide output
data with a Bit Error Rate (BER) better than or equal to 2.5 x 10
• At the Beginning of Life (BOL)
-10
.
8. Theseopticalpowervaluesaremeasuredwiththefollowingconditions:
The Beginning of Life (BOL) to the End of Life (EOL) optical power
degradation is typically 1.5 dB per the industry convention for long
wavelength LEDs. The actual degradation observed in Avago’s 1300 nm
LED products is < 1 dB, as specified in this data sheet. Over the specified
operating voltage and temperature ranges. With 25 MBd (12.5 MHz
square-wave),inputsignal.
• Over the specified operating temperature and voltage ranges
• Input symbol pattern is the FDDI test pattern defined in FDDI PMD
Annex A.5 with 4B/5B NRZI encoded data that contains a duty cycle
base-linewandereffectof50 kHz. Thissequencecausesanearworst
caseconditionforinter-symbolinterference.
• Receiver data window time-width is 2.13 ns or greater and centered at
mid-symbol.Thisworstcasewindowtime-widthistheminimumallowed
eye-opening presented to the FDDI PHY PM_Data indication input
(PHY input) per the example in FDDI PMD Annex E. This minimum
windowtime-widthof2.13nsisbasedupontheworstcaseFDDIPMD
ActiveInputInterfaceopticalconditionsforpeak-to-peakDCD(1.0ns),
DDJ (1.2 ns) and RJ (0.76 ns) presented to the receiver.
Attheendofonemeterofnotedopticalfiberwithcladdingmodesremoved.
The average power value can be converted to a peak power value by
adding 3 dB. Higher output optical power transmitters are available on
specialrequest.PleaseconsultwithyourlocalAvagosalesrepresentative
forfurtherdetails.
9. The relationship between Full Width Half Maximum and RMS values for
Spectral Width is derived from the assumption of a Gaussian shaped
spectrum which results in a 2.35 X RMS = FWHM relationship.
10. The optical rise and fall times are measured from 10% to 90% when the
transmitter is driven by a 25 MBd (12.5 MHz square-wave) input signal.
TheANSIT1E1.2committeehasdesignatedthepossibilityofdefiningan
eye pattern mask for the transmitter optical output as an item for further
study. Avago will incorporate this requirement into the specifications for
these products if it is defined. The HFBR-57E0 products typically comply
withthetemplaterequirementsofCCITT(nowITU-T)G.957Section3.2.5,
Figure 2 for the STM- 1 rate, excluding the optical receiver filter normally
associated with single mode fiber measurements which is the likely
source for the ANSI T1E1.2 committee to follow in this matter.
11a. Systematic Jitter contributed by the transmitter is defined as the
combinationofDutyCycleDistortionandDataDependentJitter.Systematic
Jitterismeasuredat50% thresholdusinga155.52MBd(77.5MHzsquare-
To test a receiver with the worst case FDDI PMD Active Input jitter
condition requires exacting control over DCD, DDJ and RJ jitter compo-
nents that is difficult to implement with production test equipment. The
receivercanbeequivalentlytestedtotheworstcaseFDDIPMDinputjitter
conditionsandmeettheminimumoutputdatawindowtime-widthof2.13
ns. This is accomplished by using a nearly ideal input optical signal (no
DCD, insignificant DDJ and RJ) and measuring for a wider window time-
width of 4.6 ns. This is possible due to the cumulative effect of jitter
componentsthroughtheirsuperposition(DCDandDDJaredirectlyadditive
and RJ components are rms additive). Specifically, when a nearly ideal
input optical test signal is used and the maximum receiver peak-to-peak
jittercontributionsofDCD(0.4ns),DDJ(1.0ns),andRJ(2.14ns)exist,the
minimum window time-width becomes 8.0 ns -0.4 ns - 1.0 ns - 2.14 ns =
4.46 ns, or conservatively 4.6 ns. This wider window time-width of 4.6 ns
guarantees the FDDI PMD Annex E minimum window time-width of 2.13
ns under worst case input jitter conditions to the Avago receiver.
• Transmitter operating with an IDLE Line State pattern, 125 MBd (62.5
MHz square-wave), input signal to simulate any cross-talk present
between the transmitter and receiver sections of the transceiver.
14a. All conditions of Note 13a apply except that the measurement is made at
the center of the symbol with no window time- width.
23
wave), 2 - 1 psuedorandom data pattern input signal.
11b. Duty Cycle Distortion contributed by the transmitter is measured at the
50% threshold of the optical output signal using an IDLE Line State, 125
MBd (62.5 MHz square-wave), input signal.
11c. DataDependentJittercontributedbythetransmitterisspecifiedwiththe
FDDI test pattern described in FDDI PMD Annex A.5.
12a. Random Jitter contributed by the transmitter is specified with a 155.52
MBd (77.5 MHz square-wave) input signal.
12b. RandomJittercontributedbythetransmitterisspecifiedwithanIDLELine
State, 125 MBd (62.5 MHz square-wave) input signal. See Application
Information-TransceiverJitterPerformanceSectionofthisdatasheetfor
furtherdetails.
14b. All conditions of Note 13b apply except that the measurement is made at
the center of the symbol with no window time-width.
15a. SystematicJittercontributedbythereceiverisdefinedasthecombination
of Duty Cycle Distortion and Data Dependent Jitter. Systematic Jitter is
measuredat50% thresholdusinga155.52MBd(77.5MHzsquare-wave),
23
2
-1psuedorandomdatapatterninputsignal.
15
15b Duty Cycle Distortion contributed by the receiver is measured at the 50%
thresholdoftheelectricaloutputsignalusinganIDLELineState,125MBd
(62.5MHzsquare-wave), inputsignal. Theinputopticalpowerlevelis-20
dBm average.
15c. Data Dependent Jitter contributed by the receiver is specified with the
FDDI DDJ test pattern described in the FDDI PMD Annex A.5. The input
optical power level is -20 dBm average.
16a. Random Jitter contributed by the receiver is specified with a 155.52 MBd
(77.5 MHz square- wave) input signal.
16b. Random Jitter contributed by the receiver is specified with an IDLE Line
State, 125 MBd (62.5 MHz square-wave), input signal. The input optical
power level is at maximum “P
(W)”. See Application Information -
IN MIN
TransceiverJitterSectionforfurtherinformation.
17. Thisvalueismeasuredduringthetransitionfromlowtohighlevelsofinput
opticalpower.
18. Thisvalueismeasuredduringthetransitionfromhightolowlevelsofinput
opticalpower. AtLossofSignalassert, thereceiveroutputsDataOutand
Data Out Bar go to steady PECL levels High and Low respectively.
19. The Loss of Signal output shall be de-asserted within 100 µs after a step
increase of the Input Optical Power.
20. LossofSignaloutputshallbeassertedwithin350µsafterastepdecrease
in the Input Optical Power. At Loss of Signal Assert, the receiver outputs
Data Out and Data Out Bar go to steady PECL levels High and Low
respectively.
21. TheHFBR-57E0transceivercomplieswiththerequirementsforthetrade-
offsbetweencenterwavelength,spectralwidth,andrise/falltimesshown
in Figure 3. This figure is derived from the FDDI PMD standard (ISO/IEC
9314-3 : 1990 and ANSI X3.166 - 1990) per the description in ANSI T1E1.2
Revision 3. The interpretation of this figure is that values of Center
Wavelength and Spectral Width must lie along the appropriate Optical
Rise/Fall Time curve.
OrderingInformation
1300 nm LED (Operating Case Temperature 0 to +70 °C)
HFBR-57E0LZ
HFBR-57E0PZ
Standard de-latch
Bail de-latch
1300 nm LED (Operating Case Temperature -40 °C to +85 °C)
HFBR-57E0ALZ
HFBR-57E0APZ
Standard de-latch
Bail de-latch
EEPROMcontentsand/orlabeloptions
HFBR-57E0LZ-YYY
HFBR-57E0PZ-YYY
Standard de-latch, 0 to +70°C
Bail de-latch, 0 to +70°C
HFBR-57E0ALZ-YYY Standard de-latch, -40°C to +85°C
HFBR-57E0APZ-YYY Bail de-latch, -40°C to +85°C
Where "YYY" is customer specific.
HandlingPrecaution
The HFBR-57E0xxZ is a pluggable module and is NOT designed for aqueous wash, IR reflow or
wave soldering processes.
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Pte. in the United States and other countries.
Data subject to change. Copyright © 2006 Avago Technologies Pte. All rights reserved.
5989-4773EN - January 25, 2006
相关型号：
HFBR-57E0PZ-YYY
Multimode Small Form Factor Pluggable Transceivers with LC connector for ATM, FDDI, Fast Ethernet
AVAGO
HFBR-57E5APZ
Multimode Small Form-Factor Pluggable Transceivers with LC connector and DMI for ATM, FDDI, Fast Ethernet and SONET OC-3/SDH STM-1
AVAGO
HFBR-57E5APZ
Transceiver, 1270nm Min, 1380nm Max, LC Connector, Surface Mount, ROHS COMPLIANT PACKAGE
FOXCONN
HFBR-57L5AP
Digital Diagnostic SFP 850 nm Transceiver for Fibre Channel 1.0625 Gb/s and Ethernet 1.25 Gb/s
AVAGO
HFBR-57M5AP
FIBER OPTIC TRANSCEIVER, 830-860nm, 2125Mbps(Tx), 2125Mbps(Rx), PANEL MOUNT, LC CONNECTOR, METAL, PACKAGE-20
AVAGO
HFBR-5803AT
FDDI 100 Mb/s ATM and Fast Ethernet Transceivers in Low Cost 1 x 9 Package Style
AGILENT
©2020 ICPDF网 联系我们和版权申明