AOL1401 [FREESCALE]

P-Channel Enhancement Mode Field; P沟道增强型场
AOL1401
型号: AOL1401
厂家: Freescale    Freescale
描述:

P-Channel Enhancement Mode Field
P沟道增强型场

文件: 总6页 (文件大小:443K)
中文:  中文翻译
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AOL1401  
P-Channel Enhancement Mode Field  
Effect Transistor  
General Description  
provide excellent RDS(ON), and ultra-low low gate  
The AOL1401 uses advanced trench technology to  
charge with a 25V gate rating. This device is suitable  
ESD protected.  
for use as a load switch or in PWM applications. It is  
Features  
VDS (V) = -38V  
ID = -85A  
R
DS(ON) < 8.5m(VGS = -20V)  
RDS(ON) < 10m(VGS = -10V)  
Ultra SO-8TM Top View  
D
Bottom tab  
connected to  
drain  
D
G
S
S
G
Absolute Maximum Ratings TA=25°C unless otherwise noted  
Parameter  
Symbol  
Maximum  
Units  
VDS  
Drain-Source Voltage  
-38  
V
VGS  
Gate-Source Voltage  
Continuous Drain  
Current G  
±25  
-85  
V
TC=25°C  
TC=100°C  
ID  
-62  
Pulsed Drain Current C  
IDM  
A
-120  
-12  
Continuous Drain  
Current G  
TA=25°C  
TA=70°C  
TC=25°C  
TC=100°C  
TA=25°C  
TA=70°C  
IDSM  
PD  
-10  
100  
W
Power Dissipation B  
50  
2.08  
1.3  
PDSM  
W
Power Dissipation A  
TJ, TSTG  
Junction and Storage Temperature Range  
-55 to 175  
°C  
Thermal Characteristics  
Parameter  
Symbol  
Typ  
21  
48  
1
Max  
25  
Units  
°C/W  
°C/W  
°C/W  
Maximum Junction-to-Ambient A  
t 10s  
RθJA  
Maximum Junction-to-Ambient A  
Maximum Junction-to-Case B  
60  
Steady-State  
Steady-State  
RθJC  
1.5  
www.freescale.net.cn  
1/6  
AOL1401  
P-Channel Enhancement Mode Field  
Effect Transistor  
Electrical Characteristics (TJ=25°C unless otherwise noted)  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Units  
STATIC PARAMETERS  
BVDSS  
Drain-Source Breakdown Voltage  
ID=-250µA, VGS=0V  
-38  
V
VDS=-30V, VGS=0V  
-100  
-500  
±1  
IDSS  
Zero Gate Voltage Drain Current  
nA  
TJ=55°C  
µA  
µA  
V
DS=0V, VGS=±20V  
DS=0V, VGS=±25V  
IGSS  
Gate-Body leakage current  
V
±10  
-3.5  
VGS(th)  
ID(ON)  
Gate Threshold Voltage  
On state drain current  
VDS=VGS ID=-250µA  
VGS=-10V, VDS=-5V  
VGS=-20V, ID=-20A  
-1.5  
-2.2  
V
A
-120  
6.8  
9.1  
7.9  
50  
8.5  
11  
10  
mΩ  
mΩ  
RDS(ON)  
TJ=125°C  
Static Drain-Source On-Resistance  
VGS=-10V, ID=-20A  
VDS=-5V, ID=-20A  
IS=-1A,VGS=0V  
gFS  
VSD  
IS  
Forward Transconductance  
Diode Forward Voltage  
S
V
A
0.71  
-1  
Maximum Body-Diode Continuous Current  
14.5  
DYNAMIC PARAMETERS  
Ciss  
Coss  
Crss  
Rg  
Input Capacitance  
3800 4560  
pF  
pF  
pF  
V
GS=0V, VDS=-20V, f=1MHz  
GS=0V, VDS=0V, f=1MHz  
Output Capacitance  
Reverse Transfer Capacitance  
Gate resistance  
560  
350  
V
7.5  
9
SWITCHING PARAMETERS  
Qg(10V)  
Qgs  
Qgd  
tD(on)  
tr  
Total Gate Charge (10V)  
Gate Source Charge  
Gate Drain Charge  
Turn-On DelayTime  
Turn-On Rise Time  
Turn-Off DelayTime  
Turn-Off Fall Time  
61.2  
11.88  
15.4  
13.5  
17  
74  
nC  
nC  
nC  
ns  
ns  
ns  
ns  
VGS=-10V, VDS=-20V, ID=-20A  
VGS=-10V, VDS=-20V, RL=1,  
RGEN=3Ω  
tD(off)  
tf  
97  
43  
trr  
IF=-20A, dI/dt=100A/µs  
IF=-20A, dI/dt=100A/µs  
30  
Body Diode Reverse Recovery Time  
Body Diode Reverse Recovery Charge  
36  
ns  
Qrr  
29  
nC  
A: The value of R θJA is measured with the device mounted on 1in 2 FR-4 board with 2oz. Copper, in a still air environment with T A =25°C. The  
Power dissipation PDSM is based on R θJA and the maximum allowed junction temperature of 150°C. The value in any given application depends on  
the user's specific board design, and the maximum temperature of 175°C may be used if the PCB allows it.  
B. The power dissipation PD is based on TJ(MAX)=175°C, using junction-to-case thermal resistance, and is more useful in setting the upper  
dissipation limit for cases where additional heatsinking is used.  
C: Repetitive rating, pulse width limited by junction temperature TJ(MAX)=175°C.  
D. The R θJA is the sum of the thermal impedence from junction to case R θJC and case to ambient.  
E. The static characteristics in Figures 1 to 6 are obtained using <300 µs pulses, duty cycle 0.5% max.  
F. These curves are based on the junction-to-case thermal impedence which is measured with the device mounted to a large heatsink, assuming  
a maximum junction temperature of TJ(MAX)=175°C.  
G. The maximum current rating is limited by bond-wires.  
H. These tests are performed with the device mounted on 1 in2 FR-4 board with 2oz. Copper, in a still air environment with T A =25°C.  
* This device is guaranteed green after date code 8P11 (June 1ST 2008)  
Rev 2: Dec 2008  
2/6  
www.freescale.net.cn  
AOL1401  
P-Channel Enhancement Mode Field  
Effect Transistor  
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS  
120  
90  
60  
30  
0
30  
25  
20  
15  
10  
5
-14V  
-10V  
VDS=-5V  
-6V  
125°C  
-4V  
25°C  
Vgs=-3.5V  
0
0
1
2
3
4
5
2
2.5  
3
3.5  
4
4.5  
5
-VDS (Volts)  
-VGS(Volts)  
Fig 1: On-Region Characteristics  
Figure 2: Transfer Characteristics  
9
8
7
6
1.8  
1.6  
1.4  
1.2  
1
VGS=-20V  
ID=-20A  
VGS=-10V  
VGS=-10V  
ID=-20A  
VGS=-20V  
0.8  
0
5
10  
15  
20  
25  
-ID (A)  
0
30  
60  
90  
Temperature (°C)  
Figure 4: On-Resistance vs. Junction Temperature  
120  
150  
180  
210  
Figure 3: On-Resistance vs. Drain Current and Gate  
Voltage  
30  
25  
20  
15  
10  
5
1.0E+01  
1.0E+00  
1.0E-01  
1.0E-02  
1.0E-03  
1.0E-04  
1.0E-05  
1.0E-06  
ID=-20A  
125°C  
125°C  
25°C  
25°C  
0
0.0  
0.2  
0.4  
0.6  
0.8  
1.0  
4
6
8
10  
-VSD (Volts)  
-VGS (Volts)  
Figure 5: On-Resistance vs. Gate-Source Voltage  
Figure 6: Body-Diode Characteristics  
3/6  
www.freescale.net.cn  
AOL1401  
P-Channel Enhancement Mode Field  
Effect Transistor  
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS  
10  
5000  
Ciss  
VDS=-20V  
ID=-20A  
8
4000  
3000  
2000  
1000  
0
6
4
Coss  
Crss  
2
0
0
5
10  
15  
-VDS (Volts)  
20  
25  
30  
0
10  
20  
30  
40  
50  
60  
70  
-Qg (nC)  
Figure 7: Gate-Charge Characteristics  
Figure 8: Capacitance Characteristics  
1000.0  
100.0  
10.0  
1.0  
1000  
800  
600  
400  
200  
0
TJ(Max)=175°C, TA=25°C  
10µs  
TJ(Max)=175°C  
TA=25°C  
RDS(ON)  
limited  
100µs  
1ms  
10ms  
100m  
DC  
0.1  
0.0001  
0.001  
0.01  
0.1  
1
10  
0.1  
1
10  
100  
-VDS (Volts)  
Pulse Width (s)  
Figure 10: Single Pulse Power Rating Junction-to-  
Case (Note B)  
Figure 9: Maximum Forward Biased Safe  
Operating Area (Note F)  
10  
1
In descending order  
D=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse  
D=Ton/T  
TJ,PK=TC+PDM.ZθJC.RθJC  
RθJC=1.5°C/W  
PD  
0.1  
0.01  
Ton  
T
Single Pulse  
0.00001  
0.0001  
0.001  
0.01  
0.1  
1
10  
100  
Pulse Width (s)  
Figure 11: Normalized Maximum Transient Thermal Impedance (Note F)  
4/6  
www.freescale.net.cn  
AOL1401  
P-Channel Enhancement Mode Field  
Effect Transistor  
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS  
60  
120  
50  
90  
40  
30  
20  
10  
0
60  
30  
0
TA=25°C  
0
25  
50  
75  
TCASE (°C)  
Figure 12: Power De-rating (Note B)  
100  
125  
150  
175  
0.01  
0.1  
1
10  
100  
1000  
Pulse Width (s)  
Figure 13: Single Pulse Power Rating Junction-to-  
Ambient (Note H)  
100  
80  
60  
40  
20  
0
0
25  
50  
75  
CASE (°C)  
Figure 14: Current De-rating (Note B)  
100  
125  
150  
175  
T
100  
10  
D=Ton/T  
In descending order  
D=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse  
TJ,PK=TA+PDM.ZθJA.RθJA  
RθJA=60°C/W  
1
0.1  
PD  
0.01  
Ton  
Single Pulse  
T
0.001  
0.00001  
0.0001  
0.001  
0.01  
0.1  
Pulse Width (s)  
1
10  
100  
1000  
Figure 15: Normalized Maximum Transient Thermal Impedance (Note H)  
5/6  
www.freescale.net.cn  
AOL1401  
P-Channel Enhancement Mode Field  
Effect Transistor  
Gate Charge Test Circuit & Waveform  
Vgs  
Qg  
-
-10V  
-
VDC  
Qgs  
Qgd  
+
Vds  
VDC  
+
DUT  
Vgs  
Ig  
Charge  
Resistive Switching Test Circuit & Waveforms  
RL  
Vds  
toff  
ton  
t
td(off)  
td(on)  
t
r
f
Vgs  
-
90%  
10%  
DUT  
Vdd  
Vgs  
VDC  
+
Rg  
Vgs  
Vds  
Unclamped Inductive Switching (UIS) Test Circuit & Waveforms  
EAR= 1/2 LIA2R  
L
Vds  
Id  
Vgs  
Vds  
-
BVDSS  
Vgs  
Vdd  
VDC  
+
Id  
Rg  
I AR  
DUT  
Vgs  
Vgs  
Diode Recovery Test Circuit & Waveforms  
Q rr = - Idt  
Vds +  
DUT  
Vgs  
trr  
Vds -  
L
-Isd  
-IF  
Isd  
Vgs  
dI/dt  
-IRM  
+
Vdd  
VDC  
Vdd  
-
-Vds  
Ig  
6/6  
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