IRFR13N15D [FREESCALE]

HEXFETÂ® Power MOSFET; HEXFETÂ®功率MOSFET


型号：	IRFR13N15D
厂家：	Freescale
描述：	HEXFETÂ® Power MOSFET HEXFETÂ®功率MOSFET
文件：	总8页 (文件大小：318K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IRFR/U13N15D

SMPS MOSFET

HEXFET^®Power MOSFET

Applications

^lHigh frequency DC-DC converters

V_DSS

150V

R_DS(on)max

I_D

14A

0.18Ω

Benefits

^lLow Gate-to-Drain Charge to Reduce

Switching Losses

^lFully Characterized Capacitance Including

Effective C_OSSto Simplify Design, (See

App. Note AN1001)

^lFully Characterized Avalanche Voltage

and Current

D-Pak

IRFR13N15D

I-Pak

IRFU13N15D

Absolute Maximum Ratings

Parameter

Max.

Units

I_D@ T_C= 25°C

I_D@ T_C= 100°C

I_DM

Continuous Drain Current, V_GS@ 10V

Pulsed Drain Current

9.8

P_D@T_C= 25°C

Power Dissipation

W/°C

Linear Derating Factor

0.57

V_GS

dv/dt

T_J

Gate-to-Source Voltage

± 30

Peak Diode Recovery dv/dt

Operating Junction and

3.8

V/ns

-55 to + 175

T_STG

Storage Temperature Range

Soldering Temperature, for 10 seconds

°C

300 (1.6mm from case )

Typical SMPS Topologies

^lTelecom 48V input Active Clamp Forward Converter

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IRFR/U13N15D

Static @ T_J= 25°C (unless otherwise specified)

Parameter

Min. Typ. Max. Units

150 ––– –––

Conditions

V_(BR)DSS

Drain-to-Source Breakdown Voltage

V_GS= 0V, I_D= 250µA

∆V_(BR)DSS/∆T_JBreakdown Voltage Temp. Coefficient

––– 0.17 ––– V/°C Reference to 25°C, I_D= 1mA

R_DS(on)

V_GS(th)

Static Drain-to-Source On-Resistance

Gate Threshold Voltage

––– ––– 0.18

3.0 ––– 5.5

Ω

V_GS= 10V, I_D= 8.3A

V_DS= V_GS, I_D= 250µA

V_DS= 150V, V_GS= 0V

V_DS= 120V, V_GS= 0V, T_J= 150°C

V_GS= 30V

––– ––– 25

––– ––– 250

––– ––– 100

––– ––– -100

I_DSS

Drain-to-Source Leakage Current

µA

Gate-to-Source Forward Leakage

Gate-to-Source Reverse Leakage

I_GSS

V_GS= -30V

Dynamic @ T_J= 25°C (unless otherwise specified)

Parameter

Forward Transconductance

Total Gate Charge

Min. Typ. Max. Units

5.0 ––– –––

––– 19 29

5.5 8.2

9.4 14

Conditions

V_DS= 50V, I_D= 8.3A

I_D= 8.3A

g_fs

Q_g

Q_gs

Q_gd

t_d(on)

t_r

Gate-to-Source Charge

Gate-to-Drain ("Miller") Charge

Turn-On Delay Time

Rise Time

–––

nC V_DS= 120V

V_GS= 10V,

V_DD= 75V

8.0 –––

26 –––

12 –––

11 –––

I_D= 8.3A

t_d(off)

t_f

Turn-Off Delay Time

Fall Time

R_G= 11Ω

V_GS= 10V

V_GS= 0V

C_iss

C_oss

C_rss

C_oss

C_osseff.

Input Capacitance

––– 620 –––

––– 130 –––

Output Capacitance

Reverse Transfer Capacitance

Output Capacitance

Effective Output Capacitance

V_DS= 25V

–––

––– 780 –––

––– 62 –––

––– 110 –––

38 –––

ƒ = 1.0MHz

V_GS= 0V, V_DS= 1.0V, ƒ = 1.0MHz

V_GS= 0V, V_DS= 120V, ƒ = 1.0MHz

V_GS= 0V, V_DS= 0V to 120V ꢀ

Avalanche Characteristics

Parameter

Single Pulse Avalanche Energy

Avalanche Current

Typ.

–––

Max.

130

8.3

Units

E_AS

I_AR

E_AR

Repetitive Avalanche Energy

8.6

Thermal Resistance

Parameter

Junction-to-Case

Typ.

–––

Max.

1.75

Units

R_θJC

R_θJA

Junction-to-Ambient (PCB mount)*

Junction-to-Ambient

°C/W

110

Diode Characteristics

Parameter

Min. Typ. Max. Units

Conditions

I_S

Continuous Source Current

(Body Diode)

MOSFET symbol

––– –––

showing the

I_SM

Pulsed Source Current

(Body Diode)

integral reverse

p-n junction diode.

V_SD

t_rr

Diode Forward Voltage

Reverse Recovery Time

Reverse RecoveryCharge

Forward Turn-On Time

––– ––– 1.3

––– 110 –––

––– 520 –––

T_J= 25°C, I_S= 8.3A, V_GS= 0V

T_J= 25°C, I_F= 8.3A

Q_rr

t_on

nC di/dt = 100A/µs

Intrinsic turn-on time is negligible (turn-on is dominated by L_S+L_D)

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IRFR/U13N15D

100

VGS

15V

12V

10V

8.0V

7.0V

6.0V

5.5V

VGS

15V

12V

10V

8.0V

7.0V

6.0V

5.5V

TOP

BOTTOM 5.0V

5.0V

0.1

20µs PULSE WIDTH

T = 25 C

20µs PULSE WIDTH

T = 175 C

0.01

0.1

100

, Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics

Fig 2. Typical Output Characteristics

100

3.0

14A

2.5

2.0

1.5

1.0

0.5

0.0

T = 175 C

T = 25 C

= 50V

20µs PULSE WIDTH

= 10V

0.1

-60 -40 -20

20 40 60 80 100 120 140 160 180

T , Junction Temperature ( C)

, Gate-to-Source Voltage (V)

Fig 3. Typical Transfer Characteristics

Fig 4. Normalized On-Resistance

Vs. Temperature

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IRFR/U13N15D

= 8.3A

10000

1000

100

= 0V,

f = 1 MHZ

= 120V

= 75V

= 30V

= C + C

SHORTED

iss

= C

rss

= C + C

oss

Ciss

Coss

Crss

FOR TEST CIRCUIT

SEE FIGURE 13

100

1000

, Drain-to-Source Voltage (V)

, Total Gate Charge (nC)

Fig 6. Typical Gate Charge Vs.

Fig 5. Typical Capacitance Vs.

Gate-to-Source Voltage

Drain-to-Source Voltage

1000

100

OPERATION IN THIS AREA LIMITED

BY R

DS(on)

T = 175 C

10us

100us

T = 25 C

1ms

10ms

T = 25 C

T = 175 C

Single Pulse

= 0 V

1.2

0.1

0.2

0.1

0.4

0.6

0.8

1.0

1.4

100

1000

,Source-to-Drain Voltage (V)

, Drain-to-Source Voltage (V)

Fig 8. Maximum Safe Operating Area

Fig 7. Typical Source-Drain Diode

Forward Voltage

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IRFR/U13N15D

R_D

V_DS

V_GS

D.U.T.

R_G

⁺V_DD

V_GS

Pulse Width ≤ 1 µs

Duty Factor ≤ 0.1 %

Fig 10a. Switching Time Test Circuit

90%

100

125

150

175

, Case Temperature ( C)

10%

Fig 9. Maximum Drain Current Vs.

d(on)

d(off)

Case Temperature

Fig 10b. Switching Time Waveforms

D = 0.50

0.20

0.10

0.05

0.1

0.01

0.02

0.01

SINGLE PULSE

(THERMAL RESPONSE)

Notes:

1. Duty factor D =

t / t

1 2

2. Peak T = P

x Z

+ T

thJC C

0.00001

0.0001

0.001

0.01

0.1

t , Rectangular Pulse Duration (sec)

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

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IRFR/U13N15D

240

200

160

120

1 5V

TOP

3.4A

5.9A

BOTTOM 8.3A

DRIVER

D.U.T

D D

20V

0.01

Ω

Fig 12a. Unclamped Inductive Test Circuit

(BR)DSS

100

125

150

175

Starting T , Junction Temperature ( C)

Fig 12c. Maximum Avalanche Energy

Vs. Drain Current

Fig 12b. Unclamped Inductive Waveforms

Current Regulator

Same Type as D.U.T.

50KΩ

.2µF

12V

.3µF

D.U.T.

3mA

Charge

Current Sampling Resistors

Fig 13a. Basic Gate Charge Waveform

Fig 13b. Gate Charge Test Circuit

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IRFR/U13N15D

Peak Diode Recovery dv/dt Test Circuit

Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

• Low Leakage Inductance

Current Transformer

D.U.T

R_G

• dv/dt controlled by R_G

• Driver same type as D.U.T.

• I_SDcontrolled by Duty Factor "D"

• D.U.T. - Device Under Test

V_DD

Driver Gate Drive

P.W.

Period

D =

=10V

D.U.T. I Waveform

Reverse

Recovery

Current

Body Diode Forward

Current

di/dt

D.U.T. V Waveform

Diode Recovery

dv/dt

Re-Applied

Voltage

Body Diode

Forward Drop

Inductor Curent

Ripple ≤ 5%

* V_GS= 5V for Logic Level Devices

Fig 14. For N-Channel HEXFET^®Power MOSFETs

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IRFR/U13N15D

D-Pak (TO-252AA) Tape & Reel Information

Dimensions are shown in millimeters (inches)

TRL

TRR

16.3 ( .641 )

15.7 ( .619 )

16.3 ( .641 )

15.7 ( .619 )

12.1 ( .476 )

11.9 ( .469 )

8.1 ( .318 )

7.9 ( .312 )

FEED D IRECTIO N

FEED DIR ECTION

N O TES

1. CO NTRO LLING D IMENSIO N : M ILLIM ETER.

2. ALL D IM EN SION S ARE SHO W N IN M ILLIM ETERS ( INCHES ).

3. OU TLINE C ON FO RMS TO EIA-481 & EIA-541.

13 INCH

16 m m

NO TES :

1. OU TLINE CON FO RMS TO EIA-481.

Notes:

Repetitive rating; pulse width limited by

Pulse width ≤ 300µs; duty cycle ≤ 2%.

max. junction temperature.

ꢀC_osseff. is a fixed capacitance that gives the same charging time

Starting T_J= 25°C, L = 3.8mH

R_G= 25Ω, I_AS= 8.3A.

as C_osswhile V_DSis rising from 0 to 80% V_DSS

I_SD≤ 8.3A, di/dt ≤ 280A/µs, V_DD≤ V_(BR)DSS

T_J≤ 175°C

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