MC145181 [FREESCALE]
Dual 550/60 MHz PLL Frequency Synthesizer with DACs and Voltage Multiplier; 双六十零分之五百五十〇 MHz的PLL频率合成器， DAC和电压倍增器
| 型号： | MC145181 |
| 厂家： | 
Freescale |
| 描述： | Dual 550/60 MHz PLL Frequency Synthesizer with DACs and Voltage Multiplier |
| 文件： | 总71页 (文件大小：957K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, IncO.rder this document by MC145181/D
1
BiCMOS COMPONENT
FOR 2 OR 3 VOLT
The MC145181 is a dual frequency synthesizer containing very–low
supply voltage circuitry. The device supports two independent loops with a
single input reference and operates down to 1.8 V. Phase noise reduction
circuitry is incorporated into the device.
The MC145181 operates up to 550 MHz on the main loop and up to
60 MHz on the secondary loop. The device has a 32/33 prescaler for the
main loop. Lock detection circuitry for both loops is multiplexed to a single
output.
SYSTEMS
SEMICONDUCTOR
TECHNICAL DATA
Two 8–bit DACs are powered through a dedicated pin. The DAC supply
range is 1.8 to 3.6 V; this voltage may differ from the main supply.
An on–chip voltage multiplier supplies power to the phase/frequency
detectors. Thus, in a 2 V application, the detectors are supplied with 4 V
power. In 2.6 to 3.6 V applications, the multiplied voltage is regulated at
approximately 5 V. The current source/sink phase/frequency detector for the
main loop is designed to achieve faster lock times than a conventional
detector. Both high and low current outputs are available along with a timer,
double buffers, and a MOSFET switch to adjust the external low–pass filter
response.
There are several levels of standby which are controllable with a 1–byte
transfer through the serial port. Either of the PLLs and/or the reference
oscillator may be independently placed in the low–power standby state. In
addition, any of the phase/frequency detector outputs may be placed in the
floating state to facilitate modulation of the external VCOs. Either DAC may
be placed in standby via a 4–byte transfer.
32
1
(Scale 2:1)
PLASTIC PACKAGE
CASE 873C
(LQFP–32, Tape & Reel Only)
VERY–SMALL 5 x 5 mm BODY
DEVELOPMENT SYSTEM
The MC145230EVK, which contains hardware and
software, is strongly recommended for system
development. (The user must provide the VCOs for
evaluating the MC145181.) The software supports
all features and modes of operation of the device. Up
to four boards or devices can be controlled and the
user is alerted to error conditions. The control
program may be used with any board based on the
MC145181, MC145225, or MC145230.
The MC145181 facilitates designing the receiver’s first and second local
oscillators for ReFLEX two–way paging applications. Also, the device
accommodates generation of the transmit carrier.
• Operating Frequency
Main Loop: 100 to 550 MHz
Secondary Loop: 10 to 60 MHz
• Operating Supply Voltage: 1.8 to 3.6 V
• Nominal Supply Current, Both Loops Active: 3 mA
• Maximum Standby Current, All Systems Shut Down: 10 µA
• Phase Detector Output Current:
ORDERING INFORMATION
1.8 V Supply — PD –Hi: 2.8 mA, PD –Lo: 0.7 mA
out out
2.5 V Supply — PD –Hi: 4.4 mA, PD –Lo: 1.1 mA
out out
Main/Secondary
Loop
Maximum
Frequency
• Two Independent 8–Bit DACs with Separate Supply Pin (Up to 3.6 V)
• Lock Detect Output with Adjustable Lock Indication Window
• Independent R Counters Allow Independent Step Sizes for Each Loop
• Main Loop Divider Range: 992 to 262,143
Device
Package
MC145181FTAR2
550/60 MHz
LQFP–32
• Secondary Loop Divider Range: 7 to 8,191
• Fractional Reference Counters Divider Range: 20 to 32,767.5
• Auxiliary Reference Divider with Small–Signal Differential
Output — Ratios: 8, 10, 12.5
• Three General–Purpose Outputs
• Direct Interface to Motorola SPI Data Port Up to 10 Mbps
ReFLEX and BitGrabber are trademarks of Motorola, Inc.
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
Motorola, Inc. 1999
Rev 1
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MC145181
CONTENTS
1. BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2. PIN CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3. PARAMETER TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
4
4
3A. Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3B. DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
5
5
5
6
6
6
8
3C. PD –Hi and PD –Lo Phase/Frequency Detector Characteristics . . . . . .
out
out
3D. PD
Phase/Frequency Detector Characteristics . . . . . . . . . . . . . . . . . . . . .
out
3E. DAC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3F. Voltage Multiplier and Keep–alive Oscillator Characteristics . . . . . . . . . . . . .
3G. Dynamic Characteristics of Digital Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3H. Dynamic Characteristics of Loop and f
Pins . . . . . . . . . . . . . . . . . . . . . . . . .
out
4. DEVICE OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
4A. Serial Interface and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4B. Reference Input and Counters Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4C. Loop Divider Inputs and Counter Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4D. Voltage Multiplier and Keep–alive Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
9
9
9
4E. Phase/Frequency Detectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4F. Lock Detectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4G. DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4H. General–purpose Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5. PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5A. Digital Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5B. Reference Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5C. Loop Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5D. Analog Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5E. External Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5F. Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6. DETAILED REGISTER DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6A. C Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6B. Hr Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6C. N Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6D. R Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6E. Hn Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6F. D Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7. APPLICATIONS INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7A. Crystal Oscillator Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7B. Main Loop Filter Design — Conventional . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7C. Main Loop Filter Design — Adapt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7D. Secondary Loop Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7E. Voltage Multiplier Stall Avoidance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
8. PROGRAMMER’S GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
8A. Quick Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
8B. Initializing the Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
8C. Programming Without Adapt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
8D. Programming Utilizing Horseshoe With Adapt . . . . . . . . . . . . . . . . . . . . . . . . . . 66
8E. Controlling the DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
9. APPLICATION CIRCUIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10. OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
2
MOTOROLA RF/IF DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MC145181
1. BLOCK DIAGRAM
16
25
Output C
Output B
Out C
Out B/Ref
PLL Stby
Out A
C Register
8 Bits
f
Output A
Mux
R
9
PLL Stby
Output A
f
R
PLL Stby
PD Float
PD Float
Osc Stby
Ph Det Pulse
Function
Timer
N Register
24 Bits
3
High–
current
Charge
Pump
19
PD –Hi
out
18
Phase/
12
f
V
f
+
–
in
N Counter
18 Stages
Frequency
Detector,
Timer,
17
13
Rx
f
in
Amp
Low–
current
Charge
Pump
and Control
f
R
20
R Counter
16 Stages
PD –Lo
out
Lo–I Gain
Polarity
16
R Register
16 Bits
Osc
V–Mult
21
22
Voltage
Multiplier
and Regulator
C
C
mult
Window
Control
16
reg
Hr Register
16 Bits
Lock
Detector
1
Osc
Osc
8
e
b
2
LD
32
Oscillator
3
Supply Current
Minimization
Circuit
2
R
Register
24 Bits
Lock
Detector
16
Test
f
R
Counter
R
16 Stages
Ratio
Phase/
Frequency
Detector
23
10
PD
out
Mode
f
V
N
Counter
30
f
in
13 Stages
Amp
Polarity
13
N
Register
13 Bits
28
27
Auxiliary
Divider
3 Stages
f
f
/Pol
/Pol
out
out
13 MSBs
Hn Register
16 Bits
8
8
DAC
8 Bits
3
2
4
D Register
16 Bits
DAC1
DAC V
DAC2
pos
5
Enb
DAC
8 Bits
Power Connections:
Pin 2 = DAC V
6
7
Shift Register and
Address Generator
D
in
pos
Pins 11, 24, 26, and 29 = V
pos
Pins 14, 15, 18, and 31 = Gnd
Clk
3
MOTOROLA RF/IF DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MC145181
2. PIN CONNECTIONS
f
/
′
f
/
Output
B
out
out
Gnd
31
f
′
V
Osc
Pol
Pol
V
in
30
pos
29
b
pos
26
32
28
27
25
Osc
1
24
V
pos
e
DAC V
2
3
4
5
6
7
8
23 PD ′
out
pos
22
21
C
DAC1
DAC2
Enb
reg
mult
C
20 PD –Lo
out
D
19 PD –Hi
out
in
Clk
LD
18 Gnd
17 Rx
9
10
11
12
13
14
15
16
Output Mode
A
V
f
f
in
Gnd Gnd Output
C
pos
in
This device contains 15,260 active transistors.
3. PARAMETER TABLES
3A. MAXIMUM RATINGS (Voltages Referenced to Gnd, unless otherwise stated)
Parameter
DC Supply Voltages
Symbol
Value
Unit
This device contains protection circuitry to
guard against damage due to high static volt-
ages or electric fields. However, precautions
must be taken to avoid applications of any
voltage higher than maximum rated voltages
to this high–impedance circuit.
V
,
–0.5 to 3.6
V
pos
DAC V
pos
DC Input Voltage — Osc , f , f , Mode,
V
in
–0.5 to V
+ 0.5
V
e
in in
pos
pos
D , Clk, Enb, f /Pol , f /Pol
in out out
DC Output Voltage
V
out
–0.5 to V
+ 0.5
V
DC Input Current, per Pin
DC Output Current, per Pin
I
±10
mA
mA
mA
mW
°C
in
I
±20
25
out
DC Supply Current, V
and Gnd Pins
I
pos
Power Dissipation, per Package
Storage Temperature
P
100
D
T
stg
–65 to 150
260
Lead Temperature, 1 mm from Case for
10 Seconds
T
°C
L
NOTES:1. Maximum Ratings are those values beyond which damage to the device may occur.
FunctionaloperationshouldberestrictedtothelimitsintheElectricalCharacteristicstables
or Pin Descriptions section.
2. ESD (electrostatic discharge) immunity meets Human Body Model (HBM) up to 2000 V.
Additional ESD data available upon request.
4
MOTOROLA RF/IF DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MC145181
3B. DC ELECTRICAL CHARACTERISTICS
V
pos
= 1.8 to 3.6 V, Voltages Referenced to Gnd, T = –40 to 85°C, unless otherwise statedtt
A
Guaranteed
Limit
Parameter
Maximum Low–Level Input Voltage
Condition
/Pol and f /Pol Configured as Inputs
Symbol
Unit
f
f
V
IL
0.3 x V
V
out
out
pos
pos
(D , Clk, Enb, Mode, f /Pol , f /Pol)
in
out
out
Minimum High–Level Input Voltage
/Pol and f /Pol Configured as Inputs
out out
V
IH
0.7 x V
V
(D , Clk, Enb, Mode, f /Pol , f /Pol)
in
out
out
Minimum Hysteresis Voltage
(Clk)
V
100
0.1
mV
V
Hys
Maximum Low–Level Output Voltage
(LD, Output A, Output B)
I
I
= 20 µA
V
out
OL
OH
OL
Minimum High–Level Output Voltage
(LD, Output A, Output B)
= –20 µA
V
V
– 0.1
V
out
pos
Minimum Low–Level Output Current
(LD, Output A, Output B)
V
= 0.3 V
I
0.7
mA
mA
out
Minimum High–Level Output Current
(LD, Output A, Output B)
V
= V
– 0.3 V
I
–0.7
out
pos
OH
Minimum Low–Level Output Current (Output C)
V
out
= 0.2 V
I
2.8
mA
OL
Maximum Input Leakage Current
V
= V
or Gnd; f /Pol and f /Pol
I
in
±1.0
µA
in
pos
out
out
(D , Clk, Enb, Mode, f /Pol , f /Pol) Configured as Inputs
in
out
out
Maximum Output Leakage Current
V
= V
or Gnd; Output in High–Impedance
I
±1
µA
Ω
out
(Output B, Output C) State
pos
OZ
Maximum ON Resistance
(Output C) 1.8 V ≤ V
2.5 V ≤ V
< 2.5 V Supply
R
75
50
pos
pos
on
≤ 3.6 V Supply (Note 1)
Maximum Standby Supply Current
V
= V
or Gnd; Outputs Open; Both PLLs in
I
STBY
10
µA
in
pos
(V
pos
and DAC V
Tied Together) Standby Mode; Oscillator in Standby Mode;
DAC1 and DAC2 Output = Zero; Keep–alive
Oscillator Off (Notes 2, 3, and 4)
pos
NOTES:1. For supply voltages restricted to 2.5 to 2.9 V and an ambient temperature range of –10 to 60°C, Output C has a guaranteed ON resistance range of 23
to 44 Ω.
2. The total supply current drain for the keep–alive oscillator, voltage multiplier, and regulator is approximately 250 µA.
3. Whenthe Mode pin is tied high, bit C6 must be programmed to a 0 for minimum supply current drain. Otherwise, if C6 = 1, the current drain is approximately
8 µA for a 1.8 V supply and approximately 40 µA for a 3.6 V supply. This restriction on bit C6 does not apply when the Mode pin is tied low.
4. To ensure minimum standby supply current drain, the voltage potential at the C
pin must not be allowed to fall below the potential at the V
pins.
pos
mult
See discussion in Section 5E under C
.
mult
3C. PD
–Hi AND PD
–Lo PHASE/FREQUENCY DETECTOR CHARACTERISTICS
out
out
Nominal Output Current, V
= 1.8 V: PD –Hi = 2.8 mA, PD –Lo = 0.7 or 0.35 mA
pos
out out
Nominal Output Current, V
≥ 2.5 V: PD –Hi = 4.4 mA, PD –Lo = 1.1 or 0.55 mA
out out
pos
Rx = 2.0 kΩ, Voltages Referenced to Gnd, Voltage Multiplier ON, T = –40 to 85°C
A
Guaranteed
Limit
Parameter
Maximum Source Current Variation Part–to–Part
Maximum Sink–versus–Source Mismatch
Output Voltage Range
Condition
Unit
(See Note)
(See Note)
(See Note)
V
= 0.5 x V
= 0.5 x V
±14
%
%
V
out
Cmult
Cmult
V
out
20
I
Variation ≤ 27%
0.6 to V
– 0.6 V
Cmult
out
Maximum Three–State Leakage Current
V
out
= 0 or V
±50
nA
Cmult
NOTE: Percentages calculated using the following formula: (Maximum Value – Minimum Value)/Maximum Value.
3D. PD
PHASE/FREQUENCY DETECTOR CHARACTERISTICS
out
V
pos
= 1.8 to 3.6 V, Voltages Referenced to Gnd, Voltage Multiplier ON, T = –40 to 85°C
A
Guaranteed
Limit
Parameter
Condition
= 0.3 V
Unit
mA
mA
nA
Minimum Low–Level Output Current
Minimum High–Level Output Current
Maximum Three–State Leakage Current
V
0.3
–0.3
±50
out
V
out
= V
– 0.3 V
Cmult
V
out
= 0 or V
Cmult
5
MOTOROLA RF/IF DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MC145181
3E. DAC CHARACTERISTICS
V
pos
= 1.8 to 3.6 V, DAC V
= 1.8 to 3.6 V; T = –40 to 85°C
pos
A
Guaranteed
Limit
Parameter
Condition
Unit
Bits
LSB
LSB
LSB
kΩ
Resolution
Maximum Integral Nonlinearity
8
±1
1
Maximum Offset Voltage from Gnd
Maximum Offset Voltage from DAC V
Maximum Output Impedance
No External Load
No External Load
2
pos
Over Entire Output Range, Including Zero
Output (which is Low–power Standby)
130
Maximum Standby Current
Zero Output, No External Load
(See I
in Section 3B)
STBY
Maximum Supply Current per DAC @ DAC V
pin Except with Zero Output, No External Load
(DAC V
) / 36
pos
mA
pos
3F. VOLTAGE MULTIPLIER AND KEEP–ALIVE OSCILLATOR CHARACTERISTICS
Voltages Referenced to Gnd, T = –40 to 85°C
A
Guaranteed
Limit
Parameter
Condition
Unit
Voltage Multiplier Output Voltage
5 MHz Refresh Rate, 100 µA Continuous
Sourcing, Measured at C
pin
mult
3.32 to 3.78
4.75 to 5.35
V
V
pos
V
pos
= 1.8 V
= 3.6 V
Keep–alive Refresh Frequency
V
pos
= 1.8 to 3.6 V
300 to 700
kHz
3G. DYNAMIC CHARACTERISTICS OF DIGITAL PINS
V
pos
= 1.8 to 3.6 V, T = –40 to 85°C, Input t = t = 10 ns, C = 25 pF
A r f L
Figure
No.
Guaranteed
Limit
Parameter
Symbol
Unit
Serial Data Clk Frequency
NOTE: Refer to Clk t Below
1
f
dc to 10
MHz
clk
w
Maximum Propagation Delay, Enb to Output A (Selected as General–Purpose Output)
Maximum Propagation Delay, Enb to Output B
2, 7
t
, t
200
200
ns
ns
PLH PHL
2, 3, 7, 8
t
t
, t ,
, t
PLH PHL
PZL PLZ
, t
,
t
PZH PHZ
Maximum Propagation Delay, Enb to Output C
4, 8
2, 7
5
t
, t
200
75
30
100
*
ns
ns
PZL PLZ
Maximum Output Transition Time, Output A; Output B with Active Pullup and Pulldown
t
, t
TLH THL
Minimum Setup and Hold Times, D versus Clk
in
t
, t
su
ns
h
Minimum Setup, Hold, and Recovery Times, Enb versus Clk
Minimum Pulse Width, Inactive (High) Time, Enb
Minimum Pulse Width, Clk
6
t
su
, t , t
h
ns
rec
6
t
t
cycles
ns
w
1
50
10
w
Maximum Input Capacitance — D , CLK, Enb
in
C
pF
in
*For Hr register access, the minimum limit is 20 Osc cycles.
e
For Hn register access, the minimum limit is 27 f cycles.
in
For N register access, the minimum limit is 20 Osc cycles + 99 f cycles.
e
in
When the timer is used for adapt, the minimum limit after the second N register access and before the next register access is the time–out interval + 99 f cycles.
in
6
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Figure 1.
Figure 2.
t
t
r
f
V
pos
Enb
50%
V
pos
90%
50%
10%
Gnd
Clk
Gnd
t
t
w
w
t
t
PHL
PLH
1/f
clk
Output A
Output B
90%
10%
t
t
THL
TLH
Figure 3.
Figure 4.
V
V
pos
pos
Enb
50%
Enb
Output C
Output C
50%
Gnd
Gnd
t
t
t
PZL
PZL
High
Impedance
90%
90%
10%
Output B
Output B
Output B
t
PLZ
PLZ
High
Impedance
10%
t
PZH
10%
t
PHZ
90%
Output B
Figure 5.
Figure 6.
t
w
Valid
V
pos
V
pos
Enb
Clk
50%
D
in
50%
Gnd
Gnd
V
t
t
h
su
t
t
t
rec
su
h
V
pos
pos
Clk
50%
50%
First
Gnd
Last
Gnd
Clock
Clock
Figure 7.
Figure 8.
Source current and
limit voltage to V
pos
Test Point
for t
and t
.
PLZ
Sink current and
limit voltage to Gnd
for t and t
PZL
Device
Under
Test
Test Point
.
PZH
PHZ
250 µA
C *
L
Device
Under
Test
C *
L
* Includes all probe and fixture capacitance.
* Includes all probe and fixture capacitance.
7
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3H. DYNAMIC CHARACTERISTICS OF LOOP AND f
PINS
out
V
pos
= 1.8 to 3.6 V, T = –40 to 85°C
A
Figure
No.
Symbol
Parameter
Condition
Min
100
100
9
Max
300
400
80
Unit
mVpp
mVpp
MHz
v
Input Voltage Range, f
Input Voltage Range, f
100 MHz ≤ f < 550 MHz
9
in
in
in
in
v
10 MHz ≤ f < 60 MHz
10
11
in
in
= 350 to 600 mVpp,
f
Input Frequency Range, Osc
v
in
Osce
e
Device in External Reference Mode
f
Crystal Frequency, Osc and Osc
e
Device in Crystal Mode
*
9
80
—
MHz
pF
Xtal
b
C
Input Capacitance of Pins Osc and
—
in
b
Osc
e
f
Output Frequency Range, f
out
and f
out
Output Signal Swing > 300 mVpp per
pin (600 mVpp differential)
12
1
6.2
MHz
kHz
out
f
φ
Operating Frequency Range of the
Phase/Frequency Detectors, PD –Hi,
PD –Lo, PD
out out
dc
600
out
*Refer to the Crystal Oscillator Considerations section.
Figure 9.
Figure 10.
100 pF
100 pF
Sine Wave
Generator
Sine Wave
Generator
f
f
in
in
Device
Under
Test
Device
Under
Test
Z
= 50
Ω
Z
= 50 Ω
out
out
V
V
in
in
RF
Meter
= 50
RF
Meter
= 50
f
in
Gnd
V
V
pos
Gnd
R
Ω
R
Ω
pos
V
V
L
L
pos
pos
100 pF
Figure 11.
Figure 12.
0.1 µF
Sine Wave
Generator
Osc
f
V
V
e
out
Device
Under
Test
Device
Under
Test
20 pF
20 pF
Peak–to–peak
Voltage
Measurement
V
in
50
Ω
Osc
Gnd
b
f
out
V
pos
V
pos
No
Connection
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Reference Counter for Main Loop
4. DEVICE OVERVIEW
Main reference counter R divides down the frequency at
Osc and feeds the phase/frequency detector for the main
e
loop. The detector feeds the two charge pumps with outputs
Refer to the Block Diagram in Section 1.
PD –Hi and PD –Lo. The division ratio of the R counter is
determined by bits in the R register.
out
out
4A. SERIAL INTERFACE AND REGISTERS
The serial interface is comprised of a Clock pin (Clk), a
Reference Counter for Secondary Loop
Data In pin (D ), and an Enable pin (Enb). Information on the
in
data input pin is shifted into a shift register on the low–to–high
transition of the serial clock. The data format is most
significant bit (MSB) first. Both Clk and Enb are
Schmitt–triggered inputs.
Secondary reference counter R divides down the
frequency at Osc and feeds the phase/frequency detector
e
for the secondary loop. The detector output is PD
out
. The
division ratio of the R counter is determined by the 16 LSBs
of the R register.
The R and N registers contain counter divide ratios for the
main loop, PLL. The R and N registers contain counter
divide ratios for the secondary loop, PLL . Additional contol
bits are located in the R , N, and C registers. The D register
controls the digital–to–analog converters (DACs). Random
access is allowed to the N, R , Hr, Hn , D, and C registers.
Two 16–bit holding registers, Hr and Hn , feed registers R
and N , respectively. [The three least significant bits (LSBs)
of the Hn register are not used.] The R and N registers
determine the divide ratios of the R and N counters,
respectively. Thus, the information presented to the R and N
counters is double–buffered. Using the proper programming
sequence, new divide ratios may be presented to the N, R,
and N counters; simultaneously.
The R counter has a special mode to provide a frequency
output at pins f
low–jitter ECL–type outputs. With the Mode pin low, software
control allows the Osc frequency to be divided–by–8, –10,
and f
(differential outputs). These are
out
out
e
or –12.5 and routed to the f
out
pins. This output is derived by
tapping off of a front–end stage of the R counter and feeding
the auxiliary counter which provides the divided–down
frequency. The chip must have the Mode pin low, which
activates the f
pins. The actual R divide ratio must be
out
divisible by 2 or 2.5 when the f
pins are activated. There is
out
no such restriction when the Mode pin is high. See
Section 6D, R Register.
Enb is used to activate the data port and allow transfer of
data. To ensure that data is accepted by the device, the Enb
signal line must initially be a high voltage (not asserted), then
make a transition to a low voltage (asserted) prior to the
occurrence of a serial clock, and must remain asserted until
after the last serial clock of the burst. Serial data may be
transferred in an SPI format (while Enb remains asserted).
Data is transferred to the appropriate register on the rising
edge of Enb (see Table 1). “Short shifting”, depicted as
BitGrabber in the table, allows access to certain registers
without requiring address bits. When Enb is inactive (high),
Clk is inhibited from shifting the shift register.
4C. LOOP DIVIDER INPUTS AND COUNTER CIRCUITS
f
Inputs and Counter Circuit
in
f
and f are high–frequency inputs to the amplifier which
in
in
feeds the N counter. A small signal can feed these inputs
either differentially or single–ended.
The N counter divides down the external VCO frequency
for the main loop. (The divide ratio of the N counter is also
known as the loop multiplying factor.) The divide ratio of this
counter is determined by the 18 LSBs of the N register. The
output of the N counter feeds the phase/frequency detector
for the main loop.
The serial input pins may NOT be driven above the supply
voltage applied to the V
pins.
pos
f
Input and Counter Circuit
in
f
is the high–frequency input to the amplifier which feeds
in
4B. REFERENCE INPUT AND COUNTERS CIRCUITS
the N counter. A small signal can feed this input
single–ended.
Reference (Oscillator) Circuit
The N counter divides down the external VCO frequency
for the secondary loop. (The divide ratio of the N counter is
also known as the loop multiplying factor.) The divide ratio of
this counter is determined by bits in the N register. The
output of the N counter feeds the phase/frequency detector
for the secondary loop.
For the Colpitts reference oscillator, one pin ties to the
base (Osc , pin 32) and the other ties to the emitter (Osc ,
b
e
pin 1), of an on–chip NPN transistor. In addition, the
reference circuit may be operated in the external reference
(XRef) mode as selectable via bit C6 when the Mode pin is
high.
The Osc and Osc pins support an external fundamental
b
e
or overtone crystal. The output of the oscillator is routed to
both the reference counter for the main loop (R counter) and
the reference counter for the secondary loop (R counter).
In a second mode, determined by bit C6 being 1 and the
4D. VOLTAGE MULTIPLIER AND KEEP–ALIVE
CIRCUITS
The voltage multiplier produces approximately two times
the voltage present at the V
1.8 V to about 2.5 V. With a supply range of approximately
2.5 V to 3.6 V, the elevated voltage is regulated/limited to
pins over a supply range of
Mode pin being high, Osc is an input which accepts an
pos
e
ac–coupled signal from a TCXO or other source. Osc must
b
be floated. If the Mode pin is low, this “XRef mode” is not
allowed.
approximately 5 V. The elevated voltage, present at the C
mult
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pin, is applied to both phase detectors. An external capacitor
to Gnd is required on the C pin. The other capacitors
required for the multiplier are on–chip.
Detector for Secondary Loop
mult
The detector for the secondary loop senses the phase and
frequency difference between the outputs of the R and N
counters. Detector output PD
out
with a three–state push–pull driver.
The output can be forced to the floating state by a bit in the
C register. This facilitates introduction of modulation into the
VCO input.
A capacitor to Gnd is also required on the C
voltage on this pin is equal to the voltage on the V pins
over a supply range of 1.8 V to about 2.5 V. The voltage on
pin. The
reg
is a voltage–type output
pos
C
is limited to approximately 2.5 V maximum when the
pins exceed 2.5 V.
The refresh rate determines the repetition rate that the
reg
V
pos
capacitors for the voltage multiplier are charged. Refresh is
normally derived off of the signal present at the Osc pin,
e
4F. LOCK DETECTORS
through a divider which is part of the voltage multiplier and
regulator circuitry. The refresh rate is controlled via bits in the
R register.
When the reference oscillator circuit is placed in standby,
an on–chip keep–alive oscillator assists in maintaining the
elevated voltage on the phase detectors. The keep–alive
refresh rate is per the spec table in Section 3F.
Window counters in each of the lock detector circuits
determine the lock detector phase threshold for PLL and
PLL . The window counter divide ratio for the main loop’s lock
detector is controlled via a bit in the N register. The window
counter divide ratio for the secondary loop is not controllable
by the user.
The lock detector window determines a minimum phase
difference which must occur before the Lock Detect pin goes
high. Note that the lock detect signals for each loop drive an
AND gate, which then feeds the LD pin. The LD pin indicates
the condition of both loops, or the one active loop if the other
is in standby. If both loops are in standby, LD is low indicating
unlocked.
If desired, the keep–alive oscillator can be inhibited from
turning on, by placing the multiplier in the inactive state via R
register bits. This causes the phase/frequency detector
voltage to bleed off while in standby, but has the advantage of
achieving the lowest supply current if all other sections of the
chip are shut down.
4E. PHASE/FREQUENCY DETECTORS
Detector for Main Loop
4G. DACs
The two independent 8–bit DACs facilitate crystal
oscillator trimming and PA output power control. They are
also suitable for any general–purpose use.
Each DAC utilizes an R–2R ladder architecture. The
output pins, DAC1 and DAC2, are directly connected to the
ladder; that is, there is no on–chip buffer.
The DAC outputs are determined by the contents of the D
register. When a DAC output is zero scale, it is also in a
low–power mode. The power–on reset (POR) circuit
initializes the DACs in the low–power mode upon power up.
The detector for the main loop senses the phase and
frequency difference between the outputs of the R and N
counters. The detector feeds both a high–current charge
pump with output PD –Hi and a low–current charge pump
out
with output PD –Lo.
out
The charge pumps can be operated in three conventional
manners as controlled by bits in the N register. PD –Lo can
out
be enabled with PD –Hi inhibited. Conversely, PD –Hi
out
out
can be enabled with PD –Lo inhibited. Both outputs can be
out
enabled and tied together externally for maximum charge
pump current. Finally, both outputs can be inhibited. In this
last case, they float. The outputs can also be forced to the
floating state by a bit in the C register. This facilitates
introduction of modulation into the VCO input.
4H. GENERAL–PURPOSE OUTPUTS
There are three outputs which may be used as port
expanders for a microcontroller unit (MCU).
Output A is actually a multi–purpose output with a
push–pull output driver. See Table 2 for details.
Output B is a three–state output. The state of Output B
depends on two bits; one of these bits also controls whether
the main PLL is in standby or not. See Table 5 for details.
Output C is an open–drain output. The state of this output
is controlled by one bit per Table 4. Output C is specified with
a guaranteed ON resistance, and thus, may be used in an
analog fashion.
The charge pumps can be operated in an adapt mode as
controlled by bits in the N register. The bits essentially
program a timer which determines how long PD –Hi is
out
active. After the time–out, PD –Hi floats and PD –Lo
out out
becomes active. In addition, a second set of R and N counter
values can be engaged after the time–out. For more
information, see Table 16 and Section 8, Programmer’s
Guide.
10
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Data is retained in the registers over a supply range of 1.8
5. PIN DESCRIPTIONS
to 3.6 V. The bit–stream formats are shown in Figures 13
through 18.
5A. DIGITAL PINS
Enb, D , and Clk
in
Pins 5, 6, and 7 — Serial Data Port Inputs
LD
Pin 8 — Lock Detectors Output
The Enb input is used to activate the serial interface to
allow the transfer of data to the device. To transfer data to the
device, the Enb pin must be low during the interval that the
data is being clocked in. When Enb is taken back high
(inactive), data is transferred to the appropriate register
depending either on the data stream length or address bits.
The C, Hr, and N registers can be accessed using either a
unique data stream length (BitGrabber) or by using address
bits (Conventional). The D, Hn , and R registers can only be
accessed using address bits. See Table 1.
The bit stream begins with the MSB and is shifted in on the
low–to–high transition of Clk. The bit pattern is 1 byte (8 bits)
long to access the C register, 2 bytes (16 bits) to access the
Hr register, or 3 bytes (24 bits) to access the N register. A bit
pattern of 4 bytes (32 bits) is used to access the registers
when using address bits. The device has double buffers for
storage of the N and R counter divide ratios. One double
buffer is composed of the Hr register which feeds the R
register. An Hr to R register transfer occurs whenever the N
register is written. The other double buffer is the Hn register
which feeds the N register. An Hn to N register transfer
occurs whenever the N register is written. Thus, new divide
ratios may be presented to the R, N , and N counters
simultaneously.
This signal is the logical AND of the lock detect signals
from both PLL and PLL . For the main PLL, the phase
window that defines “lock” is programmable via bit N22. The
phase window for the secondary PLL is not programmable.
If either PLL or PLL is in standby, LD indicates the lock
condition of the active loop only. If both loops are in standby,
the LD output is a static low level.
Each PLL’s lock detector is in the high state when the
respective loop is locked (the inputs to the phase detector
being the same phase and frequency). The lock detect signal
is in the low state when a loop is out of lock. See Figure 19.
Upon power up, the LD pin indicates a not locked
condition. The LD pin is a push–pull CMOS output. If unused,
LD should be left open.
Output A
Pin 9 — Multiple–Purpose Digital Output
Depending on control bits R 21 and R 20, Output A is
selectable by the user as a general–purpose output (either
high or low level), f (output of main reference counter), f
R
R
(output of secondary reference counter), or a phase detector
pulse indicator for both loops. When selected as
general–purpose output, bit C7 determines whether the
output is a high or low level per Table 2. When configured as
Transitions on Enb must not be attempted while Clk is
high. This puts the device out of synchronization with the
microcontroller. Resynchronization occurs whenever Enb is
high (inactive) and Clk is low.
f , f , or phase detector pulse, Output A appears as a
R
R
normally low signal and pulses high.
Output A is a slew–rate limited CMOS totem–pole output.
If unused, Output A should be left open.
Table 1. Register Access
(LSBs are C0, R0, N0, D0, R 0, and N 0)
Number
Access
Type
Accessed
Register
Address
Nibble
Register Bit
Nomenclature
Figure
No.
of
Clocks
BitGrabber
C
Hr
N
—
—
—
$0
$1
$2
$3
$5
$4
8
C7, C6, C5, ..., C0
13
14
15
13
14
15
18
16
17
BitGrabber
16
24
32
32
32
32
32
32
R15, R14, R13, ..., R0
N23, N22, N21, ..., N0
C7, C6, C5, ..., C0
BitGrabber
Conventional
Conventional
Conventional
Conventional
Conventional
Conventional
C
Hr
N
R15, R14, R13, ..., R0
N23, N22, N21, ..., N0
D15, D14, D13, ..., D0
R 23, R 22, R 21, ..., R 0
N 15, N 14, N 13, ..., N 0
D
R
Hn
NOTE: $0 denotes hexadecimal zero, $1 denotes hexadecimal one, etc.
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Table 2. Output A Configuration
voltages above V are clipped at approximately 0.7 V
pos
above V
. If unused, Output C should be left open.
pos
Bit
R 21
Bit
R 20
Bit
C7
Function of Output A
Table 4. Output C Programming
0
0
0
0
0
General–Purpose Output,
Low Level
Bit C5
State of Output C Pin
0
Low level
1
General–Purpose Output,
High Level
(ON resistance per
Electrical Table)
0
1
1
1
0
1
x
x
x
f
f
R
1
High impedance
(leakage per Electrical Table)
R
Phase Detector Pulse
Indicator
Output B
Pin 25 — General–Purpose Digital Output
Mode
Pin 10 — Mode Input
When the Mode pin is tied low (approximately Gnd), the
pair of pins named f /Pol and f /Pol become outputs f
This pin is controllable by bits C6 and C1 as either low
level, high level, or high impedance per Table 5. Note that
whenever the main PLL is placed in standby by bit C1, Output
B is forced to high impedance. The three–state MOSFET
output is slew–rate limited. If unused, Output B should be left
open.
out
out
out
and f . As such, these pins are the divided down reference
out
frequency. The division ratio is controlled by bits per Table 6.
In addition, when Mode is low, the R counter is preceded by
a fixed–divide prescaler. Also, only a crystal may be used at
Table 5. Output B Programming
pins Osc and Osc ; an external reference, such as a TCXO,
b
e
State of
Output B Pin
Condition of
Main PLL
should not be used to drive either pin. The default on the
phase detector polarity is positive. See the summary in
Table 3.
Bit C6
Bit C1
0
0
1
1
0
1
0
1
Low level
High impedance*
High level
Active
Standby*
Active
When the Mode pin is tied high (approximately V
), the
pos
pair of pins named f /Pol and f /Pol become inputs Pol
out
out
and Pol. As such, these pins control the polarity of the
phase/frequency detectors for PLL and PLL, respectively. In
addition, when Mode is high, the R counter is preceded by a
dual–modulus prescaler. Therefore, the R counter is
completely programmable per Figure 16. Also, either a
crystal or TCXO may be used with the device. See the
summary in Table 3.
High impedance
Standby
*Power–up default.
f
/Pol and f /Pol
out
out
Pins 28 and 27 — Dual–purpose Outputs/Inputs
These pins are outputs when the Mode pin is low and
inputs when the Mode pin is high.
Table 3. Mode Pin Summary
When the Mode pin is low, these pins are small–signal
Attribute
Mode Pin = Low Level Mode Pin = High Level
differential outputs f
the signal present at the Osc pin. The frequency of the
output signal is per Table 6. If this function is not needed, the
Mode pin should be tied high, which minimizes supply
current. In this case, these inputs must be tied high or low per
Tables 7 and 8.
and f
with a frequency derived from
out
out
f
/Pol pin Pin is f
output;
out
Pin is Pol input and
controls polarity of
phase detector
out
e
polarity of phase
detector is positive
f
/Pol pin Pin is f
out
output;
polarity of phase
Pin is Pol input and
controls polarity of
phase detector
out
detector is positive
Table 6. f
and f
Frequency
(Mode Pin = Low)
Oscillator
circuit
Supports a crystal only
Supports crystal or
accommodates TCXO
out
out
Bit N23
Bit R 1
Bit R 0
Output Frequency
R counter Programmable in
increments of 2 or 2.5
Programmable in
increments of 0.5
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Osc divided by 10
e
Output B
pin
State of pin controlled
by Bit C6
Pin not used, Bit C6
controls whether
crystal or TCXO is
accommodated
Osc divided by 12.5
e
Osc divided by 12.5
e
Osc divided by 12.5
e
Osc divided by 8
e
Output C
Osc divided by 10
e
Pin 16 — General–Purpose Digital Output
Osc divided by 10
e
This pin is controllable by bit C5 as either low level or high
impedance per Table 4.
The output driver is an open–drain N–channel MOSFET
connected to Gnd. The ESD (electrostatic discharge)
Osc divided by 10
e
protection circuit for this pin is tied to Gnd and V
. Thus,
pos
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When the Mode pin is high, these pins are digital inputs
5C. LOOP PINS
Pol and Pol which control the polarity of the phase/frequency
detectors. See Tables 7 and 8. Positive polarity is used when
an increase in an external VCO control voltage input causes
an increase in VCO output frequency. Negative polarity is
used when a decrease in an external VCO control voltage
input causes an increase in VCO output frequency.
f
and f
in
in
Pins 12 and 13 — Frequency Input for Main Loop (PLL)
These pins feed the on–chip RF amplifier which drives the
high–speed N counter. This input may be fed differentially.
However, it is usually used in a single–ended configuration
with f driven while f is tied to a good RF ground (via a
in
in
Table 7. Main Phase/Frequency Detector Polarity
capacitor). The signal source driving this input must be ac
coupled and originates from an external VCO.
(Mode Pin = High)
The sensitivity of the RF amplifier is dependent on
frequency as shown in the Loop Specifications table.
Main Detector Polarity
(PD
out
–Lo and PD –Hi)
out
Mode Pin
High
Pol Pin
Low
High
*
Sensitivity of the f input is specified as a level across a 50 Ω
in
Positive
load driven by a 50 Ω source. A VCO that can drive a load
High
Negative
Positive
within the data sheet limits can also drive f . Usually, to avoid
in
load pull and resultant frequency modulation of the VCO, f is
in
Low
lightly coupled by a small value capacitor and/or a resistor.
See the applications circuit of Figure 65.
*Pin configured as an output; should not be driven.
Table 8. Secondary Phase/Frequency
Detector Polarity
f
in
Pin 30 — Frequency Input for Secondary Loop (PLL )
(Mode Pin = High)
This pin feeds the on–chip RF amplifier which drives the
high–speed N counter. This input is used in a single–ended
configuration. The signal source driving this input must be ac
coupled and originates from an external VCO.
The sensitivity of the RF amplifier is dependent on
frequency as shown in the Loop Specifications table.
Sensitivity of the f
in
50 Ω load driven by a 50 Ω source. A VCO that can drive a
load within the data sheet limits can also drive f . Usually, to
avoid load pull and resultant frequency modulation of the
Secondary Detector
Polarity
Mode Pin
High
Pol Pin
Low
High
*
(PD )
out
Positive
Negative
Positive
High
input is specified as a level across a
Low
*Pin configured as an output; should not be driven.
in
VCO, f is lightly coupled by a small value capacitor and/or
in
a resistor. See the applications circuit of Figure 65.
5B. REFERENCE PINS
If the secondary loop is not used, PLL should be placed in
Osc and Osc
Pins 1 and 32 — Reference Oscillator Transistor Emitter
and Base
e
b
standby and f should be left open.
in
PD
–Hi and PD –Lo
out
out
Pins 19 and 20 — Phase/Frequency Detector Outputs
for Main Loop (PLL)
These pins can be configured to support an external
crystal in a Colpitts oscillator configuration. The required
connections for the crystal circuit are shown in the Crystal
Oscillator Considerations section.
Each pin is a three–state current source/sink/float output
for use as a loop error signal when combined with an external
Additionally, the pins can be configured to accept an
external reference frequency source, such as a TCXO. In this
low–pass loop filter. Under bit control, PD –Lo has either
one–quarter or one–eighth the output current of PD –Hi per
out
Table 10. The detector is characterized by a linear transfer
function (no dead zone). The polarity of the detector is
controllable. The operation of the detector is described below
and shown in Figure 20.
out
case, the reference signal is ac coupled into Osc and the
e
Osc pin is left floating. See Figure 11.
b
Bit C6 and the Mode input pin control the configuration of
these pins per Table 9.
Table 9. Reference Configuration
Mode
Table 10. Current Ratio of PD
–Hi
out
and PD
–Lo
out
Reference
Configuration
Input
Pin
Output Current Ratio
PD –Hi:PD –Lo
Bit
N18
Bit C6
Comment
out out
(Gain Ratio)
Low
X
Supports Crystal
(default)
C6 used to control
Output B*
0
1
4 : 1
8 : 1
High
High
0
1
Supports Crystal
Output B not useful
Output B not useful
Requires External
Reference
When the Mode pin is high, positive polarity occurs when
the Pol pin is low. Also, when the Mode pin is low, polarity
*See Table 5.
13
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defaults to positive. Positive polarity is described below. f is
the output of the main loop’s VCO divider (N counter). f is
R
the output of the main loop’s reference divider (R counter).
PD
out
V
Pin 23 — Phase/Frequency Detector Output for
Secondary Loop (PLL )
(a) Frequency of f > f or phase of f leading f :
This pin is a three–state voltage output for use as a loop
error signal when combined with an external low–pass loop
filter. The detector is characterized by a linear transfer
function (no dead zone). The polarity of the detector is
controllable. The operation of the detector is described below
and shown in Figure 21.
V
R
V
R
current–sinking pulses from a floating state.
(b) Frequency of f < f or phase of f lagging f :
V
R
V
R
current–sourcing pulses from a floating state.
(c) Frequency and phase of f = f : essentially a floating
V
R
state, voltage at pin determined by loop filter.
When the Mode pin is high, positive polarity occurs when
the Pol pin is low. Also, when the Mode pin is low, polarity
When the Mode pin is high, negative polarity occurs when
the Pol pin is high. Negative polarity is described below. f is
V
defaults to positive. Positive polarity is described below. f is
V
the output of the main loop’s VCO divider (N counter). f is
R
the output of the secondary loop’s VCO divider (N counter).
the output of the main loop’s reference divider (R counter).
f
is the output of the secondary loop’s reference divider (R
R
(a) Frequency of f > f or phase of f leading f :
V
R
V
R
counter.)
current–sourcing pulses from a floating state.
(b) Frequency of f < f or phase of f lagging f :
(a) Frequency of f > f or phase of f leading f
:
:
V
R
V
R
R
V
R
V
R
negative pulses from high impedance.
(b) Frequency of f < f or phase of f lagging f
current–sinking pulses from a floating state.
(c) Frequency and phase of f = f : essentially a floating
V
R
V
V
R
positive pulses from high impedance.
(c) Frequency and phase of f = f : essentially a
state, voltage at pin determined by loop filter.
V
R
These outputs can be enabled and disabled by bits in the
C and N registers. Placing the main PLL in standby (bit C1
= 1) forces the detector outputs to a floating state. In addition,
setting the PD Float bit (bit C4 = 1) forces the detector
outputs to a floating state while allowing the counters to run
for the main PLL. For selection of the outputs, see Table 11.
high–impedance state, voltage at pin determined by
loop filter.
When the Mode pin is high, negative polarity occurs when
the Pol pin is high. Negative polarity is described below. f
is the output of the secondary loop’s VCO divider (N
V
counter). f is the output of the secondary loop’s reference
The phase detector gain (in amps per radian) = PD
current (in amps) divided by 2π.
R
out
counter (R counter.)
If a detector output is not used, that pin should be left
open.
(a) Frequency of f > f or phase of f leading f
:
:
V
R
V
R
positive pulses from high impedance.
(b) Frequency of f < f or phase of f lagging f
V
R
V
R
Table 11. Selection of Main Detector Outputs
negative pulses from high impedance.
(c) Frequency and phase of f = f : essentially a
Bit
Bit
Bit
V
R
high–impedance state, voltage at pin determined by
loop filter.
N21
N20
N19
Result
0
0
0
0
0
0
1
1
0
1
0
1
Both outputs not enabled
This output can be enabled and disabled by bits in the C
register. Placing the secondary PLL in standby (bit C0 = 1)
forces the detector output to a high–impedance state. In
addition, setting the PD Float bit (bit C3 = 1) forces the
detector output to a high–impedance state while allowing the
counters to run for PLL .
PD –Lo enabled
out
PD –Hi enabled
out
Both PD –Lo and PD –Hi
out out
enabled
1
1
1
1
0
0
1
1
0
1
0
1
PD –Hi enabled for 16 f cycles
R
out
only, then PD –Lo enabled
The phase detector gain (in volts per radian) = C
voltage (in volts) divided by 4π.
mult
out
If the secondary loop is not used, PLL should be placed in
standby and PD should be left open.
PD –Hi enabled for 32 f cycles
out
R
only, then PD –Lo enabled
out
out
PD –Hi enabled for 64 f cycles
out
R
only, then PD –Lo enabled
out
5D. ANALOG OUTPUTS
PD –Hi enabled for 128 f
out
R
cycles only, then PD –Lo
out
DAC1 and DAC2
Pins 3 and 4 — Digital–to–Analog Converter Outputs
enabled
NOTES:1. When a detector output is not enabled, it is floating.
These are independent outputs of the two 8–bit D/A
converters. The output voltage is determined by bits in the D
register. Each output is a static level with an output
impedance of approximately 100 kΩ.
2. Setting bit N21 = 1 places the IC in an adapt mode and engages a
timer.
The DACs may be used for crystal oscillator trimming, PA
(power amplifier) output power control, or other
general–purpose use.
If a DAC output is not used, the pin should be left open.
14
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5E. EXTERNAL COMPONENTS
5F. SUPPLY PINS
Rx
DAC V
pos
Pin 17 — Current–Setting Resistor
Pin 2 — Positive Supply Potential for DACs
An external resistor to Gnd at this pin sets a reference
current that is used to determine the current at the
This pin supplies power to both DACs and determines the
full–scale output of the DACs. The full–scale output is
phase/frequency detector outputs PD –Hi and PD –Lo.
A value of 2 kΩ is required.
approximately equal to the voltage at DAC V
. The voltage
out out
pos
applied to this pin may be more, less, or equal to the potential
applied to the V pins. The voltage range for DAC V is
pos pos
C
mult
Pin 21 — Voltage–Multiplier Capacitor
1.8 to 3.6 V with respect to the Gnd pins.
If both DACs are not used, DAC V should be tied to the
pos
same potential as V
.
An external capacitor to Gnd at this pin is used for the
on–chip voltage multiplier circuit. The value of this capacitor
must be greater than 20 times the value of the largest loop
filter capacitor. For example, if the largest loop filter capacitor
on either the main loop or the secondary loop is 0.01 µF, then
pos
V
pos
Pins 11, 24, 26, and 29 — Principal Positive Supply
Potential
a 0.22 µF capacitor could be used on the C
pin.
These pins supply power to the main portion of the chip.
mult
To ensure minimum standby supply current drain, the
voltage potential at the C pin must not be allowed to fall
All V
voltage range for V
pins.
pins must be at the same voltage potential. The
pos
is 1.8 to 3.6 V with respect to the Gnd
mult
pos
below the potential at the V
pins. Therefore, if the
pos
keep–alive oscillator is shut off, the user should tie a large
valueresistor(>10MΩ)betweentheC pinandV . This
resistor should be sized to overcome leakage from C
mult
For optimum performance, all V
pos
pins should be tied
together and bypassed to a ground plane using a
low–inductance capacitor mounted very close to the device.
Lead lengths and printed circuit board traces between the
capacitor and the IC package should be minimized. (The
very–fast switching speed of the device can cause excessive
current spikes on the power leads if they are improperly
bypassed.)
mult
pos
to
Gnd due to the printed circuit board and the external
capacitor. The consequence of not using the resistor is
higher supply current drain in standby. If standby is not used,
the resistor is not necessary. Also, if the keep–alive oscillator
is used, the resistor can be omitted.
C
Gnd
reg
Pin 22 — Regulator Capacitor
Pins 14, 15, 18, and 31 — Ground
An external capacitor to Gnd at this pin is required for the
on–chip voltage regulator. A value of 1 µF is recommended.
Common ground for the device. All Gnd pins must be at
the same potential and should be tied to a ground plane.
15
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6. DETAILED REGISTER DESCRIPTIONS
6A. C REGISTER
16
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C REGISTER BITS
See Figure 13 for C register access and serial data
formats.
PD Float (C3)
This bit controls the phase/frequency detector for the
secondary loop, output PD . When this bit is 0, the
out
secondary phase detector operates normally. When the bit is
1, the output is forced to the floating state which opens the
loop and allows modulation to be introduced into the external
VCO input. During this time, the counters are still active. This
bit is inhibited from affecting the phase detector during a
Out A (C7)
When the Output A pin is selected as a General–Purpose
Output (via bits R 21 = R 20 = 0), bit C7 determines the state
of the pin. When C7 is 1, Output A is forced to a high level.
When C0 is 0 Output A is forced low.
PD
pulse.
out
If the loop is locked prior to C3 being set to 1, the lock
detect signal from the secondary loop continues to indicate
“lock” immediately after PD Float is set to 1. If the phase of
the loop drifts outside the lock detect window, then the lock
detect signal indicates “not locked”. If the loop is not locked,
and PD Float is set to 1, then the lock detect signal from the
secondary loop continues to indicate “not locked”.
When Output A is not selected as a General–Purpose
Output, bit C7 has no function; i.e., C7 is a “don’t care” bit.
Out B/XRef (C6)
Bit C6 is a dual–purpose bit.
When the Mode pin is tied low, C6 and C1 (PLL Stby), can
be used to control Output B. See Table 12. (The reference
circuit defaults to crystal configuration.)
When the Mode pin is tied high, additional control of the
reference circuit is allowed. See Table 13.
Osc Stby (C2)
This bit controls the crystal oscillator and external
reference input circuit. When this bit is 0, the circuit is active.
When the bit is 1, the circuit is shut down and is in the
low–power standby mode. When this circuit is shut down, a
keep–alive oscillator for the voltage doubler is activated,
unless the doubler is shut off via bits in the R register. In the
crystal oscillator mode, when C2 transitions from a 1 to a 0
state, a kick–start circuit is engaged for a few milliseconds.
The kick–start circuit ensures self–starting for a
properly–designed crystal oscillator
Table 12. Out B/XRef Bit with Mode Pin = Low
State of
Output B Pin
Condition of
Main PLL
Bit C6
Bit C1
0
0*
1
0
1*
0
Low level
High impedance*
High level
Active
Standby*
Active
1
1
High impedance
Standby
NOTE
*Power up default.
Whenever C2 is 1, both bits C1 and C0 must be
1, also.
To minimize standby supply current, the voltage multiplier
may be shut down (by bits R 19, R 18, and R 17 being all
zeroes). If this is the case and the voltage multiplier feature is
being used, the user must allow sufficient time for the
phase/frequency detector supply voltage to pump up when
the multiplier is brought out of standby. This “pump up” time is
Table 13. Out B/XRef Bit with Mode Pin = High
Bit C6
Reference Configuration
Supports Crystal*
Accommodates External Reference
0*
1
*Power up default.
dependent on the C
capacitor size. Pump current is
mult
approximately 100 µA. During the pump up time, either the
PLL standby bits C1 and C2 must be 1 or the phase/
frequency detector float bits C3 and C4 must be 1.
Out C (C5)
This bit determines the state of the Output C pin. When C5
is 1, Output C is forced to a high–impedance state. When C5
is 0, Output C is forced low.
PLL Stby (C1)
When set to 1, this bit places the main PLL in the standby
mode for reduced power consumption. PD –Hi and
out
PD Float (C4)
PD –Lo are forced to the floating state, the N and R
out
This bit controls the phase detector for the main loop,
counters are inhibited from counting, the main loop’s input
amp is shut off, the Rx current is inhibited, and the main
phase/frequency detector is shut off. The reference oscillator
circuit is still active and independently controlled by bit C2.
When this bit is programmed to 0, the main PLL is taken
out of standby in two steps. First, the input amplifier is
activated, all counters are enabled, and the Rx current is no
outputs PD –Hi and PD –Lo. When this bit is 0, the main
out out
phase detector operates normally. When the bit is 1, the
outputs are forced to the floating state which opens the loop
and allows modulation to be introduced into the external VCO
input. During this time, the counters are still active. This bit is
inhibited from affecting the phase detector during a PD –Hi
out
or PD –Lo pulse.
out
longer inhibited. Any f and f signals are inhibited from
R
V
If the loop is locked prior to C4 being set to 1, the lock
detect signal from the main loop continues to indicate “lock”
immediately after PD Float is set to 1. If the phase of the loop
drifts outside the lock detect window, then the lock detect
signal indicates “not locked”. If the loop is not locked, and PD
Float is set to 1, then the lock detect signal from the main loop
continues to indicate “not locked”.
toggling the phase/frequency detectors and lock detector at
this time. Second, when the f pulse occurs, the N counter is
R
loaded, and the phase/frequency and lock detectors are
initialized via both flip–flops being reset. Immediately after
the load, the N and R counters begin counting down together.
At this point, the f and f pulses are enabled to the phase
R
V
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and lock detectors, and the phase/frequency detector output
is enabled to issue an error correction pulse on the next f
counter’s prescaler are shut down only when Osc Stby bit C2
is set to 1.
When C0 is reset to 0, PLL is taken out of standby in two
steps. All PLL counters and the input amp are enabled. Any
and f signals are inhibited from toggling the associated
R
and f pulses. (Patent issued on this method.)
V
During standby, data is retained in all registers and any
register may be accessed. When setting or clearing the PLL
Stby bit, other bits in the C register may be changed
simultaneously.
f
R
V
phase/frequency detector at this time. Second, when the f
R
pulse occurs, the N counter is loaded and the phase/
frequency detector is initialized via both flip–flops being
reset. Immediately after the load, the N and R counters
begin counting down together. At this point, the f and f
PLL Stby (C0)
When set to 1, this bit places the PLL section of the chip,
R
V
pulses are enabled to the phase and lock detectors, and the
phase/frequency detector output is enabled to issue an error
correction pulse on the next f and f pulses. (Patent issued
which includes the on–chip f
input amp, in the standby
in
mode for reduced power consumption. PD
is forced to the
out
floating state. The R and N counters are inhibited from
counting and placed in the low–current mode. The exception
is the R counter’s prescaler when the Mode pin is low. The
R
V
on this method.)
During standby, data is retained in all registers, and any
register may be accessed. When setting or clearing the PLL
Stby bit, other bits in the C register may be changed
simultaneously.
R counter’s prescaler remains active along with the f
and
out
pins when PLL is placed in standby (Mode pin = low).
f
out
When the Mode pin is low, the f
pin, f
pin, and R
out
out
18
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6B. Hr REGISTER
19
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6C. N REGISTER
20
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N REGISTER BITS
See Figure 15 for N register access and serial data
formats.
Table 16. Main Phase Detector Control
N21
0
N20
0
N19
0
Result
Both PD –Hi and PD –Lo floating
out out
Control (N23)
0
0
1
PD –Hi floating, PD –Lo enabled
out out
When the Mode pin is low, Control bit N23 determines the
divide ratio of the auxiliary divider which feeds the buffers for
0
1
0
PD –Hi enabled, PD –Lo floating
out out
0
1
1
Both PD –Hi and PD –Lo enabled
out out
the f
and f
pins. See Table 14 for the overall ratio
out
out
1
0
0
PD –Hi enabled and PD –Lo
out out
between Osc and f /f
.
e
out out
floating for 16 f cycles, then PD –Hi
When the Mode pin is high, N23 must be programmed
to 1.
R
out
out
floating and PD –Lo enabled
1
1
1
0
1
1
1
0
1
PD –Hi enabled and PD –Lo
out out
Table 14. Osc to f
Frequency Ratio,
Mode = Low
floating for 32 f cycles, then PD –Hi
e
out
R
out
floating and PD –Lo enabled
out
Osc to f
Frequency Ratio
PD –Hi enabled and PD –Lo
out out
e
out
N23
0
R 1
0
R 0
0
floating for 64 f cycles, then PD –Hi
R
out
floating and PD –Lo enabled
out
10:1
PD –Hi enabled and PD –Lo
out
out
0
0
1
12.5:1
12.5:1
12.5:1
8:1
floating for 128 f cycles, then
R
PD –Hi floating and PD –Lo
0
1
0
out
out
enabled
0
1
1
1
0
0
Current Ratio (N18)
1
0
1
10:1
This bit allows for MCU control of the PD –Hi to
out
–Lo current (or gain) ratio on the main loop
PD
out
phase/frequency detector outputs. See Table 17.
1
1
0
10:1
1
1
1
10:1
Table 17. PD
–Hi to PD –Lo Current Ratio
out
out
LD Window (N22)
PD
Current
–Hi
PD
Current
–Lo
out
out
Bit N22 determines the lock detect window for the main
loop. Refer to Table 15 and Figure 19.
C
C
PD
out
PD
–Hi to
–Lo
mult
mult
Pin = 5 V
Pin = 5 V
out
(Nominal)
(Nominal)
Current Ratio
N18
0
Table 15. Lock Detect Window
LD Window
4:1
8:1
4.4 mA
4.4 mA
1.1 mA
(Approximated)
N22
1
0.55 mA
0
32 Osc periods
e
N Counter Divide Ratio (N17 to N0)
1
128 Osc periods
e
These bits control the N Counter divide ratio or loop
multiplying factor. The minimum allowed value is 992. The
maximum value is 262,143. For ease of programming, binary
representation is used. For example, if a divide ratio of 1000
is needed, the 1000 in decimal is converted to binary
00 0000 0011 1110 1000 and is loaded into the device for
N17 to N0. See Figure 15.
Phase Detector Program (N21, N20, N19)
These bits control which phase detector outputs are active
for the main loop. These bits also control the timer interval
when adapt is utilized for the main loop. See Table 16.
21
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6D. R REGISTER
22
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R REGISTER BITS
ensures that the voltage multiplier is operating at optimum
efficiency. For example, for a system utilizing a 16.8 MHz
reference, bits R 19, R 18, and R 17 should be programmed
as 001 if the user desires to use the voltage multiplier. If the
user does not want to use the multiplier, the bits should be
programmed as 000. In the latter case, only a 0.1 µF bypass
See Figure 16 for R register access and serial data
format.
Y Coefficient (R 23 and R 22)
These bits are programmed per Table 18. Note that for the
MC145181, the bits are always programmed as 00. For
compatibility, the other combinations are reserved for use
with the MC145225 and MC145230.
capacitor is needed at the C
pin and an external
mult
phase/frequency detector supply voltage of 3.6 to 5.25 V
must be provided to the C pin.
mult
Table 20. Voltage Multiplier Control
Table 18. Y Coefficient
Maximum Allowed
Maximum Allowed
Multiplier
State
Frequency at
Frequency at f Pin
in
R 23
R 22
Osc Pin
R 19
R 18
R 17
e
0
0
1
1
0
1
0
1
550 MHz
(not used)
(not used)
(not used)
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
Inactive
Active
Active
Active
—
80 MHz
20 MHz
40 MHz
80 MHz
(for factory evaluation)
Output A Function (R 21 and R 20)
These bits control the function of the Output A pin per
Table 19. When selected as a general–purpose output, bit C7
Test/Rst (R 16)
This bit must be programmed to 0 by the user.
controls the state of the pin. The signals f and f are the
R
R
outputs of the R and R counters, respectively. The selection
as a detector pulse is a test feature.
R Counter Divide Ratio (R 15 to R 0)
These bits control the R counter divide ratio. Thus, these
bits determine the secondary loop’s minimum step size. This
step size is the same as the phase/frequency detector’s
operating frequency which must not exceed 600 kHz.
With the Mode pin tied high, the minimum allowed value is
20. The maximum value is 32,767.5. For ease of
programming, binary representation is used. However, the
binary value must be multiplied by 2. For example, if a divide
ratio of 1000 is needed, the 1000 in decimal is converted to
binary 0000 0011 1110 1000. This value is multiplied by 2
and becomes 0000 0111 1101 0000 and is loaded into the
device for R 15 to R 0. See Figure 16.
Table 19. Output A Function Selection
Function Selected
for Output A
R 21
R 20
0
0
1
1
0
1
0
1
General–Purpose Output
f
R
f
R
Phase/Frequency Detector
Pulse from either loop
With the Mode pin tied low, Table 21 shows the divide
ratios available. There are two formulas for the divide ratio
when Mode is low.
If R 1 R 0 are 00: R Ratio = (Value of R 15 to R 2) x 2.
If R 1 R 0 are 01, 10, 11: R Ratio = (Value of R 15 to R 2)
x 2.5.
V–Mult Control (R 19, R 18, R 17)
These bits control the voltage multiplier per Table 20.
When the multiplier is in the active state, the bits determine
the voltage multiplier’s refresh rate of the capacitor tied to the
C
pin.
mult
When active, the bits should be programmed for the
lowest possible maximum frequency shown in the table. This
23
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Table 21. R Counter Divide Ratios with Mode Pin Tied Low*
R Counter
Divide Ratio
R 15 R 14 R 13 R 12 R 11 R 10
R 9
R 8
R 7
R 6
R 5
R 4
R 3
R 2
R 1
R 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Not Allowed
Not Allowed
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
0
1
1
1
1
1
1
0
0
0
0
0
0
1
0
0
0
1
1
1
0
0
0
1
1
1
1
0
0
1
0
0
1
0
0
1
0
0
1
1
0
1
X
0
1
X
0
1
X
0
1
X
Not Allowed
20
25
25
22
27.5
27.5
24
30
30
26
32.5
32.5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
0
1
32,766
40,957.5
40,957.5
X
* Divide ratios with the Mode pin tied high are shown in Figure 16.
24
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6E. Hn REGISTER
25
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6F. D REGISTER
26
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Figure 19. Lock Detector Operation
One f Period
R
f
vs f
V
R
> LD
< LD
< LD
< LD
< LD
< LD
< LD
> LD
> LD
Phase
Window Window Window Window Window Window Window Window Window
Relationship
Locked
LD
Output
Unlocked
NOTES:
1. Illustration shown is for the main loop and applies when the secondary loop is either phase locked or in
standby. The actual detector outputs for each loop are ANDed together at the LD pin.
2. The secondary loop is similar to the above illustration.
3. The approximate lock detect window for the main loop is either 64 or 256 Osc cycles and is programmable
e
via bit N22. The approximate window for the secondary loop is 64 Osc cycles and is not programmable.
e
4. The LD output is low whenever the phase difference is more than the lock detect window.
5. The LD output is high whenever the phase difference is less than the lock detect window and continues to
be less than the window for 3 f periods or more.
R
LOCK DETECTOR OUTPUT CONDITIONS
f
R
versus f Relation
Lock Detector Output
Microcontroller Action
V
Frequency is the same with phase inside the Static high level output
LD window
Senses high level and no edges, therefore loop
is locked
Frequency is the same with phase outside
the LD window
Static low level output
Senses low level, therefore loop is unlocked
Senses edges, therefore loop is unlocked
Senses low level, therefore loop is unlocked
Frequency is slightly different, thus phase is
changing
Dynamic “chattering” output, output has
transitions
Frequency is grossly different
Static low level output
NOTE: For simplicity, this table applies to the main loop. The secondary loop is similar. The detector outputs feed an AND gate whose output is the LD pin.
27
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Figure 20. PD
out
–Hi and PD
out
–Lo Detector Output Characteristics
f
R
Reference
Osc R)
÷
e
f
V
VCO Feedback
(f N)
÷
in
Source Current
PD –Hi,
*
out
PD –Lo
Float
out
Sink Current
*At this point, when both f and f are in phase, the output source and sink circuits are turned on for a short interval.
R
V
NOTES:
1. The detector generates error pulses during out–of–lock conditions. When locked in phase and frequency, the output is high impedance and
the voltage at that pin is determined by the low–pass filter capacitor.
2. Waveform shown applies when the f
/Pol pin is low and the Mode pin is high.
out
3. When the f
/Pol pin is high and Mode is high, the PD –Hi and PD –Lo waveform is inverted.
out out
out
4. The waveform shown is also the default when the Mode pin is low.
Figure 21. PD
out
Detector Output Characteristics
f
R
Reference
Osc R )
÷
e
f
V
VCO Feedback
(f
÷
N )
in
High Voltage
*
PD
High Z
out
Low Voltage
*At this point, when both f and f are in phase, the output source and sink circuits are turned on for a short interval.
R
V
NOTES:
1. The detector generates error pulses during out–of–lock conditions. When locked in phase and frequency, the output is high impedance
and the voltage at that pin is determined by the low–pass filter capacitor.
2. Waveform shown applies when the f
/Pol pin is low and the Mode pin is high.
waveform is inverted.
4. The waveform shown is also the default when the Mode pin is low.
out
3. When the f
/Pol pin is high and Mode is high, the PD
out
out
28
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Due to the series/parallel arrangement of the equivalent
components, the crystal exhibits two resonances. The first,
sometimes just called resonance, is the series resonance of
7. APPLICATIONS INFORMATION
7A. CRYSTAL OSCILLATOR CONSIDERATIONS
The oscillator/reference circuit may be connected to
operate in either of two configurations. With the Mode pin
placed “high” and bit C6 programmed to 1, the
oscillator/reference circuit of the MC145181 will accept an
external reference input. The external reference signal
the R , C , L branch. The other, sometimes called the
anti–resonance, is the parallel resonance including C . For
o
the series resonance the formula is
s
s
s
1
f =
s
.
2π L C
s
s
should be capacitive, connected to Osc with Osc left
e
b
floating. Commercially available temperature compensated
crystal oscillators (TCXOs) or crystal–controlled data clock
oscillators provide a very stable reference frequency. For
additional information about TCXOs and data clock
oscillators, please consult the Electronic Engineers Master
Catalog, internet web page, or similar publication/service.
The on–chip Colpitts reference oscillator can be selected
by either tying the Mode pin low or by programming the C6 bit
to zero when Mode is high. The oscillator may be operated in
either the fundamental mode, as show by Figure 22, or as an
overtone oscillator. The “kick start” feature ensures reduced
“stalling” of hard–starting crystals.
For parallel resonance, the formula is
1
f =
p
.
L C C
o
s
s
2π
C + C
o
s
As can be seen from this equation, the anti–resonant
frequency is higher than the series resonant frequency. The
ratio between the resonant and anti–resonant frequency can
be found using the formula
∆f
C
s
=
f
2 (C + C )
o s
where
and
Crystal Resonators
∆f = f – f
p
The equivalent circuit of a crystal resonator most
commonly used is shown in Figure 23. The crystal itself is a
specially cut (usually AT for overtone operation) block of
quartz. The dimensions, (shape, thickness, length, and
width) determine the operating characteristics of the crystal.
When deformed and allowed to return naturally to its resting
shape, it is observed to oscillate. This oscillation has the
typical characteristics of a damped oscillation and an
equivalent electrical signal can be found on the surface of the
crystal. In addition, if an equivalent electrical signal is applied
to the crystal, it will be observed to oscillate. The equivalent
s
f + f
s
p
.
f =
2
By exploiting this characteristic, the crystal oscillator
frequency can be tuned slightly. If a capacitor is connected in
series with the crystal operating in the resonance mode, the
frequency will shift upward. If a capacitance is added in
parallel with a crystal operating in an anti–resonant mode, the
frequency will be shifted down.
values for R , L , C , and C can be used to predict the
s
s
s
o
operation of the crystal when used as an electronic oscillator.
Figure 22. Fundamental Mode Oscillator Circuit
M1
+V
R1
Q1
C3
Osc
Osc
b
C2
C1
Frequency Synthesizer
X
e
1
I1
200/800
R2
0
µA
0
M2
0
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Figure 23. Crystal Resonator Equivalent Circuit
Figure 24. Overtone Crystal Equivalent Circuit
L
L1
s
s
C
R
s
C1
R1
s
s
s
s
s
1
2
X
1
1
2
1
2
2
C
o
L3
s
C3
R3
L5
s
C5
R5
X
R
s
s
e
e
1
C
NOTE: Values are supplied by crystal manufacturer (parallel
resonant crystal).
o
Because of the acoustic properties of the crystal
resonator, the crystal “tank” responds to energy not only at its
fundamental frequency, but also at specific multiples of the
fundamental frequency. In the same manner that a shorted or
open transmission line responds to multiples of the
fundamental frequency, the crystal “tank” responds similarly.
A shorted half–wave transmission line (or closed acoustic
chamber) will not only resonate at its fundamental frequency,
but also at odd multiples of the fundamental. These are called
the overtones of the crystal and represent frequencies at
which the crystal can be made to oscillate. The equivalent
circuit of an overtone crystal is shown is Figure 24.
M1R1 and M2R2 provide the ability to start operation with a
higher than normal operating current to stimulate crystal
activity. This “kick start” current is nominally four times the
normal current. An internal counter times the application of
the “kick start” and returns the current to normal after the time
out period.
The mutual conductance (transconductance) of the
transistor Q1 is useful in determining the conditions
necessary for oscillation. The nominal value for the
transconductance is found from the formula
I
e
gm =
26
The components for the appropriate overtone are
represented by 1, 3, and 5. The fundamental components are
represented by 1, and those of importance for the third and
fifth overtones, by 3 and 5.
where Ie is the emitter current in mA.
The operation of the oscillator can be described using the
concept of “negative resistance”. In a normal tuned circuit,
any excitation tends to be dissipated by the resistance of the
circuit and oscillation dies out. The resistive part of the crystal
along with the resistance of the wiring and the internal
resistance of C1, C2, and C3, make up this “damping”
resistance. Some form of energy must be fed back into the
circuit to sustain oscillation. This is the purpose of the
amplifier.
Fundamental Mode
The equivalent circuit for the Colpitts oscillator operating in
the fundamental mode is shown in Figure 25.
C3 is selected to provide a small reduction in the inductive
property of the crystal. In this manner, the frequency of the
oscillator can be “pulled” slightly. The biasing combination of
Figure 25. Fundamental Mode Colpitts Oscillator Equivalent Circuit
M1
+V
R1
Q1
R
C3
st
Osc
Osc
b
C2
C1
Frequency Synthesizer
C1
s
e
I1
200/800
L1
C
R2
s
o
µA
M2
0
R1
s
0
0
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If we define the damping as resistive, we can define the
In determining values for C1, C2, and C3, two limits are
considered. At one end is the relationship of C3 to C2 and
C1. If C3 is made 0 or the reactance of C3 is small compared
to the reactance of C1 and C2, no adjustment of the crystal
frequency is possible. The other limit is the relationship
opposite or regenerative property as negative resistance.
Figure 26 shows the basic circuit of the Colpitts oscillator. C3
has been combined with the crystal elements for simplicity.
For the circuit to oscillate, there must be at least as much
“negative resistance” (regeneration) as there is resistance
(damping). We can define this by deriving the input
impedance for the amplifier.
gm Z
Z
> R
sum
c1 c2
is the sum of resistances in the resonant loop.
where R
sum
Since this equation must be true for the circuit to oscillate, it
is obvious that as the values of C1 and C2 are increased, the
series resistances must be reduced and/or gm increased.
Since gm is a function of device current and there is a
Figure 26. Colpitts Oscillator Basic Circuit
physical limit on how small R
oscillation can no longer be sustained.
can be made, at some point
sum
Normally, it is desirable to choose the “negative
resistance” to be several times greater than the “damping”
resistance to ensure stable operation. A factor of four or five
is a good “rule of thumb” choice.
I
in
Q1
To determine crystal power, the equivalent circuit shown in
Figure 27 can be used. In this case, we are addressing a
condition where the transistor amplifier is operating at the
limit of class A; that is, the device is just at cutoff during the
peak negative excursions. At this point,
C2
C1
V
in
R = gm X
e
X
c1 c2
if the amplitude is constant and the oscillator is stable. For
this to occur, the sum of all resistances in the resonant loop
If a driving signal is defined as V , the resultant current
in
will be equal to R , where R represents the effective
e
e
that flows can be identified as I . The relationship of V to I
is
in
in
in
resistance of I1. This can be written as
R
= R + R = R
s e
V
= I (Z + Z ) – I (Z – βZ
)
c1
sum
st
in in c1
c2
b
c2
and
where R is the crystal resistance and R is the additional
s
st
0 = I (Z ) + I (Z + r )
in c2 c2
distributed resistances within the resonant loop. At the point
where the transistor enters cutoff we have the equation
b
b
where I is the base current of transistor Q1. Solving the two
b
equations and assuming Z << r , the input impedance can
c2
b
v1 + v2
(I – I ) Z + (I + β ) Z
in c2 in ib c1
b
–I
in
=
=
.
be expressed as
X
+ R
X
+ R
e
ls
β = current gain of the transistor. Rewriting:
I (Z – βZ
e
ls
–gm
1
Z
+
in
2
ω C1 C2
C1 C2
jω
)
c1
b
c2
I
in
=
.
C1 + C2
Z
+ Z + X + R
c2 ls e
c1
where ω = 2πf. This is equivalent to the series combination of
a real part whose value is
For oscillation to occur, we must have
+ Z + X 0 .
Z
–gm
c1
c2
ls
REAL =
If we assume βZ is normally much greater than Z then
2
c1 c2
ω C1 C2
–I Z
e
c1
and the imaginary part whose value is
I
.
in
R
e
1
IMAG =
For the condition we have specified,
I (bias) + I (instantaneous ac) = 0
C1 C2
jω
e
e
C1 + C2
the transistor is just cutting off and the peak current, I is
in
To sustain oscillation, the amplifier must generate a
“negative resistance” equal or greater than the REAL part of
the above equation and opposite in polarity.
equal to the bias current. The peak input current is
represented as
I |Z
|
e c1
–gm
I (peak) =
in
.
R
=
neg
R
e
2
ω C1 C2
The power dissipation of the series resistances in the
resonant loop can be written as
As long as the relation
–R
= –SUM (R + R + R + R + R ) ,
st c1 c2 c3
neg
s
2
2
I (peak) R
in
(I |Z |)
e c1
P =
=
the circuit will oscillate and the frequency of oscillation will be
defined as
2
2 R
sum
where R
sum
= R .
e
1
L (C1||C2||C3)
f =
o
The power dissipation for the crystal itself becomes
2π
s
2
(I |Z |)
e c1
P
=
.
crystal
where C3 is the series frequency adjusting capacitor.
2 R
s
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Figure 27. Equivalent Circuit for Crystal Power Estimation
I
in
R1 || R2
l
b
C2
B
lb
L
s
V
x R2 / (R1 + R2)
CC
X
1
R
s
V
CC
I1
200/800
C1
R
e
µA
Overtone Operation
combination of L1 and C1 is capacitive at the overtone
frequency and inductive at the fundamental frequency.
For overtone operation, the circuit is modified by the
addition of an inductor, L1; and a series capacitor, C4. C4 is
inserted as a dc blocking capacitor whose capacitance is
chosen sufficiently large so that its reactance can be ignored.
This circuit is shown in Figure 28.
1
F <
f
< F
o
2π L C
1
1
The net inductance of the rest of the resonant loop then
balances this capacitance at the overtone frequency.
For oscillation to occur at the overtone frequency, the
condition
1
+ X + X
l2
– X
c3
l(stray)
gm Z > R
Z
c1 c2 s
1
1
–
must exist.
represents the impedance across C1 and can be
X
– X
X
ls
cs
c0
Z
c1
defined as
1
–
Z
= jX ||(R + jX )
c1 l1 l1
+
= 0
c1
1
1
where R is the dc resistance of the inductor L1.
l1
X
X
c1
l1
For overtone operation, this must occur at the desired
harmonic. For example, if the crystal is chosen to oscillate at
the third overtone, C1 and C2 must be chosen so that the
above condition exists for Z and Z at the third harmonic of
L2 and C3 are chosen to provide the desired adjustment to
the resonant overtone frequency. This is normally computed
by calculating the expected ppm change at the resonant
frequency and using this to define the value of the reactance
necessary to produce this change.
c1
c2
the fundamental frequency for the crystal. In addition, care
must be taken that the “negative resistance” of the amplifier is
not sufficient at the fundamental frequency to induce
oscillation at the fundamental frequency. It may be necessary
to add additional filtering to reduce the gain of the amplifier at
the fundamental frequency. The key to achieving stable
overtone oscillator operation is ensuring the existence of the
above condition at the desired overtone while ensuring its
failure at all other frequencies.
X (of L2 and C3)
∆F (ppm) =
f
Z (crystal at resonance)
∆F (ppm) = X(of L2 and C3)/Z(crystal at resonance)
f
The values needed for this calculation can be derived from
the value of the fundamental frequency and C . If C is
o
o
known or can be measured, C is defined as
s
L1 and C1 are chosen so that
C
o
1
C =
s
> F
f
200
2π L C
1
1
for an AT cut crystal.
The fundamental frequency can be used to calculate the
where F is the fundamental frequency of the crystal
f
resonator. If L1 and C1 are chosen to be net capacitive at the
desired overtone frequency and if the condition
value for L using either the series resonant or parallel
s
resonant formulas given earlier. Since the Q of the crystal,
gm Z
Z
> R
X
R
c1 c2 s
Q =
is true only at the desired overtone frequency, the oscillator
will oscillate at the frequency of the overtone. Normally, L1
and C1 are not chosen to be resonant at the overtone
frequency but at a lower frequency to ensure that the parallel
is usually sufficiently large at the resonant frequency so that
R << Z(crystal)
s
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R can be ignored. The value for C3 and L2 are chosen so
that
then
s
X
(max) >= 2[∆F (ppm)] Z(crystal)
c3
f
X
= X
l2
c3
and
when C3 is adjusted to approximately half its maximum
capacitance. At this setting, the combination produces a zero
change in the overtone frequency. If C3 is then chosen so
X (max)
c
X (min)=
c
4
that X at minimum capacitance is
This results in an adjustable change in the operating
frequency of +[∆F (ppm)] and –[∆F (ppm)]/2. If ratios nearer
c3
f
f
[X (max)] – X >= ∆F (ppm) Z(crystal)
c3
l2
f
to 1:1 are used for X (max) and X , the tuning range will be
c3 l2
and L2 is approximately
skewed with a wider –[∆F (ppm)] but at the expense of less
f
X
(max)
c3
2
adjustability over the +[∆F (ppm)] range.
f
X
=
I2
Figure 28. Colpitts Oscillator Configured for Overtone Operation
M1
+V
R1
L2
Q1
C3
Osc
Osc
b
e
C2
C1
Frequency Synthesizer
X
1
0
I1
200/800
R2
M2
L1
µA
0
C4
0
0
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7B. MAIN LOOP FILTER DESIGN — CONVENTIONAL
the loop contribution. The loop filter acts as a low–pass filter
to the crystal reference and the loop contribution. The loop
filter acts as a high–pass filter to the VCO with an in–band
gain equal to unity. The loop contribution includes the PLL IC,
as well as noise in the system; supply noise, switching noise,
etc. For this example, a loop contribution of 15 dB has been
selected.
The current output of the charge pump allows the loop
filter to be realized without the need of any active
components. The preferred topology for the filter is illustrated
in Figure 29.
The R /C components realize the primary loop filter. C
o
o
a
is added to the loop filter to provide for reference sideband
suppression. If additional suppression is needed, the R /C
The crystal reference and the VCO are characterized as
high–order 1/f noise sources. Graphical analysis is used to
determine the optimum loop bandwidth. It is necessary to
have noise plots from the manufacturers of both devices.
This method provides a straightforward approximation
suitable for quickly estimating the optimal bandwidth. The
loop contribution is characterized as white–noise or
low–order 1/f noise, given in the form of a noise factor which
combines all the noise effects into a single value. The phase
noise of the crystal reference is increased by the noise factor
of the PLL IC and related circuitry. It is further increased by
the total divide–by–N ratio of the loop. This is illustrated in
Figure 30. The point at which the VCO phase noise crosses
the amplified phase noise of the crystal reference is the point
of the optimum loop bandwidth. In the example of Figure 30,
the optimum bandwidth is approximately 15 kHz.
x
x
realizes an additional filter. In most applications, this will not
be necessary. If all components are used, this results in a
fourth order PLL, which makes analysis difficult. To simplify
this, the loop design will be treated as a second order loop
(R /C ), and additional guidelines are provided to minimize
o
o
the influence of the other components. If more rigorous
analysis is needed, mathematical/system simulation tools
should be used.
Component
Guideline
C
a
R
x
C
x
<0.1 x C
o
>10 x R
o
<0.1 x C
o
To simplify analysis further, a damping factor of 1 will be
selected. The normalized closed loop response is illustrated
in Figure 31 where the loop bandwidth is 2.5 times the loop
natural frequency (the loop natural frequency is the
frequency at which the loop would oscillate if it were
unstable). Therefore, the optimum loop bandwidth is
15 kHz/2.5 or 6.0 kHz (37.7 krads) with a damping
The focus of the design effort is to determine what the
loop’s natural frequency, ω , should be. This is determined by
o
R , C , K , K , and N . Because K , K , and N are given, it is
o
o
p
v
t
p
v
t
only necessary to calculate values for R and C . There are
o
o
three considerations in selecting the loop bandwidth:
1. Maximum loop bandwidth for minimum tuning speed.
coefficient, ζ
1. T(s) is the transfer function of the loop
2. Optimum loop bandwidth for best phase noise
performance.
filter.
where
3. Minimum loop bandwidth for greatest reference
sideband suppression.
N = Total PLL Divide Ratio — 8 x N
t
where (N = 25 ... 40),
K = VCO Gain – 2π Hz/V,
Usually a compromise is struck between these three
cases, however, for a fixed frequency application, minimizing
the tuning speed is not a critical parameter.
v
K = Phase Detector/Charge Pump Gain – A
p
= ( |I
| + |I
| ) / 4π.
OL
OH
To specify the loop bandwidth for optimal phase noise
performance, an understanding of the sources of phase
noise in the system and the effect of the loop filter on them is
required. There are three major sources of phase noise in the
phase–locked loop — the crystal reference, the VCO, and
Technically, K and K should be expressed in radian units
v
p
[K (rad/V), K (A/rad)]. Since the component design
v
p
equation contains the K x K term, the 2π cancels and the
v
p
value can be expressed as AHz/V (amp hertz per volt).
Figure 29. Loop Filter
Xtl
Osc
Ph/Frq
Det
Charge
Pump
R Counter
VCO
R
x
R
C
C
x
o
a
C
o
0
0
N Counter
PLL
0
34
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Figure 30. Graphical Analysis of
Optimum Bandwidth
Figure 31. Closed Loop Frequency Response
for ζ = 1
–60
–70
Natural Frequency
Optimum Bandwidth
10
3 dB Bandwidth
Closed Loop Response
0
–80
–90
VCO
–10
–20
–100
–110
–120
–130
–140
–150
20 x log (N )
t
–30
–40
15 dB NF of the Noise
Contribution from Loop
–50
–60
Crystal Reference
100
0.1
1.0
10
Hz
100
1.0 k
10
1 k
10 k
100 k
1M
Hz
In summary, follow the steps given below:
design. The following describes the use of behavioral
modeling to develop useful models for studying loop filter
performance. In many applications the levels of sideband
spurs can also be studied.
Step 1: Plot the phase noise of crystal reference and the
VCO on the same graph.
Step 2: Increase the phase noise of the crystal reference by
the noise contribution of the loop.
Behavioral modeling is chosen, as opposed to discrete
device modeling, to improve performance and reduce
simulation time. PLL devices can contain several thousand
individual transistors. To simulate at this level can result in
generation of an enormous amount of data when compared
to a simpler behavioral model. For example, a logic NAND
gate can contain several transistors. Each of these requires a
data set for each of the transistor terminals. If a half dozen
transistors are used in the gate design, both current and
voltage measurements for each terminal of each device for
every node in the circuit is calculated. The gate can be
expressed as a behavioral model, which is treated and
simulated as a single device. Since PSpice sees this as a
single rather than multiple devices, the amount of
accumulated data is much less, resulting in a faster
simulation.
For applications using integrated circuits such as PLLs, it
is desirable to investigate the performance of the circuitry
added externally to the integrated circuit. By using behavioral
modeling rather than discrete device modeling to represent
the integrated circuit, the engineer is able to study the
performance of the design without the overhead contributed
by simulating the integrated circuit.
Step 3: Convert the divide–by–N to dB (20log 8 x N) and
increase the phase noise of the crystal reference by
that amount.
Step 4: The point at which the VCO phase noise crosses the
amplified phase noise of the crystal reference is the
point of the optimum loop bandwidth. This is
approximately 15 kHz in Figure 30.
Step 5: Correlate this loop bandwidth to the loop natural
frequency per Figure 31. In this case the 3.0 dB
bandwidth for a damping coefficient of 1 is 2.5 times
the loop’s natural frequency. The relationship
between the 3.0 dB loop bandwidth and the loop’s
“natural” frequency will vary for different values of ζ.
Making use of the equations defined in Figure 32, a
math tool or spread sheet is useful to select the
values for R and C .
o
o
Appendix: Derivation of Loop Filter Transfer Function
The purpose of the loop filter is to convert the current from
the phase detector to a tuning voltage for the VCO. The total
transfer function is derived in two steps.
Step 1 is to find the voltage generated by the impedance of
the loop filter.
Phase Frequency Detector Model
The model for the phase frequency detector is derived
using the waveforms shown in Figure 20. Two signals are
present at the input of the phase frequency detector. These
are the reference input and the feedback from the VCO
and/or prescaler. The two signals are compared to determine
the lag/lead relationship between the two signals and pulses
generated to represent the leading edge of each signal. A
pulse whose width equals the lead of one input signal over
the other is generated by an RS flip–flop (RSFF). One RSFF
generates a pulse whose width equals the lead of the
reference signal over the feedback signal, and a second
RSFF generates a signal whose width is the lead of the
feedback signal over the reference signal. The logical model
for the phase frequency detector is shown in Figure 34.
Step 2 is to find the transfer function from the input of the
loop filter to its output. The “voltage” times the “transfer
function” is the overall transfer function of the loop filter. To
use these equations in determining the overall transfer
function of a PLL, multiply the filter’s impedance by the gain
constant of the phase detector, then multiply that by the
filter’s transfer function. Figure 33 contains the transfer
function equations for the second, third, and fourth order PLL
filters.
PSpice Simulation
The use of PSpice or similar circuit simulation programs
can significantly reduce laboratory time when refining a PLL
35
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Figure 32. Design Equations for the Second Order System
2ζ
ω
o
s + 1
R C s + 1
o o
T(s) =
=
2ζ
NC
1
o
2
2
s +
s + R C s + 1
o o
s + 1
2
K K
p v
ω
ω
o
o
K K
p v
NC
1
2
ω
o
K K
o
p v
ω =
o
C =
o
=
NC
2
o
K K
p v
Nω
o
2ζ
ω R C
2ζ
o o o
R C =
o o
R =
o
ζ =
2
ω C
o o
ω
o
Figure 33. Overall Transfer Function of the PLL
For the Second Order PLL:
For the Third Order PLL:
For the Fourth Order PLL:
V
V
V
V
t
p
p
p
R C s + 1
o o
Z
(s) =
LF
C s
o
R
o
V (s)
C
t
o
o
o
T
(s) =
= 1 , V (s) = K (s)Z (s)
LF
LF
LF
p
p
V (s)
p
V
t
R C s + 1
o o
Z
(s) =
(s) =
2
C R C s + (C + C )s
o o a
o
a
R
C
a
o
C
V (s)
t
T
= 1 , V (s) = K (s)Z (s)
LF
LF
p
p
V (s)
p
V
t
R
C
a
C
x
o
C
(R C s + 1) (R C s + 1)
o o x x
Z
(s) =
(s) =
LF
3
2
C R C R C s + [(C + C )R C + C R (C + C )] s + (C + C + C )s
o o a x x x x o o
o
a
x
a
o
a
x
V (s)
1
t
T
=
,
V (s) = K (s)Z (s)
LF
LF
p
p
V (s)
p
(R C s + 1)
x x
36
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Figure 34. Phase Frequency Detector Logic Diagram
PG1
In
RSFF1
Out
S
R
Ref
R
P1
φ
Pulse Generator
RSFF2
PG2
In
R
S
V
P1
φ
In
Out
Pulse Generator
The behavioral model of the phase frequency detector
shown in Figure 35 is derived using the phase frequency
detector logic diagram. Behavioral models for the pulse
generator, AND gate (Figure 36), and RS flip–flops
(Figure 37) are created using analog behavioral blocks. The
pulse generator is created using a delay block and a “gate”
defined by the behavioral expression:
The terms lead and lag used in this explanation represent
an occurrence in time rather than a phase relationship. At any
condition other than locked, one input (either In or Ref), will
be of a higher frequency. This results in the arrival of the
pulse at that input ahead of the pulse at the other input, or
leading. The second then is lagging.
To simulate the operation of the phase frequency detector
in an actual circuit, a charge pump needs to be added. The
behavioral model for this is shown in Figure 38. Two
voltage–to–current behavioral models are used to produce
the charge pump output. Two voltage–controlled switches
with additional behavioral models, monitor the voltage of the
If [V(v1) ≥ 1 & V(v2) , 1, 5, 0]
v1 and v2 represent the two inputs to the block.
This is the behavioral expression for an AND gate with one
input inverted. The addition of the delay element produces a
pulse whose width equals the delay element.
output of the charge pump and clamp to 0 or V
a real circuit.
to simulate
CC
The pulses appearing at the output of HB1 and HB2
(Figure 35) are used to set the flip–flops, RSFF1, and
RSFF2. The leading pulse will set the appropriate flip–flop
resulting in a high at the output of that flip–flop. The output of
this flip–flop will remain high until the arrival of the second (or
lagging) pulse sets the second RS flip–flop. The presence of
a high on both RS flip–flop outputs results in the generation of
the reset pulse. The reset pulse is generated by the analog
behavioral block (configured as an AND gate) and the delay
element. The delay element is necessary to eliminate the
zero delay paradox of input to output to input.
To ensure the model conforms to the PLL, the delay blocks
in the phase frequency detector should be set to the
expected value as specified by the MC145181 data sheet. In
addition, the charge pump sink and source current behavioral
model should also be set to deliver the desired current and
V
specified to ensure correct clamping.
CC
Modeling the VCO
The VCO (Figure 39) is also modeled using Analog
Behavioral Modeling (ABM). The model used in the following
examples assumes a linear response; however, the control
voltage equation can be modified as desired. The circuit is
modeled as a sine generator controlled by the control
voltage. The sine generator can be modeled using the
EVALUE function or the ABM function. In Figure 39, the
EVALUE function is used to generate the divided output and
the ABM function is used for the undivided output. Either the
GVALUE or the ABM/I function can be used for the control
voltage.
The output of the phase frequency detector is two pulse
trains appearing at R and V . When the PLL is locked, the
φ
φ
pulses in both pulse trains will be of minimum width. When
the phase frequency detector is out of lock, one pulse train
will consist of pulses of minimum width while the width of the
pulses in the second train will be equal to the lead/lag
relationship of the input signals. If the Ref input leads ‘In’, the
pulse train at R will consist of pulses whose width equals the
φ
lead of Ref. If Ref lags ‘In’, the width of the pulses appearing
at V will equal this lag.
φ
37
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Figure 35. Behavioral Model of the Phase Frequency Detector
HB1
V1
RSFF1
S
Delay
In
Out
R
P1
φ
Out
V2
Ref
R
Pulse Generator
If [V(Q1)>=1 & V(Q2)>=1, 5, 0]
Delay
Out
In
RSFF2
Delay
In
HB2
V2
R
Out
In
V
P1
φ
Out
S
V1
Pulse Generator
Figure 36. Behavioral Block Used for the
Pulse Generator
v1
v1
v2
If (V(v1)
≥ 1 | V(v2) < 1, 5, 0)
Out
v2
Figure 37. Behavioral Block Used as an RS Flip–flop
If [V(In1)>=1 & V(In2)<1 | V(In2)<1, 5]
If [V(In2)>=1, 0]
If [V(In3)>=1 & V(In2)<1, 5, 0]
In1
S
R
In2
Q
out
In3
If [V(Q)>=1, 5, 0]
38
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Figure 38. Charge Pump Model
–3
If [V(In1)>=1 V(In2)<1, 1 x 10 , 0]
In1
In2
R
V
φ
0
φ
PD
out
idrive
–3
If [V(In2)>=1 V(In1)<1, 1 x 10 , 0]
0
If [V(idrive) > 0, 0, 1]
S1
+
+
Sbreak
0
–
–
If [V(idrive) < 5, 0, 1]
0
0
S2
+
+
–
–
Sbreak
+
5
–
V1
0
Figure 39. VCO Behavioral Model
VCO
out
1
Parameters:
t
f
k1
6.283
250 x 10
525 x 10
w
c
6
6
sin {t [f time + N v(int)]}
w
c
E1
In+
5 V
0 V
Parameters:
3
Out+
Out–
Out
1 x 10
N
Q
5000
In–
–6
1 x 10
c
evalue
f
c
sin
t
time + v(int)
w
N
0
G1
ctrl
ctrl
+
In+
IC = 0
int
In–
C1
gvalue
k1
–6
1 x 10
99
1 x 10
R1
v(ctrl) Q
c
t
N
w
39
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The equation for the sine generator is:
desired frequency. This frequency should be chosen to
represent the frequency present at the output of the N
counter of the PLL frequency synthesizer.
f
c
e = sin t
time + v(int)
.
w
N
The second output represented by the ABM function is a
sine wave output of the frequency expected from the actual
VCO. The primary purpose of this output is to allow full
frequency simulation for spectrum analysis. By running a
transient analysis of sufficient time, it is possible to determine
spur content and level. If sufficient resolution is used in the
simulation, the PSpice probe FFT transform can be used to
provide the typical spectrum analyzer display.
f is defined as the output frequency when the control voltage
c
is 0. This is the expected VCO frequency before frequency
division. For the purpose of simulation, the counter value, N,
has been written into the equation to ensure the correlation
between the modeled circuit and the mathematical loop filter
calculations. t is 2π; additional decimal places can be added
as needed. v(int) is the control voltage effect and is defined in
these examples as:
w
Loop Filter Simulation
k1
–6
v(cntl) 1 x 10
v(int) =
.
The circuit shown in Figure 40 is used to simulate the
closed loop operation for a single charge pump output.
Component values for the loop filter should be computed
using information from the previous section. Initial conditions
can be set using the “IC1” symbol with starting values
specifying the initial condition.
By adjusting component values for the loop filter,
performance of the closed loop operation can be monitored.
The control voltage to the input of the VCO can be monitored
for a variety of conditions including settling time, lock time,
and ripple present at the VCO input. In addition, the output of
the VCO can be monitored for spur sidebands caused by
ripple on the loop filter output; however, expected operation
at high frequencies may be difficult due to the excessive data
that can be generated.
As the divider ratio, N, increases for a fixed step
frequency, the number of data points required to obtain
sufficient information to overcome aliasing problems may
become excessively large. In addition, the number of
samples required should be three or more per cycle. For
VCO frequencies in the range of 500 MHz, this means the
step ceiling needs to be in the range of 100 to 500 ps. If a
simulation time of 1 ms is needed, the actual computer time
can be several hours with data accumulation in the 1– to
2–Gbyte range.
t N
w
where k1 is the VCO gain in rad/V.
The value C1 in the schematic of the VCO can be
arbitrarily changed; however, the value must match that of
Q . Q determines the value of the current to be integrated by
c
c
99
the capacitor C1. R1 is arbitrarily set to 1 x 10 and is not an
active part of the circuit; however, it must be included to
prevent open pin errors from the PSpice software. The
GVALUE function is used to perform the generation of v(int).
There is some interaction between the integrator, (GVALUE
output and C1) and R1. V(int) is a continuous ramp that is
loaded by the resistance of R1. Unless the GVALUE output
current is sufficiently large for the value chosen for R1, the
VCO control voltage required to maintain lock will increase
throughout the simulation producing nonlinear operation.
Modifications to the circuit can be performed either by
changing the values in the parameter list or for major
changes to the VCO characteristics, the equations for the
sine generator, or control voltage can be altered.
The output of the sine generator is amplified by 1000 to
produce a sharp rise/fall time and the output limited to swing
between the values of 0 V and 5 V to convert it to a digital
output. The resultant circuit/symbol accepts a voltage input
from the loop filter and produces a square wave output at the
Figure 40. PLL Closed Loop Model
HB2
In
HB1
U3
out
+
+
IC = 3.5
IC = 3.5
R
V
R
φ
φ
VCO
R3
V1
ctrl
PD
out
+
–
Out
75 k
0.2 n C1
Ref
V
R4
1 k
0
φ
φ
C3
R1
2 n
C2
0.1 n
7.5 k
0
0
0
0
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7C. MAIN LOOP FILTER DESIGN — ADAPT
S = amount the N counter is being increased (or
z
decreased) by,
Introduction
S = number of f cycles that CPH is active; this value
t
r
For PSpice simulation, the schematic model shown in
Figure 41 was chosen. The classical PLL model employing a
phase–frequency detector, a VCO, and an adaptive loop filter
is used to simplify visualization of circuit operation. The
parameter tables allow for modification of circuit performance
by providing an easy method for altering critical values
without necessitating changes to sub–level schematics. The
definition for the terms are:
is either 16, 32, 64, or 128,
VCPHH = charge pump voltage – high,
VCPHL = charge pump voltage – low,
K1 = VCO gain (Hz/volt),
f = VCO frequency at 0 V control voltage,
c
H = reference spur scaling factor.
Modeling the Phase–frequency Detector
t
w
= 2π,
Figure 42 is a schematic of the phase–frequency detector.
It includes the reference oscillator model, phase–frequency
detector model, and charge pump models. V1 is the control
element used to generate the step time for switching between
CPL and CPH. The signal source VPULSE, is used to
simulate the timer that controls when CPL and CPH are
turned on. PW calculates the pulse width that simulates the
f = reference frequency,
r
t = time delay; allows delay of the start of the high
d
current mode (used to perform reference spur
measurements),
CPL = charge pump low current,
CPH = charge pump high current,
N = N counter value,
counter from the values for S and f that are entered in the
t
r
parameter tables on the top level schematic.
Figure 41. Top Level PLL Model
HB1
ctrl
f N – f
f N – f
r c
K1
r
c
Parameters:
+
IC =
IC =
C4
+
HB2
In
VCO
Out
K1
t
f
H
6.283185308
25 k
1
w
r
R2
PD –Lo
out
R10
1 k
40.2 k
Parameters:
50 p
C1
IC =
330 p
PD –Hi
out
60.4 k
R1
R3
f N – f
r
N
S
29320
400
32
c
0
z
K1
+
+
S
C2
330 p
330 p
t
0
Parameters:
–3
–3
6
CPL
CPH
K1
1 x 10
4 x 10
4 x 10
20 k
C5
IC =
C3
33 p
f N – f
r
K1
c
Parameters:
VCPHH
VCPHL
5
0
10%
3300 p
6
C6
f
727.6 x 10
c
0
Parameters:
0
t
0
d
Figure 42. Phase–frequency Detector with Dual Charge Pumps
In
HB3
HB2
R
HB1
R
V
f
PD –Lo
out
PD –Lo
out
φ
φ
in
Ref
Shift
Ref
V
PD –Hi
out
PD –Hi
out
φ
φ
Shift
Shift
S
t
PW =
V1
4 f
r
+
–
4 t
d
t
=
d
f
r
0
41
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Reference Oscillator
The RS flip–flop equation illustrates the benefit of using
the behavioral block instead of using a primitive logic
element. A delay block and the behavioral gate equation
generate a pulse whose width is equal to the value of the
delay block. To generate the output using a primitive logic
element such as a NAND gate, an inverter would be
necessary to invert one of the NAND inputs. This approach
requires three elements to be used instead of the two of the
behavioral approach just for the pulse generator. In the
behavioral approach, the equation for the behavioral AND
gate is folded into the RS flip–flop, eliminating a separate
gate altogether. Constructing the model with classic logic
elements would require two NOR gates for the flip–flop, a
delay element, an inverter, and an AND gate; five elements
as compared with three for the behavioral approach. Since
the RS flip–flop is used in two places in the model, four less
components are needed for simulation. Since the speed of
the simulation is directly impacted by the number of
components being simulated, any reduction in the total
number of components is a savings in simulation time and
computer memory.
The reference oscillator is shown in Figure 43. The
oscillator is modeled using an analog behavioral block. The
function for the block is written as an “If” condition. If the
signal shift is low, the reference frequency f will be generated
r
if shift is high, a signal of four times f will be generated. The
r
limiter/gain block converts the low level sine wave output of
the analog behavioral block into a square wave. The values
of 0 for the low value and 5 for the high value are used
throughout. These values are chosen out of habit and are not
critical in an analog behavioral environment, providing the
conformity is universal throughout the design.
Figure 43. Reference Oscillator
Shift
Shift
5 V
Ref
1 k
The RS flip–flops generate the lead or lag outputs that are
used to “steer” the VCO. The pulse generator equation
produces narrow pulses coincident with the leading edge of
each of the input signals. These pulses set the appropriate
RS flip–flop. Once set, the leading flip–flop must wait until the
lagging flip–flop is also set. The behavioral AND gate
provides the necessary output pulse to reset the flip–flops.
The delay element placed at the output of the behavioral
AND gate prevents an undefined state for the detector. The
value 5 ns is chosen to correspond with the data sheet. The
logic functions as a three state phase/frequency detector with
an operating range of ±2π. R and V deliver positive pulses,
0 V
If [V(shift) < 1, sin (t f time), sin (t f time) 4]
w r
w r
Phase–frequency Detector
The actual phase–frequency detector model minus
reference oscillator and charge pumps is shown in Figure 44.
The detector is composed of three delay modules: a
behavioral AND gate, and two RS flip–flops. The STP
function resets the phase/frequency detector logic on
initiation of the simulator. The circuit for the behavioral RS
flip–flop is shown in Figure 45.
φ
φ
whose width represents the amount of the lead of each input
over the other input.
Figure 44. Phase–frequency Detector Logic
HB1
In1
Ref
Q1
R
φ
Q
out
In2
If [V(Q1)>=1 & V(Q2)>=1 | V(delay)>=1, 5, 0]
Delay
5 ns
HB2
In1
In2
Q2
V
φ
Q
out
In
Delay
5 STP (5 ns – Time)
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Figure 45. Behavioral RS Flip–flop
If [V(v1)>=1 & V(v2)<1 & V(In2)<1, 5]
U1
If [V(In2)>=1, 0]
V1
V2
Delay
1 ns
If [V(In3)>=1 & V(In2)<1, 5, 0]
In1
In2
In2
Q
Q
out
In3
If [V(Q)>=1, 5, 0]
Charge Pump Model
The other behavioral block is used to generate a VCO
output dependent on the loop, but not contributing to the
operation of the loop. This is used to emulate the actual VCO
output with one modification. “H” has been added to the
equation generating the sine wave. If H is defined as 1, the
sine wave generated will be the same as the expected VCO
output. If H is chosen as some value greater than 1, the
frequency of the output will be reduced accordingly. This is
useful when running simulations designed to show reference
spur levels.
The schematic used for the charge pump in the
phase–frequency detector model is shown in Figure 46. Each
charge pump is made from two analog behavioral blocks.
The blocks chosen are three input behavioral blocks with
current outputs. The two blocks are connected in push–pull
to generate the appropriate source and sink output. The
output of each block is defined using an “If” statement to
monitor the input signals and generate the correct output at
the appropriate time.
In cases where it is desirable to view reference spur levels,
simulation can become difficult or impossible. For example,
consider the circuit that is being discussed. This circuit
represents the evaluation kit (MC145230EVK) using a VCO
tunable between 733 MHz to 742 MHz, with a step frequency
of 25 kHz.
One note about this type of design. SPICE does not limit
the output voltage swing necessary to generate the
programmed current. It is possible to implement values for
the loop filter, which will cause the charge pump to exceed
the rail voltage. To limit the output voltage to prevent
exceeding the value of the rails, the two behavioral blocks,
voltage–controlled switches S1 and S2, and constants
VCPHH and VCPHL are added. S1 and S2 on/off resistance
NOTE
This example is for reference only. The
maximum operating frequency of the MC145181
is 550 MHz. Operation of the VCO at
frequencies greater than 550 MHz requires the
inclusion of additional external division such as a
prescaler.
12
is set to 1 Ω and 1 x 10 Ω, and the off/on voltage is set to
0 V and 1 V to correspond to the behavioral blocks. The
values defined by the constants are accessible from the
parameter tables on the top level schematic.
VCO Model
To obtain useful information from the simulation, a
sampling rate greater than the Nyquist limit must be used
(three to five samples per cycle). This dictates a step size
less than 1/2 nanosecond. Additionally, the reference
frequency is only 25 kHz. To accurately represent the
conditions for spur generation, the simulation time must be
The model used for simulating the VCO is shown in
Figure 47. The VCO is composed of a sine wave generator
and a control element. An analog behavioral block is used as
a sine wave generator and a GVALUE element is used as a
control element. The GVALUE is operated as an integrator.
The output of the integrator is defined as
long enough to include a sufficient number of f periods.
r
v(int) = k1 v(ctrl) Q
.
c
Otherwise, no spurs are generated. In addition, the data file
system is limited to 2 Gbyte, either in the NT 4.0 operating
system or in PSpice itself. If the file exceeds 2 Gbyte, the
data is discarded. To simulate reference spur generation at
730 MHz, a 1 ms simulation time was chosen. The simulation
ran for several hours and generated a data file just under
2 Gbyte. The result is shown in Figure 48. The plot obtained
from the EVK is shown in Figure 49 for comparison.
The block designated to provide the feedback to the
phase–frequency detector uses a single input analog
behavioral block. The signal shift generated by V1 in the
phase–frequency detector block is used to define the output
frequency of the behavioral block. In this manner, the
switching of the N and R values for the programmable
counters can be simulated. In the implementation shown, the
two frequencies will be either 25 kHz or 100 kHz when locked
to the reference oscillator.
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Figure 46. CPL and CPH Charge Pumps
If [V(In1)>=1 & V(In2) <1 & V(shift) <1, CPL, 0]
In1
V
R
φ
In2
0
φ
Shift
PD –Lo
out
Shift
0
If [V(In2)>=1 & V(In1) <1 & V(shift) <1, CPL, 0]
If [V(In1)>=1 & V(In2) <1 & V(shift) >= 1, CPH, 0]
0
drv
PD –Hi
out
0
If (V(In2)>=1 & V(In1)<1 & V(shift) >= 1, CPH, 0)
If [V(idrv) > VCPHH, 1, 0]
S4
+
–
+
–
Sbreak
0
VCPHH
If [V(drv) < VCJPHL, 1, 0]
S5
+
+
–
–
0
VCPHL
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Figure 47. VCO Model
Parameters:
–6
1 x 10
Q
VCO
c
f
time + v(int)
H
c
sin
t
w
t
w
f
f
time + v(int)
time + v(int)
,
If (V(turbo) <1, sin
c
N + S
z
z
4 t
w
sin
c
N + S
5 V
Turbo
Shift
Out
0 V
6
1 x 10
G1
ctrl
ctrl
In+
+
IC = 0
int
In–
gvalue
–6
1 x 10
99
1 x 10
C1
R1
K1 v(ctrl) Q
0
c
Figure 48. Reference Spur Simulation at 730 MHz
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Figure 49. Sybil EVK Reference Spur Measurements
Ref Lvl
– 73.32 dB
10 dBm
25.00000000 MHz
SWT
130 ms
Unit
dBm
1
10
–0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
1AVG
1SA
1
Center 737.5000009 MHz
6.4 kHz
Span 64 kHz
It should be noted that the reference spur values obtained
from the simulation are lower than the values obtained from
the actual EVK. This is because the simulation model is an
“ideal” modeling of the PLL. To obtain results closer to the
actual implementation, the models should be “massaged” to
be more representative of the actual circuit. For example,
spur levels more consistent with actual circuitry can be
obtained by adding a resistance to ground at the input of the
VCO to represent leakage. The value chosen should be
consistent with VCO and circuit component performance.
To reduce simulation time, the H value may be used. By
reducing the frequency of the VCO output, the number of
samples required for simulation can also be reduced. The
output shown in Figure 50 shows the result of dividing the
VCO output of 730 MHz by 7.3 to produce a 100 MHz output.
The reference spurs are better represented since adequate
simulation time is possible.
conditions. These models are starting points for more
accurate implementations.
Loop filter analysis is more accurate, since the
predominate factors are in the loop filter itself. To simulate the
performance of the loop filter, t is set for 0, N is set to the
d
desired divider value, and S is set to the desired step. For
z
this example, 733 MHz was chosen.
NOTE
These values are for reference only. The
maximum operating frequency of the MC145181
is 550 MHz. For VCO frequencies greater than
550 MHz, an added external divider such as a
prescaler is necessary.
With the VCO model shown, V(ctrl) = 0 produces an output
of 727.6 MHz and at V(ctrl) = 1.35 V, the VCO frequency
would be 733 MHz; the minimum MC145230EVK default
operating frequency. To show the response of the loop filter to
To generate these outputs, the parameter values used
were those shown on the top level schematic. The simulator
a 10 MHz step at this operating frequency, S = 10 MHz/
z
25 kHz = 400. The simulation is run for 1 ms with a step
ceiling of 100 ns. The result is shown in Figure 51.
If the simulation is examined over a longer period of time,
the long term settling can be compared to the performance of
the actual circuitry. The plot shown in Figure 52 shows the
VCO control voltage with the display resolution set to 1 mV.
This compares to the plot of frequency variation
measurements made on the actual EVK. This plot is shown in
Figure 53.
was set to run a transient sweep, with t set for a delay that
d
would prevent the 4X frequency from being started. The initial
conditions were set to 1 V and the simulation run for 1 ms.
VCO was monitored and the probe display button FFT was
initiated. The X and Y axis were adjusted to those shown.
Note: These simulations are presented as the result of
“ideal” models and may not accurately display real hardware.
It would be best to load the VCO input with additional leakage
devices such as a large resistance, to accurately display real
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Figure 50. H Set to Generate a 100 MHz Output
Figure 51. 10 MHz Step for an Operating Frequency of 729 MHz
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Figure 52. VCO Settling
Figure 53. Frequency Settling of the EVK
VERTICAL
Freq C
tlk only
waiting for trigger
Center/
Top/
Span
Bottom
742.003715MHz
Center
741.999715MHZ
Span
8.000kHZ
741.999715MHz
1.000k HZ /div
741.995715MHz
Find Center
0.00 s
1.000 ms
200.0 s/div
2.0000 ms
µ
T 742.2
1
µs
T 0.00s
2
∆
–742.2 µs
Find Center
And Span
ref int
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It is noted that the results obtained from the simulation
performed on all, or selected components. By limiting the
circuit to minimum necessary components, simulation can be
performed using only the PSpice evaluation copy. In addition,
the optional PSpice program Optimizer should allow refining
the loop filter more easily.
While PSpice is a powerful tool, it is not without limits.
Since it was designed to run on large mainframe computers,
the PC is just now becoming powerful enough to make use of
the capability of the simulator. A fast Pentium class processor
with a large RAM and a hard drive of the Gbyte size is a
necessity. Even with the most judicious planning, some
simulations will “bump” the limits of the system.
compare favorably to those obtained from the measurements
of the EVK. The simulation display resolution is adjusted to
represent the same ±4 kHz deviation as shown in Figure 53.
Since variation in VCO control voltage is equal to the VCO
frequency divided by the VCO gain, this axis may be
redefined to show change in frequency rather than change in
control voltage.
The models shown represent a “skeleton” that may be
used to develop extensive and reliable simulations that can
greatly reduce actual breadboarding and testing. In addition
to the basic simulations shown, PSpice provides a method by
which worst case and Monte Carlo evaluation can be
49
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7D. SECONDARY LOOP FILTER DESIGN
Seidman, Arthur H., Integrated Circuits Applications
Handbook, Chapter 17, pp. 538–586. New York, John Wiley
& Sons.
Low Pass Filter Design for PD
out
Fadrhons, Jan, “Design and Analyze PLLs on a
Programmable Calculator,” EDN. March 5, 1980.
AN535, Phase–Locked Loop Design Fundamentals,
Motorola Semiconductor Products, Inc., 1970.
AR254, Phase–Locked Loop Design Articles, Motorola
Semiconductor Products, Inc., Reprinted with permission
from Electronic Design, 1987.
AN1207, The MC145170 in Basic HF and VHF Oscillators,
Motorola Semiconductor Products, Inc., 1992.
AN1671, MC145170 PSpice Modeling Kit, Motorola
Semiconductor Products, Inc., 1998.
The design of low pass filtering for PD
out
for the device
can be accomplished using the following design information.
In addition to the example included here, Motorola
Application Note AN1207, also includes examples of active
filtering which may be used to supplement this information.
PD
out
VCO
R
1
R
2
C
Example:
Given the following information:
VCO frequency = 45.555 MHz,
Frequency step size = 5 kHz,
VCO gain = 3.4 MHz/V.
K K
φ VCO
ω =
n
NC(R + R )
1
2
N
Design a loop filter with a damping factor of 0.707.
ζ = 0.5 ω R C +
n
2
K K
φ VCO
The VCO is assumed to have a linear response
throughout the range used in this example. The gain for the
VCO has been given as 3.4 MHz/V and is multiplied by
2π rad/s/Hz for calculating loop filter values.
R sC + 1
2
F(s) =
(R + R )sC + 1
1
2
7
= 2π rad/s/Hz x 3.4 MHz/V = 2.136 x 10 rad/s/V .
K
VCO
The gain for the phase detector is defined as
Definitions:
N = Total Division Ratio in Feedback Loop
V
DD
K (Phase Detector Gain) = V
/ 4π V/radian for PD
/2π V/radian for φ
V
φ
DD
DD
out
K =
V/rad for PD
out
.
φ
4π
K (Phase Detector Gain) = V
φ
and φ
R
Using a value for V
(phase detector supply voltage) of
DD
3.6 V with the output voltage multiplier turned off, the value is
2π∆f
VCO
K
(VCO Gain) =
VCO
3.6
∆V
VCO
K =
φ
= 0.2865 V/rad .
4π
For a nominal design starting point, the user might consider a
damping factor ζ ≈ 0.7 and a natural loop frequency ω
(2πf /50), where f is the frequency at the phase detector
input. Larger ω values result in faster loop lock times and, for
similar sideband filtering, higher f –related VCO sidebands.
Let
≈
n
2π f
r
R
R
ω =
= 628.3 rad/s
45.555 MHz
n
50
n
and
R
F
VCO
Recommended Reading:
N =
=
= 9111 .
F
5 kHz
step size
Gardner, Floyd M., Phaselock Techniques (second
edition). New York, Wiley–Interscience, 1979.
Manassewitsch, Vadim, Frequency Synthesizers: Theory
and Design (second edition). New York, Wiley–Interscience,
1980.
Choosing C = 0.05 µF and calculating R1 + R2,
K K
φ
VCO
R1 + R2 =
= 34 kΩ .
2
N C ω
n
Blanchard, Alain, Phase–Locked Loops: Application to
Coherent Receiver Design. New York, Wiley–Interscience,
1976.
Egan, William F., Frequency Synthesis by Phase Lock.
New York, Wiley–Interscience, 1981.
With a damping factor of 0.707,
0.707
–
N
0.5 ω
K K
φ VCO
n
R2 =
= 15 kΩ ,
C
Rohde, Ulrich L., Digital PLL Frequency Synthesizers
Theory and Design. Englewood Cliffs, NJ, Prentice–Hall,
1983.
Berlin, Howard M., Design of Phase–Locked Loop
Circuits, with Experiments. Indianapolis, Howard W. Sams
and Co., 1978.
R1 = (R2 + R1) – R2 = 34 k – 15 k = 19 kΩ 20 kΩ .
The choice for C is somewhat arbitrary, however, its value
does impact the performance of the loop filter. If possible, a
range of choices for C should be used to calculate potential
loop filters and the resultant filters simulated, as will be
shown below, to determine the best balance.
Kinley, Harold, The PLL Synthesizer Cookbook. Blue
Ridge Summit, PA, Tab Books, 1980.
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If additional filtering is desired, R1 may be split into two
equal resistors and a capacitor to ground inserted. Since the
closest resistance to one–half of 9 k is 4.7 kΩ, this value is
chosen for R1 and R1 . The maximum value for the added
capacitance is based on the bandwidth of the original loop
filter.
junction of R1 and R1 . Using the values defined above, C
a b c
is determined to be
1
C =
c
a
b
R1 R1 + R1 R2
a
b
a
ω
3
(R1 + R2) ω
3
The general form for the transfer function for the passive
filter shown in Figure 54, can be shown to have the form:
1
=
= 10.83 nfd 10 nfd
.
s + ω
R1 R1 + R1 R2
a b a
2
F(s) = K
ω
B
h
(R1 + R2) 10
(s + ω ) (s + ω )
1
3
where
1
Figure 54. Passive Loop Filter for PD
ω =
1
,
out
(R1 + R1 + R2) C
a
b
V
+
IC = 0
1
R1
R1
b
ω =
2
,
a
R2C
1
10 k
10 k
V1
C
10 n
0
c
ω =
3
,
R1 R1 + R1 R2
R2 15 k
a
b
a
C
c
(R1 + R2)
C
50 n
0
where
and
R1 = R1 + R1
a
b
0
ω > ω
3
.
2
Open Loop AC Analysis of the Loop Filter
Since splitting R1 into two equal values, R1 and R1 and
b,
a
inserting the capacitance between the junction of R1 and
a
AC analysis is chosen for the mode of simulation for
PSpice and VSIN is chosen for V1 and is set to produce a 1 V
peak output signal. The simulation is then run and the result
shown in Figure 55.
A Bode plot of the loop filter is obtained which describes
the open loop characteristics of the loop filter. The corner
frequencies of the filter can be modified and the simulation
rerun until the desired wave shape is obtained. Since AC
analysis runs much faster than transient analysis, the AC
open loop analysis of the loop filter is much quicker and
requires less resources than the closed loop transient
analysis.
R1 does not change the position of the pole located at ω ,
b
1
the value of ω remains
1
1
1
ω =
1
=
.
(R1 + R1 + R2) C
(R1 + R2) C
a
b
The 0 identified at ω = 1/R2 C is also unaffected by the
2
addition of C if ω > ω .
c
3
2
Since
R1
2
R1 = R1 =
.
a
b
the value of C can be determined by specifying the value for
c
ω
and using the values already determined for R1 and R2.
3
Closed Loop Filter Simulations Using PSpice
The rule of thumb is to choose ω to be 10 x ω so as not to
3
B
The top level schematic for simulating a simple loop filter
impact the original filter. ω can be found as
B
for PD
operating closed loop, is shown in Figure 56. This
out
filter uses the values calculated above.
2
2 4
(2 + 4ζ + 4ζ )]
ω
= ω
[1 + 2ζ
+
B
n
The schematic represents the PLL function using the
internal phase detector, PD
above, and a VCO. The parameter table allows altering the
divider value of N, the maximum current obtained from
, the loop filter calculated
out
2
ω
= 628.3 rad/s [1 + 2 (0.707)
B
PD
, and PD charge pump voltage from the top level
out
schematic.
out
2 4
(2+ 4 (0.707) + 4 (0.707) )]
+
The schematic for the VCO is shown in Figure 57. Analog
behavioral modeling is used rather than discrete transistor
modeling to reduce component count and improve simulation
efficiency.
3
= 1.293 x 10 rad/s .
3
10 ω = 12.93 x 10 rad/s .
B
The behavioral VCO is composed of an integrator that
transforms the input ctrl into the voltage control V(int) and a
sine wave generator function whose frequency is controlled
by V(int). EVALUE and GVALUE functions are used to
perform the transforms. The analog behavioral models, ABM
and ABMI, can also be used.
The circuit for the passive loop filter is shown in Figure 54.
R1 is split into two equal values and C inserted at the
c
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Figure 55. Bode Plot of the Passive Loop Filter
Figure 56. Passive Loop Filter
HB1
Ctrl
V
+
IC = 0
HB2
Ref
R1
R6
Parameters:
PD
out
Out
CP
N
0.3 mA
9111
10 k
10 k
V2
+
–
C4
10 nf
In
Parameters:
VCPH
VCPL
3.6
0
0
R2 15 k
+
IC = 0
0
C2
50 nf
0
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Figure 57. VCO Behavioral Model
E1
Parameters:
5 V
6
1 x 10
In+
In–
Out+
Out–
Out
t
f
6.283
38.756 x 10
21.36283005 x 10
w
c
6
0 V
6
K1
evalue
f
c
sin
t
time + v(int)
w
Parameters:
1 x 10
N
–6
Q
c
0
G1
In+
ctrl
ctrl
+
IC = 0
int
In–
gvalue
–6
1 x 10
C1
99
1 x 10
R1
k1
v(ctrl) Q
c
t
N
w
G1 performs the operation [k1/(t N)] v(ctrl) Q . This
integrates the input ctrl to produce a voltage ramp used by E1
to produce the desired output. This input is integrated by C1
leading and lagging edges is reflected in the pulse width of
the leading edge flip–flop. The lagging edge flip–flop will
display a narrow pulse equal in width to the value chosen for
the delay at the output of the behavioral AND gate. This
should be programmed to the minimum value as specified by
the data sheet and is usually 5 ns or less.
w
c
whose value should equal Q for most applications. R1 is
c
required by SPICE to prevent a floating node error.
E1 performs the calculations necessary to generate a sine
wave of the desired frequency based on the values listed in
the parameter tables and the value of ctrl. The output of E1 is
Since the outputs R and V are pure logic signals,
φ
φ
additional circuitry is necessary to produce the output PD
.
out
This output should be high impedance when not driving, and
pull either high or low depending on which function (R or V )
is active. The circuitry shown in Figure 61 performs this
function.
6
multiplied by 1 x 10 and limited to 0 and 5 to obtain a square
wave with a fast rise/fall time. Since I/O_STM is a standard
model whose values are 0 and 5, these are used here and in
the phase detector rather than modifying the component
libraries.
φ
φ
To eliminate the need for discrete modeling of PD
,
out
analog behavioral modeling is used. Analog behavioral
blocks ABMI/2, generate a current source/sink output
whenever the appropriate input is high.
The parameter tables provide a convenient method for
setting VCO parameters. t is 2π, f is the zero control
w
c
voltage VCO frequency, and K1 is the VCO gain in rad/s/V.
The sub–schematic for the phase/frequency detector
section of the drawing is shown in Figure 58. This is
composed of two blocks, HB3 and HB4. HB3 performs the
A second set of behavioral blocks monitor the output
idrive, and switch on the appropriate voltage controlled
switch whenever the output rises to the value of V
detector supply voltage) or drops to 0.
(phase
DD
PD
function with HB4 performing the actual phase
out
To model PD
PD
out
, either a model of the transistors used for
must be used or this behavioral arrangement can be
detector operation.
out
The circuit for the phase/frequency detector is shown in
Figure 59. The model is made up of two pulse generators,
two RS flip–flops, and appropriate behavioral gates.
HB1 and HB2 are RS flip–flops. These are constructed
from behavioral blocks as shown in Figure 60. A behavioral
AND gate with a 5 ns delay completes the three state (±2π)
phase/frequency detector. The STP function ensures the RS
flip–flops are reset at initiation.
used. Since the output is specified by a specific output level
and current capability, this arrangement suffices. The output
swing becomes VCPH in the schematic and the current
capability is CP. If a non–zero value is desired for V , the
lo
value VCPL is adjusted from the parameter table on the top
level schematic.
This arrangement allows setting the output voltage swing
To perform the phase detector function, the Ref and f
inputs of the behavioral RS flip–flops are configured to
simulate edge triggered operation. This is achieved by
of PD
by specifying VCPH, the current drive of PD
by
in
out
out
specifying the desired value for CP, and leakage values can
be simulated by setting the appropriate attributes for S1 and
S4 or by adding additional resistance.
placing a 1 ns delay in the Ref and f signal paths. The input
in
and output of the delay are compared by the input behavioral
block and interpreted as a 1 ns pulse. These pulses are used
Simulation
to set HB1 and HB2. If f leads Ref, the In flip–flop, HB2, will
be set first. When Ref leads f , the Ref flip–flop, HB1, will be
in
set first. The lagging edge drives the second flip–flop output
high and the behavioral AND gate then resets both flip–flops.
The delay line at the output of the behavioral AND gate
prevents PSpice from being confused and also completes
the simulation of the phase detector. The outputs of the two
Figures 62 and 63 are the simulation results of running a
transient analysis on the example shown above. The time to
lock from power on is simulated by setting the initial condition
(IC1) to 0 and running the simulation. Figure 62 is the time
versus value of the VCO control voltage. Figure 63 shows the
output at the input of the loop filter and can be used to
determine lock time.
in
RS flip=flops are labeled R and V . The time between the
φ
φ
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Figure 58. Phase/Frequency Detector
HB4
HB3
PD
out
In
f
R
R
PD ′
out
in
φ
φ
Ref
V
V
Ref
φ
φ
Figure 59. Phase Detector Logic
HB1
Ref
In1
In2
Q1
V
φ
Q
out
If [V(Q1)>=1 & V(Q2)>=1 | V(delay)>=1, 5, 0]
U10
Delay
5 ns
HB2
In1
In2
Q2
R
φ
Q
out
In
5 STP (5 ns – Time)
Figure 60. Behavioral RS Flip–flop
If [V(v1)>=1 & V(v2)<1 & V(In2)<1, 5]
U5
If [V(In2)>=1, 0]
V1
V2
Delay
1 ns
If [V(In3)>=1 & V(In2)<1, 5, 0]
In1
In2
In2
Q
Q
out
In3
If [V(Q)>=1, 5, 0]
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Figure 61. R /V to PD
out
Conversion
φ
φ
If (V(In1)>=1 & V(In2)<1, CP, 0)
In1
In2
R
φ
0
V
φ
idrive
PD
out
If (V(In2)>=1 & V(In1)<1, CP, 0)
0
If (V(idrive)>0, 0, 1)
S1
+
+
–
Sbreak
–
0
VCPL
If (V(idrive)<5, 0, 1)
S4
+
+
–
–
Sbreak
0
VCPH
Figure 62. VCO Control Voltage versus Time
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Figure 63. PD
out
at Input to Loop Filter
Summary
attention to VCO modeling, expected output characteristics
can be verified prior to laboratory testing. While simulation
does not replace laboratory testing, it can be used to find
solutions to “what if” questions without the need for extensive
empirical data gathering.
PSpice provides a method by which the performance of
PLL circuitry can be simulated prior to, or in addition to,
laboratory testing. The use of behavioral modeling allows the
creation of simulation circuits that can provide valuable
information for loop filter design and adjustment. By judicious
56
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7E. VOLTAGE MULTIPLIER STALL AVOIDANCE
detectors’ maximum output voltage is determined by the
minimum voltage at C and the headroom required for the
mult
current source. See the following figure.
There are three important criteria to note, highlighted in
the following sections: Allowing for Voltage Build,
Ensuring Valid Counter Programming, and Allowing for
Overshoot. Violation of any of these may cause the voltage
multiplier to collapse. Once the voltage collapses, the loop
goes out of lock and can not recover until the voltage is
allowed to build up again. For an active loop, the voltage
multiplier is designed to maintain the multiplied voltage on the
Voltage at C
mult
Pin
Headroom for Current Source
phase/frequency detector supply pin (C
is active, the multiplier cannot build the voltage.
). If the main loop
mult
Overshoot
Allowing for Voltage Build
After power up, a sufficient time interval must be provided
for the on–chip voltage multiplier to build up the voltage on
Steady–state Control Voltage
the C
pin. During this interval, the phase/frequency
detector outputs for the main loop (PD –Hi and PD –Lo)
mult
out
out
must be inactive (floating outputs). The POR (power–on
reset) circuit forces this “float” condition, thus allowing the
voltage to build on the C
pin.
mult
The duration of the interval to build the voltage is
determined by the external capacitor size tied to the C pin
and the charging current which is 100 µA minimum. The
mult
Time
following formula may be used:
For example, if the main supply voltage (V
the voltage multiplier is utilized, the minimum voltage at C
is 4.75 V. Then, to allow for current source headroom, the
maximum output voltage from the parameter table in Section
) is 3 V and
pos
T = CV/I
mult
where
T is the interval in seconds,
3C is approximately C
– 0.6 V or 4.2 V approximately.
C is the C
capacitor size in farads,
mult
mult
V is the desired voltage on C
Thus, the maximum output overshoot voltage at the
phase/frequency detector outputs should be no more than
4.2 V.
in volts, and
mult
–4
I is the charging current, 1 x 10 amps.
The desired voltage on C is 4 V for a nominal 2 V
mult
Continuing the above example, if the loop is designed with
20% overshoot in the VCO control voltage, then the
overshoot must be subtracted off of the 4.2 V shown above.
Therefore, the upper end of the control voltage to the VCO
must be no more than approximately 3.64 V.
The equations below can be used to determine
constraints:
supply and 5 V for any supply above 2.6 V.
After this interval, the chip can maintain the voltage on the
C
pin and the phase detectors may be safely placed in the
mult
active state.
The interval above also applies when the voltage multiplier
is turned off (with power applied) via bits R 19 R 18 R 17
being 000. After the multiplier is turned back on, sufficient
time must be allowed for the voltage to build on C
mult
case, typically an external resistor does not allow the C
V – 1.2
. In this
φ
∆V ≤
mult
(see Section
2α + 1
voltage to discharge below approximately V
pos
SSV
= V – α (∆V) – 0.6
φ
5E, under C
). Note that if the voltage multiplier is NOT
max
mult
turned off (that is, the above bits are unequal to 000), the
where
keep–alive circuit maintains the multiplied voltage on C
.
mult
∆V is the VCO control voltage range, the maximum minus
the minimum voltage,
Ensuring Valid Counter Programming
V is the minimum phase detector supply voltage (at the
φ
Before the PLLs and/or phase detectors are taken out of
standby, legitimate divide ratios (pertinent to the application)
must be loaded in the registers. For example, proper divide
ratios must be loaded for the R, N, R , and N counters. Also,
proper values for all other bits must be loaded. For example:
selection of crystal or external reference mode must be made
prior to activation of the loops.
After the IC is initialized with the proper bits loaded, the
main loop may then be safely activated via the phase
detector float bit and/or the PLL standby bit being
programmed to 0.
C
pin) per the following table,
mult
α is the control voltage overshoot in decimal; for example,
20% overshoot is 0.2, and
SSV is the maximum allowed steady–state VCO
max
control voltage.
MINIMUM PHASE DETECTOR VOLTAGE
FROM VOLTAGE MULTIPLIER
Supply Voltage,
Minimum Phase Detector
V
pos
Voltage, V
φ
1.8 V
2.0 V
2.5 V
3.6 V
3.32 V
Allowing for Overshoot
3.72 V
The VCO control voltage overshoot for the main loop must
not be allowed to exceed the capability of the phase/
frequency detectors’ maximum output voltage. The
4.75 V
4.75 V
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8. PROGRAMMER’S GUIDE
8A. QUICK REFERENCE
BitGrabber ACCESS OF THE REGISTERS
Enb
D
MSB
LSB
in
Clk
1
2
3
4
8 Clocks to Access the C Register
16 Clocks to Access the Hr Register
24 Clocks to Access the N Register
CONVENTIONAL ACCESS OF THE REGISTERS
Enb
D
in
x
x
x
x
A3
A2
A1
A0
LSB
Clk
4
1
2
3
5
6
7
8
9
10
11
12
32
32 Clocks Always Used
Address
$0 Accesses C Register
$1 Accesses Hr Register
$2 Accesses N Register
$3 Accesses D Register
$4 Accesses Hn
$5 Accesses R
′
Register
′
Register
= when the PLL device loads the data bit.
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8A. QUICK REFERENCE (continued)
C REGISTER
Conventional Access
Don’t Care
Nibble
(Shifted in First)
Least
Significant Nibble
(Shifted in Last)
Address Nibble
A3 A2 A1 A0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
C7 C6 C5 C4
See Below
C3 C2 C1 C0
See Below
0
0
0
0
BitGrabber Access
Most Significant
Nibble
(Shifted in First)
Least
Significant Nibble
(Shifted in Last)
C7 C6 C5 C4
C3 C2 C1 C0
Out A
Out C
PD
PLL
Float
Stby
Out B/Xref PD
Float
Osc
Stby
PLL
Stby
Out A = Output A Pin Logic State
PD′ Float = Phase Detector′ Float
0 = Active, normal operation (power up default)
0 = Pin is forced to 0 (power up default)
1 = Pin is forced to 1
See Note 1
1 = PD ′ is forced to high impedance
out
Osc Stby = Oscillator Standby
0 = Active, normal operation (power up default)
1 = Oscillator/reference circuit in standby
See Note 2
Out B/XRef = Output B Pin Logic State/
External Reference Selection
See table below
Out C = Output C Pin Logic State
0 = Pin is forced to 0 (power up default)
1 = Pin is forced to high impedance
PLL Stby = PLL Standby
0 = Active, normal operation
1 = Main PLL in standby (power up default)
See table below
PD Float = Phase Detector Float
0 = Active, normal operation (power up default)
PLL′ Stby = PLL′ Standby
1 = PD –Hi/PD –Lo are forced to high impedance
0 = Active, normal operation
1 = Secondary PLL in standby (power up default)
out out
NOTES: 1. For the Out A bit to control the Output A pin as a port expander, bits R′21 R′20 must be 00, which selects Output A as a
general–purpose output. If R′21 R′20 are not equal to 00, then the Out A bit is a don’t care.
2. Whenever Osc Stby = 1, both PLL Stby and PLL′ Stby must be 1, also.
Mode Pin and Bit Summary
Mode Pin
Out B/XRef Bit
PLL Stby Bit
Reference Circuit
Xtal Osc mode
Output B Pin Main PLL
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
Z
1
Z
0
Z
1
Z
Active
Standby
Active
Xtal Osc mode
Xtal Osc mode
Xtal Osc mode
Standby
Active
Xtal Osc mode
Xtal Osc mode
Standby
Active
External Reference mode
External Reference mode
Standby
NOTES: Xtal osc = crystal oscillator. Z = high impedance.
59
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8A. QUICK REFERENCE (continued)
Hr REGISTER
Conventional Access
Don’t Care
Nibble
(Shifted in First)
Least
Significant Nibble
(Shifted in Last)
Address Nibble
A3 A2 A1 A0
x
x
x
x
x
x
x
x
x
x
x
x
R15
. . .
R12
R11
. . .
R8
R7
. . .
R4
R3
. . .
R0
0
0
0
1
MSB of R Counter
Divide Value
LSB of R Counter
Divide Value
BitGrabber Access
Most Significant
Nibble
(Shifted in First)
Least Significant
Nibble
(Shifted in Last)
R15
. . .
R12
R11
. . .
R8
R7
. . .
R4
R3
. . .
R0
MSB of R Counter
Divide Value
LSB of R Counter
Divide Value
EXAMPLE: To program the R counter to divide by 1000 in decimal, first multiply 1000 by 2 which is 2000. Convert 2000 to
hexadecimal: $7D0. Then, add leading 0s to form 2 bytes (4 nibbles): $07D0. Finally, load the Hr register bits R15
to R0 with $07D0. When the N register is subsequently loaded, data passes from the first Hr register (buffer) to the
second R register (buffer). (Data is still retained in the Hr register.)
With BitGrabber, no address bits are needed. With a conventional load, address bits A3 to A0 must be included.
NOTE: Hexadecimal numbers are preceded with a dollar sign. For example: hexadecimal 1234 is shown as $1234.
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8A. QUICK REFERENCE (continued)
N REGISTER
Conventional Access
Don’t Care
Nibble
(Shifted in First)
Least
Significant Nibble
(Shifted in Last)
Address Nibble
A3 A2 A1 A0
x
x
x
x
N23
. . .
N20
N19
. . .
N16
N15
. . .
N12
N11
. . .
N8
N7
. . .
N4
N3
. . .
N0
0
0
1
0
See Below
BitGrabber Access
Most Significant
Nibble
(Shifted in First)
Least
Significant Nibble
(Shifted in Last)
N15
. . .
N12
N11
. . .
N8
N7
. . .
N4
N3
. . .
N0
N23 N22 N21 N20
N19 N18 N17 N16
LD
Window
Current
Ratio
LSB of N Counter
Divide Value
Control
Phase Detector
Program
MSB of N Counter
Divide Value
Control = Control for Auxiliary Divider
See Table A
Phase Detector Program = Detector Program for Main Loop
See Table B
LD Window = Lock Detector Window for Main Loop
0 = 32 Osc periods
Current Ratio = PD –Hi to PD –Lo Current Ratio
out out
0 = 4:1
1 = 8:1
e
1 = 128 Osc periods
e
EXAMPLE: To program the N counter to divide by 1000 in decimal, first convert to hexadecimal: $3E8. Then, add leading 0s to form
2 leading bits plus 2 bytes (2 bits plus 4 nibbles); this is N17 to N0. Bits N23 to N18 should be appropriate to control the
above functions. Finally, load the N register. Loading the N register also causes data to pass from the Hr register to the
R register and data from the Hn′ register to pass to the N′ register.
With BitGrabber, no address bits are needed. With a conventional load, address bits A3 to A0 must be included.
Table A. Osc to f
Frequency Ratio,
out
Table B. Main Phase Detector Control
N21 N20 N19 Result
Both PD –Hi and PD –Lo floating
e
Mode = Low
Osc to f
Frequency Ratio
e
out
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
out
out
N23
0
R 1
0
R 0
0
PD –Hi floating, PD –Lo enabled
out out
10:1
PD –Hi enabled, PD –Lo floating
out out
0
0
1
12.5:1
12.5:1
12.5:1
8:1
Both PD –Hi and PD –Lo enabled
out out
0
1
0
PD –Hi enabled and PD –Lo floating
out out
0
1
1
for 16 f cycles, then PD –Hi floating
R
out
and PD –Lo enabled
out
1
0
0
1
1
1
0
1
1
1
0
1
PD –Hi enabled and PD –Lo floating
out out
1
0
1
10:1
for 32 f cycles, then PD –Hi floating
R
out
out
1
1
0
10:1
and PD –Lo enabled
1
1
1
10:1
PD –Hi enabled and PD –Lo floating
out out
NOTE: WhentheModepinishigh, thef
pinsareconfigured
for 64 f cycles, then PD –Hi floating
out
as polarity inputs and N23 must be programmed to 1.
R
out
out
and PD –Lo enabled
PD –Hi enabled and PD –Lo floating
out out
for 128 f cycles, then PD –Hi floating
R
out
and PD –Lo enabled
out
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8A. QUICK REFERENCE (continued)
R′ REGISTER
Conventional Access only
Don’t Care
Nibble
(Shifted in First)
Least
Significant Nibble
(Shifted in Last)
Address Nibble
A3 A2 A1 A0
R′
15
. . .
R
′
12
R′
11
. . .
R′
8
R′
7
. . .
R
′
4
R′
3
. . .
R′0
x
x
x
x
R′
23 R
′
22R
′
21R
′
20
R′19 R′18R′17R′16
0
1
0
1
Y
V–Mult
Control
Test/Rst
MSB of R
Counter Divide
′
LSB of R
Divide Value
′ Counter
Coefficient
Output A
Function
Value
Y Coefficient
V–Mult Control = Voltage Multiplier Control
0 0 0 = Multiplier OFF, 9 MHz ≤ Osc ≤ 80 MHz
0 0 = only programming values allowed
e
0 0 1 = Multiplier ON, 9 MHz ≤ Osc ≤ 20 MHz
e
Output A Function = Controls Output A Mux
0 0 = General–Purpose Output
0 1 0 = Multiplier ON, 20 MHz < Osc ≤ 40 MHz
e
0 1 1 = Multiplier ON, 40 MHz < Osc ≤ 80 MHz
e
0 1 = f
1 0 = f
R
R
′
Test/Rst = Test/Reset
1 1 = Phase Detector pulse
0 = only programming value allowed
EXAMPLE: When the Mode pin is tied low, see Table 21 for R′ counter programming. When the Mode pin is tied high, to program the
R′ counter to divide by 1000 in decimal, first multiply 1000 by 2, which is 2000. Convert 2000 to hexadecimal: $7D0. Then,
add leading 0s to form 2 bytes (4 nibbles); this becomes bits R′15 to R′0. Bits R′23 to R′16 should be appropriate to control
the above functions. Finally, load the R′ register.
With a conventional load, address bits A3 to A0 must be included.
NOTE: Hexadecimal numbers are preceded with a dollar sign. For example: hexadecimal 1234 is shown as $1234.
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8A. QUICK REFERENCE (continued)
Hn′ REGISTER
Conventional Access only
Don’t Care
Nibble
(Shifted in First)
Least
Significant Nibble
(Shifted in Last)
Address Nibble
A3 A2 A1 A0
x
x
x
x
x
x
x
x
N′
15
. . .
N
′
12
N′
11
. . .
N′
8
N′
3
. . .
N′0
x
x
x
x
N′
7
. . .
N
′
4
0
1
0
0
MSB of N
Divide Value
′
Counter
LSB of N
Divide Value
′ Counter
EXAMPLE: To program the N′ counter to divide by 1000 in decimal, first multiply 1000 by 8, which is 8000. Convert 8000 to
hexadecimal: $1F40. Then, add leading 0s (if necessary) to form 2 bytes (4 nibbles). Finally, configure address bits A3
to A0 and load the Hn′ register. When the N register is subsequently loaded, data passes from the first Hn′ register (buffer)
to the second N′ register (buffer). (Data is still retained in the Hn′ register.)
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8A. QUICK REFERENCE (continued)
D REGISTER
Conventional Access only
Don’t Care
Nibble
(Shifted in First)
Least
Significant Nibble
(Shifted in Last)
Address Nibble
A3 A2 A1 A0
x
x
x
x
x
x
x
x
D15
. . .
D12
D11
. . .
D8
D7
. . .
D4
D3
. . .
D0
x
x
x
x
MSB of
DAC2
LSB of
DAC2
MSB of
DAC1
LSB of
DAC1
0
0
1
1
DAC2 Value
DAC1 Value
DAC1 Value = Analog Output Level of DAC1
DAC2 Value = Analog Output Level of DAC2
$00 = zero output
$00 = zero output
$01 = zero + 1 LSB output
$01 = zero + 1 LSB output
$02 = zero + 2 LSBs output
$02 = zero + 2 LSBs output
$03 = zero + 3 LSBs output
$03 = zero + 3 LSBs output
•
•
•
•
•
•
$FD = full scale – 2 LSBs output
$FE = full scale – 1 LSB output
$FF = full scale output
$FD = full scale – 2 LSBs output
$FE = full scale – 1 LSB output
$FF = full scale output
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8B. INITIALIZING THE DEVICE
Introduction
and an external reference is accommodated (Out B/Xref bit
C6 = 1, with the Mode pin high). When the voltage multiplier
is enabled by programming the R register, the voltage is
allowed to build on the C
pin such that a voltage higher
The registers retain data as long as power is applied to the
device. The R and N registers contain counter divide ratios
for the main loop, PLL. The R and N registers contain
counter divide ratios for the secondary loop, PLL . Additional
control bits are located in the R , N, and C registers. The D
register controls the DACs. Section 8A is a handy reference
for register access and bit definitions.
mult
than the main supply voltage is providing power to the
phase/frequency detectors. Both loops are active (PLL Stby
bits C1 = C0 = 0). Also, for this example, Output A and Output
C are programmed low (Out bits C7 = C5 = 0).
In summary, hexadecimal 58 or $58 is serially transferred
(BitGrabber access with no address bits).
The C, D, R , and N registers can be directly written, and
have an immediate impact on chip operation. The Hr and Hn
registers can be directly written, but have no immediate
impact on chip operation. This is because the Hr and Hn
registers are the front–ends of double buffers. The Hr register
feeds the R register. The Hn register feeds the N register.
Changing data in the R and/or N registers is done with a
write to the Hr and/or Hn register, respectively, followed by a
write to the N register. The transfer of data from the Hr to R
and Hn to N registers is triggered with a write to the N
register.
Step 2: Load the R Register
For the secondary loop, the 19.44 MHz reference must be
divided down to 80 kHz by the R counter; the divide ratio is
243. Per Section 8A, the value is doubled to 486. The 16
LSBs of the R register determine the R counter divide ratio.
Therefore, 486 is converted to $01E6 and becomes the 16
LSBs (R 15 to R 0) in the R register. Test/Rst bit R 16 must
be a 0. Bits R 19 to R 17 determine the refresh rate of the
voltage multiplier. The frequency at Osc is <20 MHz.
e
Therefore, per Section 8A, bits R 19 to R 17 must be 001. If
Output A is needed as a MCU port expander, bits R 21 =
R 20 = 0. Per Section 8A, Y Coefficient bits R 23 = R 22 = 0.
In summary, $050201E6 is serially transferred
(conventional access with an address of 0101).
Typically, the Hr and Hn registers are written once, during
initialization after power up. The Hr and Hn registers only
need to be accessed if their data is changing.
An Example
Step 3: Load the Hr Register
Following is an initialization example for a system with a
main loop that covers 450 to 500 MHz in 5 kHz steps. An
external reference of 19.44 MHz is utilized. The secondary
loop is selected to run at 50 MHz. Both VCOs are positive
polarity meaning that when the input control voltage
increases, the output frequency increases. A divided–down
For the main loop, the 19.44 MHz reference must be
divided down to 5 kHz by the R counter; the divide ratio is
3888. Per Section 8A, the ratio 3888 is doubled to 7776 and
then converted to $1E60. The Hr register value is
programmed as $1E60. When the Hr register contents are
transferred to the R register, the R counter divide ratio is
determined.
In summary, $1E60 is serially transferred (BitGrabber
access). This value is transferred from the Hr to the R
register when the N register is accessed in Step 5.
reference is not needed (f
and f ). Therefore, the Mode
out
out
pin is tied to V
pos
and the Pol and Pol pins are tied to ground.
The following initialization gives serial data examples for
BitGrabber access of the C, Hr, and N registers.
Initialization
Step 4: Load the Hn Register
Below is the six–step initialization sequence used after
power up for the example given above.
For the secondary loop, the phase detector is chosen to
run at 80 kHz. Therefore, 80 kHz must be multiplied up to
50 MHz which is a factor of 625. Per Section 8A, the factor is
first multiplied by 8 which equals 5000 and then converted to
$1388. The Hn register is programmed as $1388. When the
Hn register contents are transferred to the N register, the N
counter divide ratio is determined.
Programming the C register first is recommended if the
voltage multiplier is utilized. There are three important criteria
to note. Violation of any criterion may cause the voltage
multiplier to collapse. The first criterion is that after power up,
a sufficient time interval must be provided (after the C and R
registers are initialized) for the on–chip voltage multiplier to
In summary, $04001388 is serially transferred
(conventional access with an address of 0100). The value
$1388 is transferred to the N register when the N register is
accessed in Step 5.
build up the voltage on the C
pin. This interval is
pin
mult
determined by the external capacitor size tied to the C
mult
and the charging current which is about 100 µA. After this
interval, the chip can maintain the voltage on the C pin
mult
and the phase/frequency detectors for the main loop may be
safely activated. The second criterion is that before the
phase/frequency detectors are activated, legitimate divide
ratios (pertinent to the application) must be loaded in the
registers. The third criterion is a hardware issue. The three
criteria are discussed with more detail in Section 7E.
If the voltage multiplier is not used, Step 1 is eliminated
and the initialization sequence starts with Step 2.
Step 5: Load the N Register
For this example, the IC is initialized to tune the lowest end
of the main loop. The lowest end of the main loop’s frequency
range is 450 MHz. Therefore, the 5 kHz must be multiplied up
to 450 MHz which is a factor of 90,000 or $15F90 to be
loaded into bits N17 to N0 of the N register. Bit N18 is
programmed to 0 for a PD –Hi to PD –Lo current ratio of
out out
4:1. If PD –Lo is used for the main loop, bits N21 to N19
out
Step 1: Load the C Register
must be 001. (PD –Lo must be used to initialize the device
out
when
adapt is used, see Section 8D.) Bit N22 = 0 to select a
The C register is programmed such that the main loop’s
phase/frequency detector outputs are floating (PD Float bit
C4 = 1), the reference circuit is active (Osc Stby bit C2 = 0),
lock detect window of approximately 32 / Osc
32/19.44 MHz or 1.6 µs. Bit N23 must be programmed to 1
=
e
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by the user. (When the Mode pin is high, programming N23 to
8D. PROGRAMMING UTILIZING HORSESHOE WITH
a 0 is for Motorola use only.)
ADAPT
In summary, $895F90 is serially transferred (BitGrabber
access). The N register access also causes double–buffer
transfers of Hr to R and Hn to N .
Introduction
A unique adapt feature can be used with the MC145181
when conventional tuning can not meet the lock–time
requirements of a system and the annoying spurs or noise
can not be tolerated from a fractional–N scheme. The adapt
feature is available on the main loop only.
For adapt, a timer is engaged which causes an internal
data update of the R and N registers to be delayed. The IC
supports the Horseshoe scheme for adapt by allowing a
fairly–close quickly–tuned approximate frequency to be
tuned, followed by the tuning of the exact frequency. Two sets
of R and N data are sent to the device. The first set {R1, N1}
is for tuning the approximate frequency. The second set {R2,
N2} is for tuning the exact frequency. Use of the timer delays
the transfer of {R2, N2} until a programmed interval has
elapsed. In addition, after the interval has elapsed, the main
Step 6: Load the C Register
Now that legitimate divide ratios are programmed for the
counters, the main loop may be activated. Thus, the PD float
bit C4 is now programmed to 0. The standby bits are
unchanged: C2 = C1 = C0 = 0. Bit C5 could be used to control
Output C to either a low level or high impedance; for a low
level, C5 = 0. Whenever an external reference is utilized, bit
C6 must be 1. Bit C7 may be used to control Output A to a low
or high level because it is selected as “port expander” by bit
R 21 and R 20; for a low level, C7 = 0.
In summary, $40 is serially transferred (BitGrabber
access). This causes the main loop to tune to 450 MHz, the
secondary loop to tune to 50 MHz, and both the Output A and
Output C pins to be forced low.
loop control switches from PD –Hi to PD –Lo.
out
out
The device is now initialized.
Tuning Near the Top of the Band
Continuing the example, after initializing the device via
steps 1 through 6 in Section 8B, Horseshoe with adapt can
be used to tune the main loop to obtain fast frequency jumps.
Use of the BitGrabber access is recommended to minimize
the number of serial data clocks required for sending the four
“words”.
In this example, the first phase of adapt utilizes
approximate tuning with the phase/frequency detector
running at 4x the step size. Therefore, the approximate
tuning runs the detector at about 20 kHz. The second phase,
with exact tuning, runs the detector at 5 kHz. Horseshoe with
adapt requires that two data sets be serially sent to the
device for every frequency tuned. The first set is for
approximate tuning {R1, N1}; the second set is for exact
tuning {R2, N2}.
Approximate tuning with Horseshoe is unique. This
method involves two key elements: (1) increasing the phase
detector frequency and (2) varying both the R and N divide
values such that the approximate frequency is within a
certain predetermined range. The Horseshoe algorithm
contained in the development system software also allows
placing a constraint on the loop–gain variation that the user
can tolerate.
8C. PROGRAMMING WITHOUT ADAPT
Tuning the Top of the Band
After initializing the device via steps 1 through 6 in Section
8B, the only register that needs to be loaded to tune the main
loop is the N register.
For this example, tuning the upper end of the band
(500 MHz) requires that the 5 kHz at the phase/frequency
detector be multiplied up to 500 MHz. This is a loop
multiplying factor of 100,000. This value is converted to
$186A0 and is loaded for bits N17 to N0. Bits N23 to N18 are
not changed and are programmed as indicated in Section 8B,
step 5.
In summary, $8986A0 is transferred to tune the main loop.
No other registers are loaded.
Tuning Other Channels
Tuning other channels for the main loop, while keeping the
secondary loop at a constant frequency, only requires
programming the N register. See Table 22 for example
frequencies.
For example, to tune 459.97 MHz, the first {R1, N1} data
set could contain divide ratios for the R and N counters of
973.5 and 23,034, respectively. With this data set, the phase
detector is running at about 19.97 kHz and the approximate
frequency is about 170 Hz from the exact frequency. The
second data set contains R and N divide values of 3,888 and
91,994, respectively. This achieves the exact (target)
frequency of 459.97 MHz.
Table 22. Main Loop Tuning Examples
Frequency
Desired
(MHz)
Multiplying
Factor
(Decimal)
Multiplying
Factor
(Hexadecimal) (Hexadecimal)
N Register
Data
450.000
450.005
450.010
450.015
455.000
458.015
471.040
500.000
90,000
90,001
90,002
90,003
91,000
91,603
94,208
100,000
$15F90
$15F91
$15F92
$15F93
$16378
$165D3
$17000
$186A0
$895F90
$895F91
$895F92
$895F93
$896378
$8965D3
$897000
$8986A0
The timer must be programmed to determine the interval
that the device is in the approximate–tune mode. For this
example, assume this is 32 f cycles; thus, bits N21 N20
R
N19 = 1 0 1 in the first data set. Note that this time interval is
32 cycles of f , with the phase detector running at about
R
20 kHz (approximate tune) or about 1.6 ms plus the MCU
shift time shown in Figure 64. Included in the first data set are
N23 = 1 which is required when the Mode pin is high, N22 = 0
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for the lock detect window of 1.6 µs, and N18 = 0 for a current
8E. CONTROLLING THE DACs
ratio of 4:1 (because the phase detector is running at
approximately 4x the step size). Note that bits N23, N22, and
N18 are unchanged from the initialization values.
For the second data set, bits N23, N22, and N18 are
unchanged. Bits N21, N20, and N19 must be programmed as
Introduction
The two 8–bit DACs are independent circuit blocks on the
chip. They have no interaction with other circuits on the chip.
A single 16–bit register, called the D register, holds the binary
value which controls both DACs.
001. This enables PD –Lo for the exact tune after time out.
out
In summary, two data sets need to be sent to the device:
{R1, N1} and {R2, N2}. They are sent in succession as R1,
N1, R2, N2; where R1 is the R register value for the first data
set, N1 is the N register value for the first set, etc. For the
example, these values are {R1, N1} = {$079B, $A859FA} and
{R2, N2} = {$1E60, $89675A}. See Figure 64.
Programming the DACs
A DAC programmed for 0 scale is in the low–power mode.
The 0 scale is programmed as $00 for each 8–bit DAC.
As an example, consider a system that uses just one of the
DACs (DAC 1). The other DAC output is unused and is
programmed for 0 output. If a condition for a system requires
that the DAC have a half–scale output, then DAC 1 is
programmed as $80.
Tuning Other Channels
Tuning other channels for the main loop, while keeping the
secondary loop at a constant frequency, requires sending
two data sets to the part {R1, N1} and {R2, N2}. See Table 23.
In summary, $03000080 is serially transferred
(conventional access with an address of 0011).
Table 23. Main Loop Tuning Using Horseshoe With Adapt
Approximate Tuning
Exact Tuning
Desired
Target
Frequency
(MHz)
Frequency
Error
(Hz)
R1
N1
R2
N2
450.000
450.005
450.020
450.255
459.970
500.000
$0798
$079B
$0798
$0795
$079B
$0798
$A857E4
$A85807
$A857E5
$A857CE
$A859FA
$A861A8
0
548
0
$1E60
$1E60
$1E60
$1E60
$1E60
$1E60
$895F90
$895F91
$895F94
$895FC3
$89675A
$8986A0
162
170
0
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9. APPLICATION CIRCUIT
Figure 65. Application Circuit
Low–pass
Filter
Main
VCO
Secondary
VCO
Low–pass
Filter
V
2 k
pos
24
V
23 22
PD
21
20 19
18
17
General–purpose
(Open–drain)
C
C
PD –Hi
Rx
pos
out′
reg mult
out
PD –Lo
out
Gnd
General–purpose
16
15
14
13
12
25
26
27
28
29
30
(Three–state)
Output C
Gnd
Output B
V
pos
V
pos
/Pol
Gnd
f
out
0.1 µF X7R
0805 SMD or
Smaller
Note 4
f
in
f
/Pol
out
R
SMD
MC145181
V
pos
V
f
0.1
µF X7R
pos
in
V
R
SMD
pos
Note 1
0805 SMD or Smaller
11
10
9
50
Ω
V
pos
f
in
SMD
Note 1
50
SMD
Ω
31
32
Mode
Note 5
Gnd
Osc
General–purpose
(Totem–pole)
Output A
b
DAC
V
Osc
1
DAC1 DAC2 Enb
D
Clk
LD
pos
e
in
2
3
4
5
6
7
8
DAC
Power
(Note 3)
NOTES:1. R should be chosen to achieve the desired isolation. Use of a
capacitor in place of R is possible, but there is the possibility of
phaselocking on VCO harmonics if they fall on thehigh–sensitivity
ReFLEX Codec
or MCU
point of the f or f
input. This is because use of a capacitor in
in in
place of R forms a high–pass filter.
2. V may range from 1.8 to 3.6 V.
pos
3. DAC power may be any potential between 1.8 V and 3.6 V.
4. Configurable pins. See Pin Descriptions.
5. Tie mode to Gnd or V
.
pos
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10. OUTLINE DIMENSIONS
PLASTIC PACKAGE
CASE 873C–01
(LQFP–32)
ISSUE A
D
D
2
0.20
C A–B D
ALL 4 SIDES
D
24
17
b1
BASE METAL
25
16
c
c1
B
A
E
E1
PLATING
b
M
0.08
C A–B D
E1
2
E
32
2
9
SECTION J–J
6
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS. AND
TOLERANCING PER ASME Y14.5M, 1994.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
1
8
0.10
H
A–B
D
D1
2
ALL 4 SIDES
3. DATUMS A, B, AND D TO BE DETERMINED
WHERE THE LEADS EXIT THE PLASTIC BODY AT
DATUM PLANE H.
D1
4. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
mm PER SIDE. D1 AND E1 ARE MAXIMUM
PLASTIC BODY SIZE DIMENSIONS INCLUDING
MOLD MISMATCH.
J
5. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL NOT CAUSE THE LEAD
WIDTH TO EXCEED THE MAXIMUM b DIMENSION
BY MORE THAN 0.08 mm. DAMBAR CAN NOT BE
LOCATED ON THE LOWER RADIUS OR THE
FOOT. MINIMUM SPACE BETWEEN A
PROTRUSION AND AN ADJACENT LEAD IS 0.07
mm.
0.080
C
K
J
C
SEATING
PLANE
4x e/2
28x e
6. EXACT SHAPE OF CORNERS MAY VARY.
MILLIMETERS
DIM
A
A1
A2
b
b1
c
c1
D
MIN
–––
MAX
1.60
0.15
1.45
0.27
0.23
0.20
0.16
0.05
1.35
0.18
0.17
0.10
0.09
2
1
R1
R2
7.00 BSC
A2
D1
E
E1
e
5.00 BSC
7.00 BSC
5.00 BSC
0.50 BSC
A
0.25
H
L
0.45
0.75
L1
R1
R2
S
1.00 REF
0.08
–––
0.20
–––
7
S
A1
0.08
0.20
0
3
L
1
2
3
0
11
11
–––
13
13
L1
DETAIL K
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
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applicationsintended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
ordeathmayoccur. ShouldBuyerpurchaseoruseMotorolaproductsforanysuchunintendedorunauthorizedapplication,BuyershallindemnifyandholdMotorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
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