MC33689DDWBR2 [FREESCALE]
System Basis Chip with LIN Transceiver; 系统基础芯片LIN收发器
| 型号： | MC33689DDWBR2 |
| 厂家： | 
Freescale |
| 描述： | System Basis Chip with LIN Transceiver |
| 文件： | 总31页 (文件大小：519K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: MC33689
Rev. 7.0, 8/2006
Freescale Semiconductor
Technical Data
System Basis Chip with LIN
Transceiver
33689D
The 33689 is a SPI-controlled System Basis Chip (SBC) that
combines many frequently used functions in an MCU-based system
plus a Local Interconnect Network (LIN) transceiver. Applications
include power window, mirror, and seat controls. The 33689 has a
5.0 V, 50 mA low dropout regulator with full protection and reporting
features. The device provide full SPI-readable diagnostics and a
selectable timing watchdog for detecting errant operation.
SYSTEM BASIS CHIP WITH LIN
The LIN transceiver waveshaping circuitry can be disabled for
higher data rates. One 50 mA and two 150 mA high-side switches with
output protection are available to drive inductive or resistive loads. The
150 mA switches can be pulse-width modulated (PWM).
Two high-voltage inputs are available for contact monitoring or as
external wake-up inputs. A current sense operational amplifier is
available for load current monitoring.
DWB SUFFIX
EW SUFFIX (PB-FREE)
98ARH99137A
The 33689 has three operational modes:
• Normal (all functions available)
• Sleep (VDD OFF, wake-up via LIN bus or wake-up inputs)
• Stop (VDD ON, wake-up via MCU, LIN bus, or wake-up inputs)
32-PIN SOICW
Features
ORDERING INFORMATION
Temperature
• Full-Duplex SPI Interface at Frequencies up to 4.0 MHz
• LIN Transceiver Capable to 100 kbps with Waveshaping Capability
• 5.0 V Low Dropout Regulator Full Fault Detection and Protection
• One 50 mA and Two 150 mA Protected High-Side Switches
• Current Sense Operational Amplifier
Device
Package
Range (T )
A
MC33689DDWB/R2
MCZ33689DEW/R2
-40°C to 125°C
32 SOICW
• The 33689 is compatible with LIN 2.0 Specification Package.
• Pb-Free Packaging Designated by Suffix Code EW
V
V
DD PWR
33689
VS1
VS2
VCC
VDD
WDC
HS3
L1
L2
5.0 V
HS1
HS2
CS
SCK
MOSI
MISO
CS
SCLK
MOSI
MISO
INT
RST
IN
OUT
TXD
RXD
MCU
SPI
E+
E-
GND
TGND
AGND
LIN
BUS
Figure 1. 33689 Simplified Application Diagram
Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as
may be required, to permit improvements in the design of its products.
© Freescale Semiconductor, Inc., 2006. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
5.0 V/50 mA
VS1
VDD
RST
Voltage
Regulator
Reset
Control
Window
Watchdog
VS2
HS1
HS2
HS3
WDC
IN
MOSI
MISO
SCLK
CS
SPI
and
Mode
Control
Pre-Driver
INT
VCC
L1
L2
Current
Sense
Op Amp
E-
E+
OUT
VS1
TXD
RXD
LIN
LIN Physical Interface
GND
TGND
AGND
Figure 2. 33689 Simplified Internal Block Diagram
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Analog Integrated Circuit Device Data
Freescale Semiconductor
2
PIN CONNECTIONS
PIN CONNECTIONS
NC
L1
TXD
RXD
INT
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
2
NC
3
CS
L2
4
HS3
HS2
HS1
TGND
TGND
VS2
LIN
5
MISO
MOSI
SCLK
TGND
TGND
IN
6
7
8
9
10
11
12
13
14
15
16
RST
GND
VS1
NC
WDC
E+
E-
OUT
VDD
AGND
VCC
Figure 3. 33689 32-SOICW Pin Connections
Table 1. 33689 32-SOICW Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on page 19.
Pin
Pin Name
Formal Name
Pin Function
Definition
No internal connection to these pins.
1, 3, 14
2, 4
NC
No Connect
N/A
Input
Inputs from external switches or from logic circuitry.
L1, L2
Level Inputs 1 and 2
High-side (HS) drive power outputs. SPI-controlled for driving system
loads.
5–7
HS3–HS1
High-Side Driver
Outputs 3 through 1
Output
Thermal ground pins for the device.
8, 9, 24, 25
TGND
VS2
Thermal Ground
Voltage Supply 2
LIN Bus
N/A
Input
Supply pin for the high-side switches HS1, HS2, and HS3.
10
11
Bidirectional pin that represents the single-wire bus transmitter and
receiver.
LIN
Input/Output
Electrical ground pin for the device.
12
13
GND
VS1
Ground
N/A
Supply pin for the 5.0 V regulator, the LIN physical interface, and the
internal logic.
Voltage Supply 1
Input
Output of the 5.0 V regulator.
15
16
VDD
5.0 V Regulator
Output
Output
N/A
Analog ground pin for voltage regulator and current sense operational
amplifier.
AGND
Analog Ground
5.0 V supply for the internal current sense operational amplifier.
Output of the internal current sense operational amplifier.
Inverted input of the internal current sense operational amplifier.
17
18
19
VCC
OUT
E-
Power Supply In
Amplifier Output
Input
Output
Input
Amplifier Inverted
Input
Non-inverted input of the internal current sense operational amplifier.
Configuration pin for the watchdog timer.
20
21
E+
AmplifierNon-Inverted
Input
Input
Watchdog
Configuration
(Active Low)
Reference
WDC
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Analog Integrated Circuit Device Data
Freescale Semiconductor
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PIN CONNECTIONS
Table 1. 33689 32-SOICW Pin Definitions (continued)
A functional description of each pin can be found in the Functional Pin Description section beginning on page 19.
Pin
Pin Name
Formal Name
Pin Function
Definition
5.0 V regulator and watchdog reset output pin.
22
Reset Output
(Active LOW)
Output
RST
External input PWM control pin for high-side switches HS1 and HS2.
Clock input for the SPI of the 33689.
23
26
27
28
IN
PWM Input Control
Serial Data Clock
Input
Input
SCLK
MOSI
MISO
SPI data received by the 33689.
Master Out Slave In
Master In Slave Out
Input
Output
SPI data sent to the MCU by the 33689. When CS is HIGH, pin is in the
high-impedance state.
SPI control chip select input pin.
29
30
31
32
Chip Select
(Active LOW)
Input
Output
Output
Input
CS
INT
This output pin reports faults to the MCU when an enabled interrupt
condition occurs.
Interrupt Output
(Active LOW)
Receiver output of the LIN interface and reports the state of the bus
voltage.
RXD
TXD
Receiver Output
Transmitter input of the LIN interface and controls the state of the bus
output.
Transmitter Input
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Freescale Semiconductor
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ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Unit
ELECTRICAL RATINGS
Supply Voltage at VS1 and VS2
V
V
PWR
V
SUPDC
-0.3 to 27
40
Continuous
Transient (Load Dump)
V
SUPTR
VDD
Supply Voltage at VDD and VCC
Output Current at VDD
-0.3 to 5.5
Internally Limited
-0.3 to VDD+0.3
-0.3 to VDD+0.3
-0.3 to 7.0
V
A
I
DD
Logic Input Voltage at MOSI, SCLK, CS, IN, and TXD
Logic Output Voltage at MISO, INT, RST, and RXD
Input Voltage at E+ and E-
V
V
INLOG
V
V
OUTLOG
V
/V
V
E+ E-
I
/I
±20
mA
V
Input Current at E+ and E-
E+ E-
Output Voltage at OUT
V
-0.3 to VCC+0.33
±20
OUT
OUT
Output Current at OUT
I
mA
V
Input Voltage at L1 and L2
DC Input with a 33 kΩ Resistor
V
-18 to 40
±100
LXDC
Transient Input with External Component (per ISO7637 Specification) (See
Figure 4, page 6)
V
LXTR
Input/Output Voltage at LIN
DC Voltage
V
V
V
-18 to 40
BUSDC
Transient Input Voltage with specified External Component (per ISO7637
Specification) (See Figure 4, page 6)
V
-150 to 100
BUSTR
DC Output Voltage at HS1 and HS2
V
V
+ 0.3
VS2
HS+
Positive
Internally Clamped
-0.3 to V + 0.3
V
Negative
HS
-
DC Output Voltage at HS3
V
V
V
HS3
VS2
ESD Voltage, Human Body Model (1)
ESD1
V
GND Configured as Ground. TGND and AGND Configured as I/O Pins
LIN, L1, and L2
All Other Pins
±4000
±2000
ESD Voltage, Charge Device Model (1)
Corner Pins (Pins 1, 16, 17, and 32)
All other Pins (Pins 2–15 and 18–31)
ESD2
V
V
±750
±500
Notes
1. ESD1 testing is performed in accordance with the Human Body Model (CZAP =100 pF, RZAP = 1500 Ω), ESD2 testing is performed in
accordance with the Charge Device Model, Robotic (CZAP =4.0 pF).
33689
Analog Integrated Circuit Device Data
Freescale Semiconductor
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ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings(continued)
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Unit
THERMAL RATINGS
Operating Temperature
Ambient
°C
TA
TJ
-40 to 125
-40 to 150
Junction
Storage Temperature
TSTG
-55 to 165
80
°C
°C/W
°C
Thermal Resistance, Junction-to-Ambient
Peak Package Reflow Temperature During Solder Mounting (2)
Notes
R
θJA
T
240
SOLDER
2. Pin soldering temperature is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause permanent damage to the device.
33689D
Transient Pulse
Generator
(Note)
1.0 nF
LIN, L1, L2
10 k
Ω
GND
GND TGND AGND
Note Waveform per ISO 7637-1. Test Pulses 1, 2, 3a, and 3b.
Figure 4. ISO 7637 Test Setup for LIN, L1, and L2 Pins
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Analog Integrated Circuit Device Data
Freescale Semiconductor
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ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C, GND = 0.0 V unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
VS1 AND VS2 INPUT PINS (DEVICE POWER SUPPLY)
Supply Input Voltage
Nominal DC
V
V
SUP
5.5
—
—
—
—
18
40
27
V
Load Dump
SUPLD
Jump Start (3)
—
V
SUPJS
Supply Input Current (4)
I
SUP(NORM)
—
—
—
5.0
35
60
8.0
45
75
mA
µA
µA
Normal Mode, IOUT at VDD = 10 mA, LIN Recessive State
I
SLEEP
Sleep Mode, VDD OFF, V
≤ 13.5 V
SUP
I
STOP
Stop Mode, VDD ON with IOUT < 100 µA, V
≤ 13.5 V
SUP
Input Threshold Voltage (Normal Mode, Interrupt Generated)
Fall Early Warning, Bit VSUV Set
V
VSUVEW
VSOVW
5.7
18
6.1
6.6
Overvoltage Warning, Bit VSOV Set
19.75
20.5
Hysteresis (5)
VSUV Flag
VSOV Flag
HYS
V
—
—
1.0
—
—
V
220
mV
VDD OUTPUT PIN (EXTERNAL 5.0 V OUTPUT FOR MCU USE) (6)
Output Voltage
V
V
V
DDOUT
I
from 2.0 mA to 50 mA, 5.5 V < V
< 27 V
4.75
5.0
5.25
DD
SUP
Dropout Voltage (7)
= 50 mA
DDDROP
V
—
0.1
0.2
I
DD
Output Current Limitation (8)
Overtemperature Pre-warning (Junction)
DD
I
50
120
200
mA
T
°C
PRE
Normal Mode, Interrupt Generated, Bit VDDT Set
Thermal Shutdown (Junction)
Normal Mode
120
165
135
170
160
—
T
°C
SD
Notes
3. Device is fully functional. All features are operating. An overtemperature fault may occur.
4. Total current (I + I ) at VS1 and VS2 pins is measured at the ground pins.
VS1
VS2
5. Parameter guaranteed by design; however, it is not production tested.
6. Specification with external capacitor 2.0 µF < C < 10 µF and 200 mΩ ≤ ESR ≤ 10 Ω. Normal mode. Low ESR electrolytic capacitor values
up to 47 µF can be used.
7. Measured when the voltage has dropped 100 mV below its nominal value.
8. Internally limited. Total 5.0 V regulator current. A 5.0 mA current for the Current Sense Operational Amplifier operation is included.
Digital outputs are supplied from VDD.
33689
Analog Integrated Circuit Device Data
Freescale Semiconductor
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ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C, GND = 0.0 V unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
VDD OUTPUT PIN (5.0 V OUTPUT FOR MCU USE) (CONTINUED) (9)
Temperature Threshold Difference
T
°C
V
DIFF
Normal Mode (T - T
)
20
30
—
40
—
SD
PRE
V
Range for Reset Active
V
SUPR
SUP
4.0
0.5 V < V < V (V
)
DD
DD
RSTTH
Line Regulation
5.5 V < V
V
mV
mV
LR1
LD1
< 27 V, I = 10 mA
—
—
20
10
150
150
SUP
DD
Load Regulation
V
1.0 mA < I < 50 mA
DD
VDD OUTPUT PIN IN STOP MODE
Output Voltage (10)
V
I
V
DDS
4.75
4.0
5.0
8.0
5.25
14
I
≤ 2.0 mA
DD
Output Current Capability (11)
Line Regulation
mA
mV
DDS
V
LRS
5.5 V < V
< 27 V, I = 2.0 mA
DD
—
—
10
40
100
150
SUP
Load Regulation
V
mV
LDS
1.0 mA < I < 5.0 mA
DD
RST OUTPUT PIN IN NORMAL AND STOP MODES
Reset Threshold Voltage
V
4.5
0.0
—
4.7
—
VDD-0.2
0.9
V
V
RSTTH
Low-Level Output Voltage
V
OL
I
= 1.5 mA, 4.5 V < V
< 27 V
O
SUP
High-Level Output Current
0.0 V < V < 0.7VDD
I
µA
OH
-275
—
—
OUT
Reset Pulldown Current
Internally Limited, VDD < 4.0 V, V
I
mA
PDRST
= 4.6 V
1.5
8.0
RST
IN INPUT PIN
Low-Level Input Voltage
High-Level Input Voltage
V
-0.3
—
—
0.3VDD
V
V
IL
IH
IN
V
0.7VDD
VDD +0.3
Input Current
I
µA
0.0 V < VIN < VDD
-10
—
10
Notes
9. Specification with external capacitor 2.0 µF < C < 10 µF and 200 mΩ ≤ ESR ≤ 10 Ω. Normal mode. Low ESR electrolytic capacitor values
up to 47 µF can be used.
10. When switching from Normal mode to Stop mode or from Stop mode to Normal mode, the voltage can vary within the output voltage
specification.
11. When I
is above I
, the 33689 enters the Reset mode.
DDS
DD
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Analog Integrated Circuit Device Data
Freescale Semiconductor
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ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C, GND = 0.0 V unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
MISO SPI OUTPUT PIN
Low-Level Output Voltage
V
V
V
OL
OH
HZ
I
= 1.5 mA
0.0
VDD - 0.9
-2.0
—
—
—
1.0
VDD
2.0
OUT
High-Level Output Voltage
= 250 µA
V
I
OUT
Tri-Stated MISO Output Leakage Current
0.0 V < V < VDD
I
µA
MISO
MOSI, SCLK, CS SPI INPUT PINS
Low-Level Input Voltage
V
-0.3
—
—
0.3 VDD
V
V
IL
High-Level Input Voltage
V
0.7VDD
VDD +0.3
IH
I
µA
Pullup Input Current on CS
PUCS
-100
-10
—
—
-20
10
V
= 4.0 V
CS
MOSI, SCLK Input Current
0.0 V < VIN < VDD
I
µA
IN
INT OUTPUT PIN
Low-Level Output Voltage
V
V
V
OL
I
= 1.5 mA
0.0
—
—
0.9
O
High-Level Output Voltage
= -250 µA
V
OH
I
VDD -0.9
VDD
O
WDC PIN
External Resistor Range
HS1 AND HS2 HIGH-SIDE OUTPUT PINS
Output Clamp Voltage
REXT
10
—
—
100
—
kΩ
V
V
CL
I
= -100 mA
-6.0
OUT
Output Drain-to-Source ON Resistance
R
Ω
DS(ON)
T
T
T
= 25°C, I
-150 mA
OUT
—
—
—
2.0
—
2.5
4.5
4.0
A
A
A
= 125°C, I
= 125°C, I
-150 mA
-120 mA
OUT
OUT
3.0
Output Current Limitation
I
300
155
—
430
—
600
190
10
mA
°C
LIM
Overtemperature Shutdown (12)
Output Leakage Current
OTSD
T
I
—
µA
LEAK
Notes
12. When overtemperature occurs, switch is turned off and latched off. Flag is set in SPI Register. Refer to description on page 26.
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Freescale Semiconductor
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ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C, GND = 0.0 V unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
HS3 HIGH-SIDE OUTPUT PIN
Output Drain-to-Source ON Resistance
Symbol
Min
Typ
Max
Unit
R
Ω
DS(ON)
T
T
T
= 25°C, I
-50 mA
-50 mA
—
—
—
5.5
—
7.0
10
14
A
A
A
OUT
= 125°C, I
= 125°C, I
OUT
10
-30 mA
OUT
Output Current Limitation
I
60
155
—
100
—
mA
°C
200
190
10
LIM
Overtemperature Shutdown (13)
Output Leakage Current
OTSD
T
I
—
µA
LEAK
OUT, E+, AND E- PINS AT CURRENT SENSE OPERATIONAL AMPLIFIER
Input Voltage – Rail-to-Rail at E+ and E-
VIMC
-0.1
—
V
V
VCC +0.1
Output Voltage Range at OUT
VOUT
0.1
0.3
—
—
With ±1.0 mA Output Load Current
With ± 5.0 mA Output Load Current
VCC - 0.1
VCC - 0.3
Input Bias Current
IB
VIO
IO
—
-15
—
—
—
nA
mV
nA
250
15
Input Offset Voltage
Input Offset Current
-100
100
L1 AND L2 INPUT PINS
Low-Voltage Detection Input Threshold Voltage
V
V
V
THL
THH
HYS
5.5 V < V
6.0 V < V
< 6.0 V
< 18 V
< 27 V
2.0
2.5
2.7
2.5
3.0
3.2
3.0
3.5
3.7
SUP
SUP
SUP
18 V < V
High-Voltage Detection Input Threshold Voltage
V
5.5 V < V
6.0 V < V
< 6.0 V
< 18 V
< 27 V
2.7
3.0
3.5
3.3
4.0
4.2
3.8
4.5
4.7
SUP
SUP
SUP
18 V < V
Input Hysteresis
V
V
5.5 V < V
SUP
< 27 V
0.5
-10
—
—
1.3
10
Input Current
I
µA
IN
-0.2 V < VIN < 40 V
Notes
13. When overtemperature occurs, switch is turned off and latched off. Flag is set in SPI Register. Refer to description on page 26.
33689
Analog Integrated Circuit Device Data
Freescale Semiconductor
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ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C, GND = 0.0 V unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
RXD OUTPUT PIN (LIN PHYSICAL LAYER)
Low-Level Output Voltage
Symbol
Min
Typ
Max
Unit
V
V
V
OL
I
≤ 1.5 mA
0.0
—
—
0.9
OUT
High-Level Output Voltage
≤ 250 µA
V
OH
I
3.75
5.25
OUT
TXD INPUT PIN (LIN PHYSICAL LAYER)
Low-Level Input Voltage
High-Level Input Voltage
Input Hysteresis
V
—
3.5
50
—
—
1.5
—
V
V
IL
V
IH
V
145
300
mV
µA
INHYS
Pullup Current Source
I
PUTXD
1.0 V < V
< 3.5 V
-100
—
-20
TXD
LIN PHYSICAL LAYER, TRANSCEIVER
Transceiver Output Voltage
V
V
LINDOM
Dominant State, TXD LOW, External Bus Pullup 500 Ω
—
—
—
1.4
—
V
Recessive State, TXD HIGH, I
= 1.0 µA
V
-1.0
LINREC
OUT
SUP
Pullup Resistor to VSUP
R
kΩ
PU
In Normal Mode and in Sleep and Stop Modes When Not Disabled by
SPI
20
30
47
Pullup Current Source
I
µA
PULIN
In Sleep and Stop Modes When Pullup Disabled by SPI
Output Current Shutdown Threshold
—
1.3
75
—
I
50
150
mA
OUTSD
Leakage Output Current to GND
I
BUSLEAK
VS1 and VS2 Disconnected, V
= 18 V
—
0.0
-1.0
1.0
3.0
—
10
20
µA
µA
LIN
Recessive State, 8.0 V < V
< 18 V, 8.0 V < V
< 18 V
LIN
SUP
1.0
mA
GND Disconnected, V
= V
, V
= -18 V
LIN
GND
SUP
LIN PHYSICAL LAYER, RECEIVER
Receiver Input Threshold Voltage
V
SUP
SUP
V
Dominant State, TXD HIGH, RXD LOW
Recessive State, TXD HIGH, RXD HIGH
0.0
0.6
—
—
0.4
1.0
BUSDOM
V
V
V
BUSREC
BUSCNT
BUSHYS
Center (V
-V
)/2
0.475
—
0.5
—
0.525
0.175
BUSDOM BUSREC
Hysteresis (V
-V
)
BUSDOM BUSREC
Bus Wake-Up Threshold
V
—
0.5
—
V
BUSWU
33689
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C, GND = 0.0 V unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
SPI INTERFACE CHARACTERISTICS
Symbol
Min
Typ
Max
Unit
SPI Operation Frequency
SCLK Clock Period
0.25
250
125
125
100
—
—
—
—
—
4.0
N/A
N/A
N/A
N/A
MHz
ns
f
SPI
tPSCLK
tWSCLKH
tWSCLKL
tLEAD
SCLK Clock High Time
SCLK Clock Low Time
ns
ns
ns
Falling Edge of CS to Rising Edge of SCLK
100
—
N/A
ns
tLAG
Falling Edge of SCLK to CS Rising Edge
MOSI to Falling Edge of SCLK (Data Setup Time)
Falling Edge of SCLK to MOSI (Data Hold Time)
40
40
—
—
N/A
N/A
ns
ns
ns
tSI(SU)
tSI(HOLD)
tRSO
MISO Rise Time (14)
—
—
25
25
50
50
C = 220 pF
L
MISO Fall Time (14)
ns
ns
tFSO
C = 220 pF
L
Time from Falling or Rising Edge of CS to: (14)
MISO Low Impedance (Enable)
0.0
0.0
—
—
50
50
tSO(EN)
tSO(DIS)
tVALID
MISO High Impedance (Disable)
Time from Rising Edge of SCLK to MISO Data Valid (14)
ns
0.0
—
50
0.2 VDD ≤ MISO ≥ 0.8 VDD, CL = 100 pF
RST OUTPUT PIN IN NORMAL AND STOP MODES
Reset Duration After VDD HIGH
t
0.65
-15
1.0
—
1.35
15
ms
DURRST
WDC PIN
Watchdog Period Accuracy Using an External Resistor (Excluding Resistor
Tolerances) (15)
%
ACC
WDC
Watchdog Time Period (15)
ms
tWDC
—
—
10.558
99.748
160
—
—
10 kΩ External Resistor
100 kΩ External Resistor
107
215
No External Resistor, WDC Open, Normal Mode
Notes
14. Parameter guaranteed by design; however, it is not production tested.
15. Watchdog time period calculation formula: tWDC = 0.991 * R + 0.648 (R in kΩ and tWDC in ms).
33689
Analog Integrated Circuit Device Data
Freescale Semiconductor
12
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C, GND = 0.0 V unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
CURRENT SENSE OPERATIONAL AMPLIFIER
Supply Voltage Rejection Ratio (16)
Common Mode Rejection Ratio (16)
SVR
CMR
GBP
60
70
—
—
—
—
—
—
dB
dB
Gain Bandwidth (16)
Output Slew Rate
Phase Margin
1.0
MHz
SR
0.5
40
—
—
—
85
—
—
—
V/µs
deg.
dB
PHMO
OLG
Open Loop Gain (16)
L1 AND L2 INPUT PINS
Wake-Up Filter Time (16)
8.0
20
38
µs
µs
tWUF
STATE MACHINE TIMING
tSTOP
Delay Between CS LOW-to-HIGH Transition (at End of SPI Stop Command)
and Stop Mode Activation (16)
1.4
6.0
12
—
—
—
5.0
30
50
Minimum Watchdog Period
No Watchdog Selected
Maximum Watchdog Period
Interrupt Low-Level Duration
7.0
-35
97
10
—
13
35
µs
%
tINT
fOSC
tNRTOUT
tSHSON
Internal Oscillator Frequency Accuracy (All Modes, for Information Only)
Normal Request Mode Time-Out (Normal Request Mode)
150
205
ms
µs
,
Delay Between SPI Command and HS1 or HS2 Turn On (17)
(18)
—
—
—
—
—
—
20
20
20
Normal Mode, V
> 9.0 V, V ≥ 0.2 V
HS VS2
SUP
,
Delay Between SPI Command and HS1 or HS2 Turn Off (17)
Normal Mode, V > 9.0 V, V ≤ 0.8 V
(18)
µs
µs
µs
tSHSOFF
tSHSON
tSHSOFF
tSNR2N
SUP
HS
VS2
,
Delay Between SPI Command and HS3 Turn On (17)
(19)
Normal Mode, V
> 9.0 V, V ≥ 0.2 V
HS VS2
SUP
,
Delay Between SPI Command and HS3 Turn Off (17)
Normal Mode, V > 9.0 V, V ≤ 0.8 V
(19)
—
—
20
30
SUP
HS
VS2
Delay Between Normal Request and Normal Mode After a Watchdog Trigger
Command (Normal Request Mode) (16)
7.0
15
µs
µs
Delay Between CS Wake-Up (CS LOW to HIGH) in Stop Mode and:
Normal Request Mode, VDD ON and RST HIGH
First Accepted SPI Command
tWUCS
tWUSPI
15
90
40
—
80
N/A
30
—
N/A
µs
µs
tS1STSPI
Delay Between Interrupt Pulse in Stop Mode After Wake-Up and First
Accepted SPI Command
15
—
—
t2CS
Minimum Time Between Rising and Falling Edge on the CS
Notes
16. Parameter guaranteed by design; however, it is not production tested.
17. When IN input is set to HIGH, delay starts at falling edge of clock cycle #8 of the SPI command and start of device activation/deactivation.
30 mA load on high-side switches. Excluding rise or fall time due to external load.
18. When IN is used to control the high-side switches, delays are measured between IN and HS1 or HS2 ON/OFF. 30 mA load on high-side
switches, excluding rise or fall time due to external load.
19. Delay between turn on or turn off command and HS ON or HS OFF, excluding rise or fall time due to external load.
33689
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C, GND = 0.0 V unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
LIN PHYSICAL LAYER: BUS DRIVER TIMING CHARACTERISTICS FOR NORMAL SLEW RATE (20)
Propagation Delay TXD to LIN (21)
Dominant State Minimum Threshold (50% TXD to 58.1% V
µs
tDOMMIN
—
—
—
—
—
—
—
—
50
50
50
50
)
SUP
tDOMMAX
tRECMIN
tRECMAX
Dominant State Maximum Threshold (50% TXD to 28.4% V
Recessive State Minimum Threshold (50% TXD to 42.2% V
)
SUP
)
SUP
Recessive State Maximum Threshold (50% TXD to 74.4% V
)
SUP
Propagation Delay Symmetry
tDOMMIN - tRECMAX
µs
µs
dt1s
dt2s
-10.44
—
—
—
—
11
tDOMMAX - tRECMIN
LIN PHYSICAL LAYER: BUS DRIVER TIMING CHARACTERISTICS FOR SLOW SLEW RATE (20)
Propagation Delay TXD to LIN (22)
Dominant State Minimum Threshold (50% TXD to 61.6% V
tDOMMIN
—
—
—
—
—
—
—
—
100
100
100
100
)
SUP
tDOMMAX
tRECMIN
tRECMAX
Dominant State Maximum Threshold (50% TXD to 25.1% V
Recessive State Minimum Threshold (50% TXD to 38.9% V
)
SUP
SUP
)
Recessive State Maximum Threshold (50% TXD to 77.8% V
)
SUP
Propagation Delay Symmetry
tDOMMIN - tRECMAX
µs
dt1s
dt2s
-22
—
—
—
—
23
tDOMMAX - tRECMIN
LIN PHYSICAL LAYER: BUS DRIVER FAST SLEW RATE
LIN High Slew Rate (Programming Mode)
dv/dt Fast
tOUTDLY
—
—
13
10
—
—
V/µs
µs
LIN PHYSICAL LAYER, TRANSCEIVER
Output Current Shutdown Delay (23)
Notes
20. 7.0 V < V
< 18 V, bus load C0 and R0 1.0 nF/1.0 kΩ, 6.8 nF/660 Ω, 10 nF/500 Ω. 50% of TXD signal to LIN signal threshold. See
SUP
Figure 5, page 16.
21. See Figure 7, page 17.
22. See Figure 8, page 17.
23. Parameter guaranteed by design; however, it is not production tested.
33689
Analog Integrated Circuit Device Data
Freescale Semiconductor
14
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C, GND = 0.0 V unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
LIN PHYSICAL LAYER: RECEIVER CHARACTERISTICS AND WAKE-UP TIMINGS
Propagation Delay LIN to RXD (24)
µs
tRDOM
tRREC
tRSYM
—
—
3.0
3.0
—
6.0
6.0
2.0
Dominant State (LIN LOW to RXD LOW)
Recessive State (LIN HIGH to RXD HIGH)
Symmetry (tRDOM - tRREC
)
-2.0
Bus Wake-Up Deglitcher (Sleep and Stop Modes) (25)
Bus Wake-Up Event Reported
From Sleep Mode (26)
30
70
90
µs
µs
tPROPWL
—
—
30
20
—
—
tWU
tWU
From Stop Mode (27)
Notes
24. Measured between LIN signal threshold V
25. See Figures 9 and 10, page 18.
or V
and 50% of RXD signal.
INH
INL
26. tWU is typically 2 internal clock cycles after a LIN rising edge is detected. In Sleep Mode, the measurement is done without a capacitor
connected to the regulator. The delay is measured between the V /2 rising edge of the LIN bus and when V reaches 3.0 V. The
SUP
DD
V
rise time is strongly dependent upon the decoupling capacitor at V
pin. See Figure 9, page 18.
DD
DD
27. tWU is typically 2 internal clock cycles after a LIN rising edge is detected. In Stop Mode, the delay is measured between the V
rising edge of the LIN bus and the falling edge of the INT pin. See Figure 10, page 18.
/2
SUP
33689
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
V
PWR
33689
VS1/VS2
R0/C0 Combinations:
1.0 kΩ/1.0 nF
TXD
RXD
R0
C0
660 Ω/6.8 nF
500 Ω/10 nF
LIN
GND TGND AGND
Figure 5. Test Circuit for Timing Measurements
tPSCLK
CS
tWSCLKH
tLEAD
tLAG
SCLK
tWSCLKL
tSI(HOLD)
tSI(SU)
MOSI
MISO
Undefined
DI 7
Don’t Care
DI 0
Don’t Care
tVALID
tSO(EN)
tSO(DIS)
DO 0
DO 7
Note Incoming data at MOSI pin is sampled by the 33689 at SCLK falling edge. Outgoing data at MISO is set by the 33689
at SCLK rising edge (after tVALID delay time).
Figure 6. SPI Timing Characteristics
33689
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Freescale Semiconductor
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ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TXD
Recessive State
tRECMAX
VLINREC
74.4%
V
SUP
58.1%
V
SUP
tDOMMIN
60%
42.2%
V
V
40%
V
SUP
SUP
LIN
SUP
28.4%
V
SUP
Dominant State
tDOMMAX
tRECMIN
RXD
t
t
RREC
RDOM
Figure 7. Timing Characteristics for Normal LIN Output Slew Rate
TXD
Recessive State
tRECMAX
VLINREC
77.8%
V
SUP
61.6%
V
SUP
tDOMMIN
60%
V
SUP
40%
V
SUP
LIN
38.9%
V
SUP
25.1%
V
SUP
Dominant State
tDOMMAX
tRECMIN
RXD
t
t
RREC
RDOM
Figure 8. Timing Characteristics for Slow LIN Output Slew Rate
33689
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
Recessive State
Recessive State
V
V
LINREC
LINREC
LIN
LIN
0.4
V
0.4 V
SUP
SUP
Dominant Level
Dominant State
VDD
INT
tPROPWL
tWU
tPROPWL
tWU
Figure 9. LIN Bus Wake-Up Behavior, Sleep Mode
Figure 10. LIN Bus Wake-Up Behavior, Stop Mode
33689
Analog Integrated Circuit Device Data
Freescale Semiconductor
18
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
A System Basis Chip (SBC) is a monolithic IC combining
many functions found in standard microcontroller-based
systems; e.g., power management, communication interface,
system protection, and diagnostics.
The LIN transceiver has waveshaping that can be disabled
when high data rates are warranted. A single 50 mA and two
150 mA fully protected high-side switches with output
clamping are available for switching inductive or resistive
loads. The 150 mA switches are PWM capable.
The 33689 is a SPI-controlled SBC combining many
functions with a LIN transceiver for slave node applications.
The 33689 has a 5.0 V, 50 mA regulator with undervoltage
reset, output current limiting, overtemperature pre-warning,
and thermal shutdown. An externally selectable timing
Window Watchdog is also included.
Two high-voltage inputs can be used to monitor switches
or provide external wake-up. An internal current sense
operational amplifier is available for load current monitoring.
FUNCTIONAL PIN DESCRIPTION
battery. The 33689 can operate from 4.5 V and under the
jump start condition at 27 V DC. Device functionality is
guaranteed down to 4.5 V at VS1 and VS2 pins. These pins
sustain standard automotive voltage conditions such as load
dump at 40 V.
LEVEL 1 AND LEVEL 2 INPUT PINS
(L1 AND L2)
These pins are used to sense external switches and to
wake up the 33689 from Sleep or Stop mode. During Normal
mode, the state of these pins can be read through the SPI
Register. (Refer to the section entitled SPI Interface and
Register Description on page 24 for information on the SPI
Register.)
LIN BUS PIN (LIN)
The LIN pin represents the single-wire bus transmitter and
receiver. It is suited for automotive bus systems and is based
on the LIN bus specification.
HIGH-SIDE DRIVER OUTPUT PINS 1 AND 2 (HS1
AND HS2)
VOLTAGE SOURCE PIN (VDD)
These two high-side switches are able to drive loads such
as relays or lamps. They are protected against overcurrent
and overtemperature and include internal clamp circuitry for
inductive load protection. Switch control is done through
selecting the correct bit in the SPI Register. HS1 and HS2
can be PWM-ed if required through the IN input pin. The
internal circuitry that drives both high-side switches is an
AND function between the SPI bit HS1 (or HS2) and the IN
input pin.
The VDD pin is the 5.0 V supply pin for the MCU and the
current sense operational amplifier.
CURRENT SENSE OPERATIONAL AMPLIFIER
PINS (E+, E-, VCC, AND OUT)
These are the pins of the single-supply current sense
operational amplifier.
• The E+ and the E- input pins are the non-inverting and
inverting inputs of the current sense operational amplifier,
respectively.
If no PWM control is required, the IN pin must be
connected to the VDD pin.
• The OUT pin is the output pin of the current sense
operational amplifier.
• The VCC pin is the +5.0 V single-supply connection for the
current sense operational amplifier.
HIGH-SIDE DRIVER OUTPUT PIN 3 (HS3)
This high-side switch can be used to drive small lamps,
Hall sensors, or switch pullup resistors. Control is done
through the SPI Register only.
The current sense operational amplifier is enabled in
Normal mode only.
No direct PWM control is possible on this pin.
This high-side switch features current limit to protect it
against overcurrent and short circuit conditions. It is also
protected against overtemperature.
WATCHDOG CONFIGURATION PIN (WDC)
The WDC pin is the configuration pin for the internal
watchdog. A resistor is connected to this pin. The resistor
value defines the watchdog period. If the pin is left open, the
watchdog period is fixed to its default value (150 ms typical).
If no watchdog function is required, the WDC pin must be
connected to GND.
VOLTAGE SUPPLY PINS 1 AND 2
(VS1 AND VS2)
The 33689 is supplied from a battery line or other supply
source through the VS1 and VS2 pins. An external diode is
required to protect against negative transients and reverse
33689
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Freescale Semiconductor
19
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
• Voltage regulator temperature pre-warning
• HS1, HS2, or HS3 thermal shutdown
• VS1 or VS2 overvoltage (20 V typical)
• VS1 or VS2 undervoltage (6.0 V typical)
RESET OUTPUT PIN (RST)
The RST pin is the 5.0 V regulator and Watchdog reset
output pin.
PWM INPUT CONTROL PIN (IN)
If an interrupt is generated, then when the next SPI read
operation is performed bit D7 in the SPI Register will be set
to logic [1] and bits D6:D0 will report the interrupt source.
The IN pin is the external PWM control pin for the HS1 and
HS2 high-side switches.
In cases of wake-up from the Stop mode, INT is set LOW
in order to signal to the MCU that a wake-up event from the
L1, L2, or LIN bus pin has occurred.
SERIAL DATA CLOCK PIN (SCLK)
The SCLK pin is the SPI clock input pin. MISO data
changes on the negative transition of the SCLK. MOSI is
sampled on the positive edge of the SCLK.
RECEIVER OUTPUT PIN (RXD)
The RXD pin is the receiver output of the LIN interface and
reports the state of the bus voltage (RXD LOW when LIN bus
is dominant, RXD HIGH when LIN bus is recessive).
MASTER OUT SLAVE IN PIN (MOSI)
The MOSI pin receives SPI data from the MCU. This data
input is sampled on the positive edge of SCLK.
TRANSMITTER INPUT PIN (TXD)
The TXD pin is the transmitter input of the LIN interface
and controls the state of the bus output (dominant when TXD
is LOW, recessive when TXD is HIGH).
MASTER IN SLAVE OUT PIN (MISO)
The MISO pin sends data to an SPI-enabled MCU. Data
on this output pin changes on the negative edge of the SCLK.
When CS is HIGH, this pin enters the high-impedance state.
GROUND PINS (GND, TGND, AND AGND)
The 33689 has three different types of ground pins.
CHIP SELECT PIN (CS)
• The GND pin is the electrical ground pin for the device.
• The AGND is the analog ground pin for the voltage
regulator and current sense operational amplifier.
• The four TGND pins are the thermal ground pins for the
device.
The CS pin is the chip select input pin for SPI use. When
this signal is high, SPI signals are ignored. Asserting this pin
LOW starts an SPI transaction. The transaction is completed
when this signal returns HIGH.
INTERRUPT OUTPUT PIN (INT)
Important The GND, the AGND, and the four TGND pins
must be connected together to a ground external to the
33689.
The INT pin is used to report 33689 faults to the MCU.
Interrupt pulses are generated for:
33689
Analog Integrated Circuit Device Data
Freescale Semiconductor
20
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
the device. The output of the regulator is also connected to
the VDD pin to provide the 5.0 V to the microcontroller.
WINDOW WATCHDOG
The window watchdog can be configured using an external
resistor at WDC pin. The watchdog is cleared through
MODE1 and MODE2 bit in the SPI Register (refer to Table 2,
page 24; also refer to the section entitled Functional Pin
Description on page 19.
Current Limit (Overcurrent) Protection
The voltage regulator has current limit to protect the device
against overcurrent and short circuit conditions.
A watchdog clear is only allowed in the open window (see
Figure 1). If the watchdog is cleared in the closed window or
has not been cleared at the end of the open window, the
watchdog will generate a reset on the RST pin and reset the
whole device.
Overtemperature Protection
The voltage regulator also features overtemperature
protection that has an overtemperature warning (Interrupt -
VDDT) and an overtemperature shutdown.
Note The watchdog clear in Normal request mode
(150 ms) (first watchdog clear) has no window.
Stop Mode
During Stop mode, the Stop mode regulator supplies a
regulated output voltage. The Stop mode regulator has a
limited output current capability.
Window Closed.
No Watchdog Clear Allowed
Window Open
for Watchdog Clear
Sleep Mode
tWDC 50%
*
tWDC 50%
*
In Sleep mode, the voltage regulator external VDD is
turned off.
Watchdog Period
tWDC
VDD VOLTAGE REGULATOR TEMPERATURE
PREWARNING
Figure 1. Window Watchdog Operation
VDD voltage regulator temperature prewarning (VDDT) is
generated if the voltage regulator temperature is above the
TPRE threshold. It will set the VDDT bit in the SPI Register
and an interrupt will be initiated. The VDDT bit remains set as
long as the error condition is present.
Window Watchdog Configuration
If the WDC pin is left open, the default watchdog period is
selected (typ. 150 ms). If no watchdog function is required,
the WDC pin must be connected to GND.
During Sleep and Stop modes the VDD voltage regulator
temperature prewarning circuitry is disabled.
The watchdog timer’s period is calculated using the
following formula:
HIGH-SIDE SWITCH THERMAL SHUTDOWN
tWDC = 0.991 R +0.648 (with R in kΩ and tWDC in ms).
*
The high-side switch thermal shutdown HSST is
generated if one of the high-side switches HS1:HS3 is above
the HSST threshold. It will shutdown all high-side switches
and set the HSST flag in the SPI Register, and an interrupt
will be initiated. The HSST bit remains set as long as the error
condition is present. During Sleep and Stop modes the high-
side switch thermal shutdown circuitry is disabled.
VDD VOLTAGE REGULATOR
The 33689 chip contains a low-power, low dropout voltage
regulator to provide internal power and external power for the
MCU. The on-chip regulator consist of two elements, the
main voltage regulator and the low-voltage reset circuit.
The VDD regulator accepts an unregulated input supply
and provides a regulated VDD supply to all digital sections of
33689
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Freescale Semiconductor
21
FUNCTIONAL DESCRIPTION
FUNCTIONAL DEVICE OPERATION
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
As described below and depicted in Figure 1 below and
Table 1 on page 23, the 33689 has three operational modes:
Normal, Sleep, and Stop. Operational modes are controlled
by MODE1 and MODE2 bits in the SPI Register (refer to
Logic Commands and Registers on page 24). In additional,
there are two transitional modes: Reset and Normal Request.
RESET MODE
At power up, the 33689 switches automatically to Reset
Mode for 1 ms if VDD goes high. If VDD stays low, after
150 ms the 33689 goes in Sleep Mode.
NORMAL REQUEST MODE
Before entering in Normal Request Mode, the 33689 stays
for 1 ms in Reset Mode. In this mode, the LIN bus can
transmit and receive information.
VDD LOW (150 ms) Expired & VSUV Bit = Logic [0]
VDD HIGH & Reset Counter (1.0 ms) Expired & Watchdog Not Selected
VDD HIGH & Reset Counter (1.0 ms)
Expired & Watchdog Selected
Normal
Request
Reset
VDD LOW OR
(Normal Request
Timeout Occurs
[150 ms] & Watchdog
Selected)
Normal
VDD LOW OR (Watchdog
Fail & Watchdog Selected)
Power
Down
VDD LOW
Wake-Up
Stop
Sleep
Legend
Watchdog Selected: External resistor between WDC pin and GND or WDC pin open.
Watchdog Not Selected: WDC pin connected to GND.
Watchdog Fail: Watchdog trigger occurs in closed window or no SPI Watchdog trigger command.
Stop Command: SPI stop command.
Sleep Command: SPI sleep request followed by SPI sleep command.
Wake-Up: L1 or L2 state change or LIN bus wake-up or CS rising edge.
Figure 1. 33689 Modes State Diagram
33689
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Freescale Semiconductor
22
FUNCTIONAL DESCRIPTION
FUNCTIONAL DEVICE OPERATION
Entering Sleep Mode
NORMAL MODE
In Normal Mode, the 33689 has slew rate and timing
compatible with the LIN protocol specification. The LIN bus
can transmit and receive information. The VDD regulator is
ON and the watchdog function can be enabled.
First and second SPI commands (with bit D6=1, D7=1,
D5 =0 or 1, D1=0, and D0=0) 11x00000 must be sent.
Entering Stop Mode
First and second SPI commands (with bit D6=1, D7=1,
D5 =0 or 1, D1=0, and D0=1) 11x00001 must be sent.
SLEEP AND STOP MODE
To safely enter Sleep or Stop modes and to ensure that
these modes are not inadvertently entered due to noise
issues during SPI transmission, a dedicated sequence must
be sent twice: data with the bits controlling the LIN bus and
the device mode.
Sleep or Stop modes are entered after the second SPI
command. Register bit D5 must be set accordingly.
Table 1. Operational Modes and Associated Functions
VDD Voltage
Regulator
Wake-Up
Capabilities
Watchdog
Function
Operational
Amplifier
Device Mode
RST Output
HS1, HS2, HS3 LIN Interface
VDD: ON
VDD: ON
N/A
LOW for 1.0 ms
typical, then
HIGH (if VDD
above threshold)
Disabled
OFF
Recessive only
Not active
Reset
N/A
HIGH.
Active LOW if
VDD
150 ms timeout
if Watchdog
enabled
ON or OFF
Transmit and
receive
Not active
undervoltage
occurs and if
Normal Request
timeout (if
Normal
Request
Watchdog
enabled)
VDD: ON
N/A
HIGH.
Active LOW if
VDD
Window
Watchdog if
enabled
ON or OFF
Transmit and
receive
Active
undervoltage
occurs or if
Watchdog fail (if
Watchdog
enabled)
Normal
VDD: ON
(Limitedcurrent
capability)
LIN and state
change on
L1:L2 inputs
Normally HIGH.
Active LOW if
VDD
Disabled
Disabled
OFF
OFF
Recessivestate
with Wake
Not active
Not active
capability
Stop
undervoltage
occurs
VDD: OFF
(Set to 5.0 V
after Wake-Up
to enter Normal
Request)
LIN and state
change on
L1:L2 inputs
LOW.
Recessivestate
with Wake
Go to HIGH after
Wake-Up and
VDD within
Sleep
capability
specification
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Freescale Semiconductor
23
FUNCTIONAL DESCRIPTION
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
During an SPI data communication, the state of MISO
reports the state of the 33689 at time of a CS HIGH-to-LOW
transition. The status flags are latched at a CS HIGH-to-LOW
transition.
SPI INTERFACE AND REGISTER DESCRIPTION
As shown in Figure 2, the SPI is an 8-bit SPI. All data is
sent as bytes. The MSB, D7, is sent first. The minimum time
between two rising edges on the CS pin is 15 µs.
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1
D7 D6 D5 D4 D3 D2 D1
Bit0
D0
MISO
MOSI
Figure 2. Data Format Description
The following tables describe the SPI Register bits,
showing reset values and reset conditions.
Table 2. SPI Register Overview
MSB
Bits
LSB
D0
Read/Write
Information
D7
D6
D5
D4
HS3
D3
D2
D1
MODE2
L2
Write
Read
LINSL2
LINSL1
LIN-PU
VSOV
HS2
HS1
MODE1
L1
INTSRC (1)
LINWU or
LINFAIL
VSUV or
VDDT
HSST
BATFAIL(2)
Write Reset
Value
0
0
0
0
0
0
—
—
—
—
Write Reset
Condition
POR,
RESET
POR,
RESET
POR
POR,
RESET
POR,
RESET
POR,
RESET
Notes
1. D7 signals interrupt source. After interrupt occurs, if D7 is a logic [1] D6:D0 indicate the interrupt source. If D7 is a logic [0] no interrupt
has occurred and D6:D0 report real-time status.
2. The first SPI read after a 33689 reset returns the BATFAIL status flag bit D4.
SPI Register: Write Control Bits
LINSL2 and LINSL1—LIN Baud Rate and Low-Power
Table 3. LIN Slew Rate Control and Device Low Power
Mode Pre-Selection Bits
Mode Pre-Selection Bits (D7 and D6)
These bits select the LIN slew rate and requested low-
power mode in accordance with Table 3. Reset clears the
LINSL2:1 bits.
LINSL2
LINSL1
Description
0
0
LIN slew rate normal
(baud rate up to 20 kbps)
0
1
1
1
0
1
LIN slew rate slow
(baud rate up to 10 kbps)
LIN slew rate fast (for program download,
baud rate up to 100 kbps)
Low power mode (Sleep or Stop mode)
request, no change in LIN slew rate
33689
Analog Integrated Circuit Device Data
Freescale Semiconductor
24
FUNCTIONAL DESCRIPTION
FUNCTIONAL DEVICE OPERATION
LIN-PU—LIN Pullup Enable Bit
This bit controls the LIN pullup resistor during Sleep and
Stop modes in accordance with Table 4. Reset clears the
LIN-PU bit.
Table 4. LIN Pullup Termination Control Bit (D5)
LIN-PU
Description
0
1
30 kΩ pullup connected in Sleep and Stop mode
30 kΩ pullup disconnected in Sleep and Stop mode
HS3:HS1—High-Side H3:HS1 Enable Bits
These bits enable the HS3:HS1 bits in accordance with
Table 5. Reset clears the HSx bit.
Note If no PWM on HS1 and HS2 is required, the IN pin
must be connected to the VDD pin.
Table 5. High-Side Switches Control Bits (D4, D3, and D2)
HS3
0
Description
HS3 OFF
HS3 ON
HS2
0
Description
HS2 OFF
HS1
0
Description
HS1 OFF
1
1
HS2 ON (if IN = 1)
1
HS1 ON (if IN = 1)
MODE2 and MODE1—Mode Section Bits
To safely enter Sleep or Stop mode and to ensure that
these modes are not affected by noise issue during SPI
transmission, the Sleep/Stop commands require two SPI
transmissions.
The MODE2 and MODE1 bits control the 33689 operating
modes in accordance with Table 6.
Table 6. Mode Control Bits (D1 and D0)
Sleep Mode Sequence The Sleep command, as shown in
Table 7, must be sent twice.
MODE2
MODE1
Description
Sleep mode (3)
Table 7. Sleep Command Bits
0
0
1
0
1
LINSL2 LINSL1 LIN-PU
HS3
0
HS2
0
HS1
0
MODE2 MODE1
0
1
Stop mode
1
1
x
0
0
Normal mode + Watchdog clear (4)
Normal mode
x = Don’t care.
1
Stop Mode Sequence The Stop command, as shown in
Table 8, must be sent twice.
Notes
3. Special SPI command and sequence is implemented in
order to avoid going into Sleep or Stop mode with a single
8-bit SPI command. Refer to Tables 7 and 8.
Table 8. Stop Command Bits
4. When a logic [0] is written to MODE1 bit while MODE2 bit
is written as a logic [1]. After the SPI command is
completed, MODE1 bit is set to logic [1] and the 33689
stays in Normal mode. In order to set the 33689 in Sleep
mode, both MODE1 and MODE2 bits must be written in
the same 8-bit SPI command. The Watchdog clear on
Normal Request mode (150 ms) has no window.
LINSL2 LINSL1 LIN-PU
HS3
0
HS2
0
HS1
0
MODE2 MODE1
1
1
x
0
1
x = Don’t care.
33689
Analog Integrated Circuit Device Data
Freescale Semiconductor
25
FUNCTIONAL DESCRIPTION
FUNCTIONAL DEVICE OPERATION
SPI Register: Read Control Bits
INTSCR —Register Content Flags or Interrupt Source
LINWU/LINFAIL—LIN Bus Status Flag Bit
The INTSCR bit, as shown in Table 9, indicates if the
register contents reflect the flags or an interrupt/wake-up
source.
This bit indicates a LIN wake-up condition or a LIN
overcurrent/overtemperature in accordance with Table 10.
Table 10. LIN Bus Status (D6)
Table 9. Interrupt Status (D7)
LINWU/
Description
LINFAIL
INTSCR
Description
0
1
No LIN bus wake-up or failure
0
1
SPI word read reflects the flag state
LIN bus wake-up occurred or LIN overcurrent/
overtemperature
SPI word read reflects the interrupt or wake-up
source
VSOV—Overvoltage Flag Bit, VSUV/BATFAIL—Under-
voltage Flag Bit, VDDT—VDD Voltage Regulator Status
Flag Bit, and HSST—High-Side Status Flag Bit
Table 11 indicates the register contents of the following
flags:
• VSOV flag is set on an overvoltage condition.
• VSUV/BATFAIL flag is set on an undervoltage condition.
• VDDT flag is set as pre-warning in case of an
overtemperature condition on the voltage regulator.
• HSST flag is set on overtemperature conditions on one of
the high-side outputs.
Table 11. Over- and Undervoltage, VDD Voltage Regulator, and High-Side Status Flag Bits (D5, D4, D3, and D2)
VSUV/
VSOV
Description
Description
VDDT
Description
HSST
Description
BATFAIL
0
V
below 19 V
above 18 V
0
V
above 6.0 V
below 6.0 V
0
No overtemperature
0
HS
SUP
SUP
SUP
No overtemperature
1
V
1
V
1
VDD overtemperature
pre-warning
1
HS1, HS2, or HS3
OFF
SUP
(overtemperature)
L2 and L1— Wake-Up Inputs L2 and L1 Status Flag Bit
The L2 and L1 flags, as shown in Table 12, reflect the
status of the L2 and L1 input pins and indicate the wake-up
source.
Table 12. Switch Input Wake-Up and Real Time Status (D1 and D0)
L2
0
Description
L1
0
Description
L2 input LOW
L1 input LOW
1
L2 input HIGH or wake-up by L2
(first register read after wake-up)
1
L1 input HIGH or wake-up by L1
(first register read after wake-up)
33689
Analog Integrated Circuit Device Data
Freescale Semiconductor
26
TYPICAL APPLICATIONS
TYPICAL APPLICATIONS
The 33689 can be configured in several applications. Figure 3 shows the 33689 in the typical master node application.
33689
V
BAT
VDD1
D1
5.0 V/50 mA
VDD
RST
VS1
Voltage
Regulator
C4
C3
C2
C1
Reset
Control
WDC
Window
Watchdog
VS2
HS1
R1
IN
MOSI
MISO
SCLK
CS
SPI and
Mode
Control
HS2
HS3
Pre-Driver
INT
VDD1
R6
VCC
L2
C5
EXT INPUT
R2
MCU
E
-
R7
Current
Sense
Op Amp
E+
L1
R3
C7
R4
D2
VS1
OUT
TXD
RXD
R5
(1)
L1
LIN Bus
LIN
LIN Physical Interface
C6
R8(1)
TGND
AGND
GND
Component Values
C1=47 µF
R1=33 kΩ
C2=C4=C5=100 nF
R2 and R3 depend on the application
C3=10 µF
R4>5.0 kΩ
C6=220 pF
R5=1.0 kΩ
C7=4.7 nF
R6= 10 kΩ
R7=2.2 kΩ
R8=Varistor type TDK AVR-M1608C270MBAAB(1)
L1 = SMD Ferrite Bead-Type TDK MMZ2012Y202B(1)
Notes:
1. L1 and R8 are external components to improve EMC and ESD performances.
2. Freescale does not assume liability, endorse, or warrant components from external manufacturers that are referenced in circuit
drawings or tables. While freescale offers component recommendations in this configuration, it is the customer’s responsibility to
validate their application.
Figure 3. 33689 in Typical Master Node Application
33689
Analog Integrated Circuit Device Data
Freescale Semiconductor
27
PACKAGING
PACKAGING DIMENSIONS
PACKAGING
PACKAGING DIMENSIONS
Important For the most current revision of the package, visit www.freescale.com and do a keyword search on the 98A
drawing number below.
DWB SUFFIX
EW SUFFIX (Pb-FREE)
32-PIN SOIC WIDE BODY
PLASTIC PACKAGE
98ARH99137A
ISSUE B
33689
Analog Integrated Circuit Device Data
28
Freescale Semiconductor
PACKAGING
PACKAGING DIMENSIONS (CONTINUED)
PACKAGING DIMENSIONS (CONTINUED)
DWB SUFFIX
EW SUFFIX (Pb-FREE)
32-PIN SOIC WIDE BODY
PLASTIC PACKAGE
98ARH99137A
ISSUE B
33689
Analog Integrated Circuit Device Data
Freescale Semiconductor
29
REVISION HISTORY
REVISION HISTORY
REVISION
DATE
DESCRIPTION OF CHANGES
•
•
•
•
•
Implemented Revision History page
Updated Outline Drawing to Revision “B”
Eliminated all pages (pages 30 to 47) referring to the MC33689DWB/R2 device
Removed MC33689DWB/R2 from the orderable parts information
Updated to the prevailing form and style
6/2006
6.0
•
Removed MC33689DEW/R2 and replaced with MCZ33689DEW/R2 in the Ordering Information
block
8/2006
7.0
33689
Analog Integrated Circuit Device Data
Freescale Semiconductor
30
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MC33689
Rev. 7.0
8/2006
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