MC33910_技术文档

Document Number: MC33910

Rev. 5.0, 12/2008

Freescale Semiconductor

Advance Information

LIN System Basis Chip with High

Side Drivers

33910

The 33910 is a Serial Peripheral Interface (SPI) controlled System

Basis Chip (SBC), combining many frequently used functions in an

MCU based system, plus a Local Interconnect Network (LIN)

transceiver. The 33910 has a 5.0 V, 50 mA low dropout regulator with

full protection and reporting features. The device provides full SPI

readable diagnostics and a selectable timing watchdog for detecting

errant operation. The LIN Protocol Specification 2.0 and 2.1 compliant

LIN transceiver has waveshaping circuitry that can be disabled for

higher data rates.

SYSTEM BASIS CHIP WITH LIN

2^NDGENERATION

Two 50 mA high side switches with optional pulse-width modulated

(PWM) are implemented to drive small loads. One high voltage input is

available for use in contact monitoring, or as external wake-up input.

This input can be used as high voltage Analog Input. The voltage on

this pin is divided by a selectable ratio and available via an analog

multiplexer.

The 33910 has three main operating modes: Normal (all functions

available), Sleep (V_DDoff, wake-up via LIN, wake-up inputs (L1), cyclic

sense and forced wake-up), and Stop (V_DDon with limited current

capability, wake-up via CS, LIN bus, wake-up inputs, cyclic sense,

forced wake-up and external reset).

AC SUFFIX (Pb-FREE)

98ASH70029A

32-PIN LQFP

The 33910 is compatible with LIN Protocol Specification 2.0, 2.1, and

SAEJ2602-2.

ORDERING INFORMATION

Temperature

Features

Device

Package

• Full-duplex SPI interface at frequencies up to 4.0 MHz

• LIN transceiver capable of up to 100 kbps with wave shaping

• Two 50 mA high side switches

Range (T )

A

MC33910G5AC/R2

MC34910G5AC/R2

-40°C to 125°C

-40°C to 85°C

32-LQFP

• One high voltage analog/logic Input

• Configurable window watchdog

• 5.0 V low drop regulator with fault detection and low voltage reset (LVR) circuitry

• Switched/protected 5.0 V output (used for Hall sensors)

• Pb-free packaging designated by suffix code AC

33910

V

BAT

VSENSE

HS1

VS1

VS2

L1

VDD

PWMIN

ADOUT0

LIN INTERFACE

LIN

MCU

MOSI

MISO

SCLK

CS

RXD

TXD

IRQ

HVDD

HS2

WDCONF

RST

Figure 1. 33910 Simplified Application Diagram

* This document contains certain information on a new product.

Specifications and information herein are subject to change without notice.

DEVICE VARIATIONS

Table 1. This specification support the following products

Device

Temperature

Generation

Specification

Rev. 5.0⁽¹⁾

MC33910AC

MC34910G5AC

Notes

-40 to 125°C

2.5

Rev. 5.0⁽¹⁾

-40 to 85°C

2.5

1. Changes to Rev. 5 include:

- Increase ESD GUN IEC61000-4-2 (gun test contact with 150 pF, 330 Ω test conditions) performance to achieve +/-6 kV min on the LIN

- Immunity against ISO7637 pulse 3b

- Reduce EMC emission level on LIN

- Improve EMC immunity against RF – target new specification including 3x68 pF

- Comply with J2602 conformance test

Table 2. This specification does not support the following products

Device

MC33910BAC/R2

Temperature

Generation

Specification

Rev 1.0 to 4.0⁽²⁾

-40 to 125°C

2.0

MC34910BAC/R2

Notes

-40 to 85°C

2.0

2. For device specifications, refer to the documentation archive history. The current specification does not cover these products.

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Analog Integrated Circuit Device Data

Freescale Semiconductor

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INTERNAL BLOCK DIAGRAM

RST IRQ

VS2

VS1

VDD

INTERRUPT CONTROL

AGND

PGND

MODULE

VOLTAGE REGULATOR

LVI, HVI,

ALL OT (VDD, HS, LIN, SD)

RESET CONTROL

MODULE

LVR, WD, EXT µC

5.0 V OUTPUT

MODULE

HVDD

WINDOW

WATCHDOG

MODULE

VS2

HIGH SIDE

CONTROL

MODULE

PWMIN

HS1

HS2

VS2

MISO

MOSI

SCLK

SPI

&

CONTROL

V_BAT

SENSE MODULE

VSENSE

CS

CHIP TEMPERATURE

SENSE MODULE

ADOUT0

L1

ANALOG INPUT

MODULE

WAKE-UP MODULE

DIGITAL INPUT MODULE

RXD

TXD

LIN PHYSICAL

LAYER

LIN

LGND

WDCONF

Figure 2. 33910 Simplified Internal Block Diagram

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PIN CONNECTIONS

RXD

TXD

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

HS2

L1

MISO

NC*

PGND

NC*

MOSI

SCLK

CS

ADOUT0

PWMIN

* Special Configuration Recommended /

Mandatory for Marked NC Pins

Figure 3. 33910 Pin Connections

Table 3. 33910 Pin Definitions

A functional description of each pin can be found in the Functional Pin Description section beginning on page 23.

Pin Name

Formal Name

Definition

This pin is the receiver output of the LIN interface which reports the state of

the bus voltage to the MCU interface.

1

RXD

Receiver Output

This pin is the transmitter input of the LIN interface which controls the state of

the bus output.

2

3

TXD

Transmitter Input

SPI Output

SPI (Serial Peripheral Interface) data output. When CS is high, pin is in the

high-impedance state.

MISO

SPI (Serial Peripheral Interface) data input.

SPI (Serial Peripheral Interface) clock Input.

SPI (Serial Peripheral Interface) chip select input pin. CS is active low.

Analog Multiplexer Output.

4

5

6

7

8

MOSI

SCLK

SPI Input

SPI Clock

CS

SPI Chip Select

Analog Output Pin 0

PWM Input

ADOUT0

PWMIN

High Side Pulse Width Modulation Input.

Bidirectional Reset I/O pin - driven low when any internal reset source is

asserted. RST is active low.

9

RST

IRQ

Internal Reset I/O

Interrupt output pin, indicating wake-up events from Stop Mode or events from

Normal and Normal request modes. IRQ is active low.

Internal Interrupt

Output

10

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PIN CONNECTIONS

Table 3. 33910 Pin Definitions

A functional description of each pin can be found in the Functional Pin Description section beginning on page 23.

Pin Name

Formal Name

Definition

11, 15-17, 19-

22, 28

No connect

NC

This input pin is for configuration of the watchdog period and allows the

disabling of the watchdog.

Watchdog

Configuration Pin

12

13

14

WDCONF

LIN

This pin represents the single-wire bus transmitter and receiver.

LIN Bus

This pin is the device LIN ground connection. It is internally connected to the

PGND pin.

LGND

LIN Ground Pin

This pin is the device low side ground connection. It is internally connected to

the LGND pin.

18

23

PGND

L1

Power Ground Pin

Wake-up Input

This pin is the wake-up capable digital input⁽³⁾. In addition, L1 input can be

sensed analog via the analog multiplexer.

24

25

HS2

HS1

High side switch outputs.

High Side Outputs

26

27

VS2

VS1

These pins are device battery level power supply pins. VS2 is supplying the

HSx drivers while VS1 supplies the remaining blocks.⁽⁴⁾

Power Supply Pin

Voltage Sense Pin

Battery voltage sense input.⁽⁵⁾

29

30

VSENSE

HVDD

Hall Sensor Supply

Output

+5.0 V switchable supply output pin.⁽⁶⁾

Voltage Regulator

Output

+5.0 V main voltage regulator output pin.⁽⁷⁾

31

VDD

This pin is the device analog ground connection.

32

AGND

Analog Ground Pin

Notes

3. When used as digital input, a series 33 kΩ resistor must be used to protect against automotive transients.

4. Reverse battery protection series diodes must be used externally to protect the internal circuitry.

5. This pin can be connected directly to the battery line for voltage measurements. The pin is self protected against reverse battery

connections. It is strongly recommended to connect a 10 kΩ resistor in series with this pin for protection purposes.

6. External capacitor (1.0 µF < C < 10 µF; 0.1 Ω < ESR < 5.0 Ω) required.

7. External capacitor (2.0 µF < C < 100 µF; 0.1 Ω < ESR < 10 Ω) required.

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Analog Integrated Circuit Device Data

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ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

Table 4. Maximum Ratings

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or

permanent damage to the device.

Ratings

Symbol

Value

Unit

ELECTRICAL RATINGS

Supply Voltage at VS1 and VS2

Normal Operation (DC)

V

-0.3 to 27

-0.3 to 40

SUP(SS)

V_SUP(PK)

Transient Conditions (load dump)

Supply Voltage at VDD

V_DD

-0.3 to 5.5

V

Input / Output Pins Voltage⁽⁸⁾

V

-0.3 to V_DD+0.3

-0.3 to 11

CS, RST, SCLK, PWMIN, ADOUT0, MOSI, MISO, TXD, RXD, HVDD

IN

V

Interrupt Pin (IRQ)⁽⁹⁾

IN(IRQ)

HS1 and HS2 Pin Voltage (DC)

V

-0.3 to V_SUP+0.3

V

HS

L1 Pin Voltage

V

-18 to 40

±100

Normal Operation with a series 33k resistor (DC)

L1DC

V

Transient input voltage with external component (according to ISO7637-2)

(See Figure 5, page 19)

L1TR

VSENSE Pin Voltage (DC)

V_VSENSE

-27 to 40

V

LIN Pin Voltage

V_BUSDC

V_BUSTR

-18 to 40

Normal Operation (DC)

-150 to 100

Transient input voltage with external component (according to ISO7637-2)

(See Figure 4, page 19)

VDD Output Current

I

Internally Limited

A

VDD

Notes

8. Exceeding voltage limits on specified pins may cause a malfunction or permanent damage to the device.

9. Extended voltage range for programming purpose only.

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Analog Integrated Circuit Device Data

Freescale Semiconductor

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ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

Table 4. Maximum Ratings (continued)

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or

permanent damage to the device.

Ratings

Symbol

Value

Unit

ESD Capability

AECQ100

V

Human Body Model - JESD22/A114 (C

= 100 pF, R

= 1500 Ω)

ZAP

V

±8.0k

±6.0k

±2000

LIN Pin

L1

ESD1-1

ESD1-2

ESD1-3

all other Pins

Charge Device Model - JESD22/C101 (C

= 4.0 pF)

ZAP

V

±750

±500

Corner Pins (Pins 1, 8, 9, 16, 17, 24, 25 and 32)

All other Pins (Pins 2-7, 10-15, 18-23, 26-31)

ESD2-1

ESD2-2

According to LIN Conformance Test Specification / LIN EMC Test

Specification, August 2004 (C = 150 pF, R = 330 Ω)

ZAP

Contact Discharge, Unpowered

LIN pin with 220 pF

V

±20k

±11k

ESD3-1

ESD3-2

ESD3-3

ESD3-4

LIN pin without capacitor

VS1/VS2 (100 nF to ground)

L1 input (33 kΩ serial resistor)

>±12k

±6000

According to IEC 61000-4-2 (C

= 150 pF, R

= 330 Ω)

ZAP

Unpowered

±8000

LIN pin with 220 pF and without capacitor

VS1/VS2 (100 nF to ground)

V

ESD4-1

ESD4-2

ESD4-3

L1 input (33 kΩ serial resistor)

THERMAL RATINGS

Operating Ambient Temperature ⁽¹⁰⁾

T

°C

A

33910

34910

-40 to 125

-40 to 85

Operating Junction Temperature

Storage Temperature

T

-40 to 150

-55 to 150

°C

J

T_STG

R_θJA

Thermal Resistance, Junction to Ambient

°C/W

Natural Convection, Single Layer board (1s)^{(10), (11)}

Natural Convection, Four Layer board (2s2p)^{(10), (12)}

85

56

Thermal Resistance, Junction to Case⁽¹³⁾

R_θJC

23

°C/W

Peak Package Reflow Temperature During Reflow^{(14), (15)}

T_PPRT

Note 15

°C

Notes

10. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient

temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

11. Per JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal.

12. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.

13. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).

14. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

15. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow

Temperature and Moisture Sensitivity Levels (MSL), go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and

enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.

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Analog Integrated Circuit Device Data

Freescale Semiconductor

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ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 5. Static Electrical Characteristics

Characteristics noted under conditions 5.5 V ≤ V_SUP≤ 18 V, -40°C ≤ T_A≤ 125°C for the 33910 and -40°C ≤ T_A≤ 85°C for the

34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at T_A= 25°C under nominal

conditions, unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

SUPPLY VOLTAGE RANGE (VS1, VS2)

V_SUP

5.5

–

18

27

40

V

Nominal Operating Voltage

Functional Operating Voltage⁽¹⁶⁾

Load Dump

V_SUPOP

V_SUPLD

–

SUPPLY CURRENT RANGE (V_SUP= 13.5 V)

Normal Mode (I_OUTat V

= 10 mA), LIN Recessive State⁽¹⁷⁾

I_RUN

–

4.5

10

mA

µA

DD

Stop Mode, VDD ON with I_OUT= 100 µA, LIN Recessive State^{(17), (18),}

I_STOP

(19) (20)

,

5.5 V < V_SUP< 12 V

V_SUP= 13.5 V

–

47

62

80

90

13.5 V < V_SUP< 18 V

180

400

Sleep Mode, VDD OFF, LIN Recessive State^{(17), (19)}

5.5 V < V_SUP< 12 V

I_SLEEP

µA

–

27

33

35

48

V_SUP= 13.5 V

160

300

13.5 V ≤ V_SUP< 18 V

Cyclic Sense Supply Current Adder⁽²¹⁾

I_CYCLIC

–

10

–

µA

V

SUPPLY UNDER/OVER-VOLTAGE DETECTIONS

Power-On Reset (BATFAIL)⁽²²⁾

Threshold (measured on VS1)⁽²¹⁾

Hysteresis (measured on VS1)⁽²¹⁾

V_BATFAIL

1.5

–

3.0

0.9

3.9

–

V_{BATFAIL_HYS}

V_SUPunder-voltage detection (VSUV Flag) (Normal and Normal Request

Modes, Interrupt Generated)

V

Threshold (measured on VS1)

Hysteresis (measured on VS1)

V_SUV

V_{SUV_HYS}

5.55

–

6.0

0.2

6.6

–

V_SUPover-voltage detection (VSOV Flag) (Normal and Normal Request

Modes, Interrupt Generated)

V_SOV

V_{SOV_HYS}

Threshold (measured on VS1)

Hysteresis (measured on VS1)

18

–

19.25

1.0

20.5

–

Notes

16. Device is fully functional. All features are operating.

17. Total current (I_VS1+ I_VS2) measured at GND pins excluding all loads, cyclic sense disabled.

18. Total I_DDcurrent (including loads) below 100 µA.

19. Stop and Sleep Modes current will increase if V_SUPexceeds13.5 V.

20. This parameter is guaranteed after 90 ms.

21. This parameter is guaranteed by process monitoring but not production tested.

22. The Flag is set during power up sequence. To clear the flag, a SPI read must be performed.

33910

Analog Integrated Circuit Device Data

Freescale Semiconductor

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ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 5. Static Electrical Characteristics (continued)

Characteristics noted under conditions 5.5 V ≤ V_SUP≤ 18 V, -40°C ≤ T_A≤ 125°C for the 33910 and -40°C ≤ T_A≤ 85°C for the

34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at T_A= 25°C under nominal

conditions, unless otherwise noted.

Characteristic

VOLTAGE REGULATOR⁽²³⁾(VDD)

Normal Mode Output Voltage

1.0 mA < I < 50 mA; 5.5 V < V

Symbol

Min

Typ

Max

Unit

V_DDRUN

V

< 27 V

SUP

4.75

60

5.00

110

5.25

200

VDD

Normal Mode Output Current Limitation

Dropout Voltage⁽²⁴⁾

I_VDDRUN

mA

V

V_DDDROP

I

= 50 mA

–

0.1

0.25

VDD

Stop Mode Output Voltage

< 5.0 mA

V

DDSTOP

I

4.75

6.0

5.0

13

5.25

36

VDD

Stop Mode Output Current Limitation

Line Regulation

I

mA

mV

VDDSTOP

LR

Normal Mode, 5.5 V < V

Stop Mode, 5.5 V < V

< 18 V; I

= 10 mA

VDD

RUN

–

25

SUP

LR

STOP

< 18 V; I

= 1.0 mA

VDD

SUP

Load Regulation

mV

°C

LD

Normal Mode, 1.0 mA < I

Stop Mode, 0.1 mA < I

< 50 mA

RUN

–

80

50

VDD

LD

STOP

< 5.0 mA

VDD

Over-temperature Prewarning (Junction)⁽²⁵⁾

Interrupt generated, VDDOT Bit Set

T

PRE

90

–

115

13

140

–

Over-temperature Prewarning Hysteresis⁽²⁵⁾

Over-temperature Shutdown Temperature (Junction)⁽²⁵⁾

Over-temperature Shutdown Hysteresis⁽²⁵⁾

T

°C

PRE_HYS

T

150

–

170

13

190

–

SD

T

SD_HYS

HALL SENSOR SUPPLY OUTPUT⁽²⁶⁾(HVDD)

V

Voltage matching H_VDDACC= (HVDD-VDD) / VDD * 100%

H

%

DD

VDDACC

I_HVDD= 15 mA

-2.0

20

–

2.0

50

Current Limitation

I

35

mA

mV

HVDD

Dropout Voltage

H

VDDDROP

I_{HVDD =}15 mA; I_VDD= 5.0 mA

–

160

–

300

40

Line Regulation

LR

mV

HVDD

I_HVDD= 5.0 mA; I_VDD= 5.0 mA

Load Regulation

LD

1.0 mA > I_HVDD> 15 mA; I_VDD= 5.0 mA

–

20

Notes

23. Specification with external capacitor 2.0 µF < C < 100 µF and 100 mΩ ≤ ESR ≤ 10 Ω.

24. Measured when voltage has dropped 250 mV below its nominal Value (5.0 V).

25. This parameter is guaranteed by process monitoring but not production tested.

26. Specification with external capacitor 1.0 µF < C < 10 µF and 100 mΩ ≤ ESR ≤ 10 Ω.

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Analog Integrated Circuit Device Data

Freescale Semiconductor

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ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 5. Static Electrical Characteristics (continued)

Characteristics noted under conditions 5.5 V ≤ V_SUP≤ 18 V, -40°C ≤ T_A≤ 125°C for the 33910 and -40°C ≤ T_A≤ 85°C for the

34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at T_A= 25°C under nominal

conditions, unless otherwise noted.

Characteristic

RST INPUT/OUTPUT PIN (RST)

Symbol

Min

Typ

Max

Unit

VDD Low Voltage Reset Threshold

V_RSTTH

V_OL

4.3

4.5

4.7

V

Low-state Output Voltage

I_OUT= 1.5 mA; 3.5 V ≤ V_SUP≤ 27 V

0.0

–

0.9

High-state Output Current (0 V < V_OUT< 3.5 V)

I_OH

-150

-250

-350

µA

Pull-down Current Limitation (internally limited)

V_OUT= V_DD

I_{PD_MAX}

mA

1.5

-0.3

–

8.0

Low-state Input Voltage

High-state Input Voltage

V_IL

V_IH

0.3 x V_DD

V_DD+0.3

V

0.7 x V_DD

MISO SPI OUTPUT PIN (MISO)

Low-state Output Voltage

V_OL

V

I

= 1.5 mA

0.0

V_DD-0.9

-10

–

1.0

V_DD

10

OUT

High-state Output Voltage

I_OUT= -250 µA

V_OH

Tri-state Leakage Current

I_TRIMISO

µA

0 V ≤ V_MISO≤ V_DD

SPI INPUT PINS (MOSI, SCLK, CS)

Low-state Input Voltage

V_IL

V_IH

I_IN

-0.3

–

0.3 x V_DD

V_DD+0.3

V

High-state Input Voltage

0.7 x V_DD

MOSI, SCLK Input Current

µA

0 V ≤ V_IN≤ V_DD

-10

10

–

10

30

CS Pull-up Current

0 V < V_IN< 3.5 V

I_PUCS

µA

20

INTERRUPT OUTPUT PIN (IRQ)

Low-state Output Voltage

I_OUT= 1.5 mA

V_OL

V_OH

I_OUT

V

0.0

V_DD-0.8

–

0.8

V_DD

2.0

High-state Output Voltage

I_OUT= -250 µA

Leakage Current

mA

V_DD≤ V_OUT≤ 10 V

PULSE WIDTH MODULATION INPUT PIN (PWMIN)

Low-state Input Voltage

V_IL

V_IH

-0.3

–

0.3 x V_DD

V_DD+0.3

V

High-state Input Voltage

0.7 x V_DD

Pull-up current

I_PUPWMIN

µA

0 V < V_IN< 3.5 V

10

20

30

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Analog Integrated Circuit Device Data

Freescale Semiconductor

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ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 5. Static Electrical Characteristics (continued)

Characteristics noted under conditions 5.5 V ≤ V_SUP≤ 18 V, -40°C ≤ T_A≤ 125°C for the 33910 and -40°C ≤ T_A≤ 85°C for the

34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at T_A= 25°C under nominal

conditions, unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

HIGH SIDE OUTPUTS HS1 AND HS2 PINS (HS1, HS2)

Output Drain-to-Source On Resistance

T_J= 25°C, I_LOAD= 50 mA; V_SUP> 9.0 V

R_DS(ON)

Ω

–

7.0

10

14

T_J= 150°C, I_LOAD= 50 mA; V_SUP> 9.0 V⁽²⁷⁾

T_J= 150°C, I_LOAD= 30 mA; 5.5 V < V_SUP< 9.0 V⁽²⁷⁾

Output Current Limitation⁽²⁸⁾

0 V < V_OUT< V_SUP- 2.0 V

I_LIMHSX

mA

60

–

90

250

7.5

Open Load Current Detection⁽²⁹⁾

I_OLHSX

I_LEAK

5.0

mA

µA

Leakage Current

-0.2 V < V_HSX< V_S2+ 0.2 V

–

10

Short-circuit Detection Threshold⁽³⁰⁾

5.5 V < V_SUP< 27 V

V_THSC

V

V_SUP-2.0

–

Over-temperature Shutdown^{(31), (32)}

Over-temperature Shutdown Hysteresis⁽³²⁾

L1 INPUT PIN (L1)

T_HSSD

140

–

160

10

180

–

°C

T_{HSSD_HYS}

Low Detection Threshold⁽³³⁾

5.5 V < V_SUP< 27 V

V_THL

V_THH

V_HYS

I_IN

V

2.0

3.0

0.4

2.5

3.5

0.8

3.0

4.0

1.4

High Detection Threshold⁽³³⁾

5.5 V < V_SUP< 27 V

Hysteresis⁽³³⁾

V

5.5 V < V_SUP< 27 V

Input Current⁽³⁴⁾

µA

kΩ

-0.2 V < V_IN< VS1

-10

–

10

Analog Input Impedance⁽³⁵⁾

R_L1IN

800

1300

2000

Analog Input Divider Ratio (RATIO_L1= V_L1/ V_ADOUT0

L1DS (L1 Divider Select) = 0

)

RATIO_L1

0.95

3.42

1.0

3.6

1.05

3.78

L1DS (L1 Divider Select) = 1

Analog Output offset Ratio

L1DS (L1 Divider Select) = 0

L1DS (L1 Divider Select) = 1

V_RATIOL1-

mV

%

OFFSET

-80

-22

6.0

2.0

80

22

Analog Inputs Matching

L1_MATCHING

L1DS (L1 Divider Select) = 0

L1DS (L1 Divider Select) = 1

96

100

104

Notes

27. This parameter is production tested up to T_A= 125°C, and guaranteed by process monitoring up to T_J= 150°C.

28. When over-current occurs, the corresponding high side stays ON with limited current capability and the HSxCL flag is set in the HSSR.

29. When open load occurs, the flag (HSxOP) is set in the HSSR.

30. HS automatically shutdown if HSOT occurs or if the HVSE flag is enabled and an over-voltage occurs.

31. When over-temperature shutdown occurs, both high sides are turned off. All flags in HSSR are set.

32. Guaranteed by characterization but not production tested

33. If L1 pin is unused it must be connected to ground.

34. Analog multiplexer input disconnected from L1 input pin.

35. Analog multiplexer input connected to L1 input pin.

33910

Analog Integrated Circuit Device Data

Freescale Semiconductor

11

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 5. Static Electrical Characteristics (continued)

Characteristics noted under conditions 5.5 V ≤ V_SUP≤ 18 V, -40°C ≤ T_A≤ 125°C for the 33910 and -40°C ≤ T_A≤ 85°C for the

34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at T_A= 25°C under nominal

conditions, unless otherwise noted.

Characteristic

WINDOW WATCHDOG CONFIGURATION PIN (WDCONF)⁽³⁶⁾

External Resistor Range

Symbol

Min

Typ

Max

Unit

R

20

–

200

15

kΩ

EXT

Watchdog Period Accuracy with External Resistor (Excluding Resistor

Accuracy)⁽³⁷⁾

WD

-15

%

ACC

ANALOG MULTIPLEXER

Temperature Sense Analog Output Voltage

T_A= -40°C

V_{ADOUT0_TEMP}

V

2.0

2.8

3.6

-

2.8

3.6

4.6

T

_A= 25°C

3.0

T_A= 125°C

Temperature Sense Analog Output Voltage per characterization⁽³⁸⁾

T_A= 25°C

V_{ADOUT0_25}

3.1

3.15

3.2

V

Internal Chip Temperature Sense Gain

S_TTOV

9.0

9.9

10.5

10.2

12

mV/K

Internal Chip Temperature Sense Gain per characterization at 3

temperatures⁽³⁸⁾See Figure 16, Temperature Sense Gain

S_{TTOV_3T}

10.5

VSENSE Input Divider Ratio (RATIO_VSENSE= V_VSENSE/ V_ADOUT0

5.5 V < V_SUP< 27 V

)

RATIO_VSENSE

RATIO_VSENSECZ

5.0

5.25

5.5

VSENSE Input Divider Ratio (RATIOVSENSE=Vsense/Vadout0) per

characterization⁽³⁸⁾

5.5 <Vsup< 27 V

5.15

-30

5.25

-10

5.35

30

0

VSENSE Output Related Offset

OFFSET_VSENSE

mV

VSENSE Output Related Offset per characterization⁽³⁸⁾

OFFSET_VSENSE

_CZ

-30

-12.6

ANALOG OUTPUT (ADOUT0)

Maximum Output Voltage

-5.0 mA < I_O< 5.0 mA

V_{OUT_MAX}

V

V_DD-0.35

0.0

–

V_DD

0.35

Minimum Output Voltage

-5.0 mA < I_O< 5.0 mA

V_{OUT_MIN}

RXD OUTPUT PIN (LIN PHYSICAL LAYER) (RXD)

Low-state Output Voltage

I_OUT= 1.5 mA

V_OL

V

0.0

–

0.8

High-state Output Voltage

I_OUT= -250 µA

V_OH

V_DD-0.8

V_DD

Notes

36. For V_SUP4.7 to 18 V

37. Watchdog timing period calculation formula: t_PWD[ms] = [0.466 * (R_EXT- 20)] + 10 with (R_EXTin kΩ)

38. These limits have been defined after laboratory characterization on 3 lots and 30 samples. These tighten limits could not be guaranteed

by production test.

33910

Analog Integrated Circuit Device Data

Freescale Semiconductor

12

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 5. Static Electrical Characteristics (continued)

Characteristics noted under conditions 5.5 V ≤ V_SUP≤ 18 V, -40°C ≤ T_A≤ 125°C for the 33910 and -40°C ≤ T_A≤ 85°C for the

34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at T_A= 25°C under nominal

conditions, unless otherwise noted.

Characteristic

TXD INPUT PIN (LIN PHYSICAL LAYER) (TXD)

Low-state Input Voltage

Symbol

Min

Typ

Max

Unit

V_IL

V_IH

-0.3

0.7 x V_DD

10

–

0.3 x V_DD

V_DD+0.3

30

V

High-state Input Voltage

Pin Pull-up Current, 0 V < V_IN< 3.5 V

I_PUIN

20

µA

LIN PHYSICAL LAYER WITH J2602 FEATURE ENABLED (BIT DIS_J2602 = 0)

LIN Under Voltage threshold

V_{TH_UNDER_}

VOLTAGE

V

Positive and Negative threshold (V_THP, V_THN

)

5.0

6.0

Hysteresis (V_THP- V_THN

)

V_{J2602_DEG}

400

mV

LIN PHYSICAL LAYER, TRANSCEIVER (LIN)⁽³⁹⁾

Operating Voltage Range

V_BAT

V_SUP

8.0

7.0

18

40

V

Supply Voltage Range

Voltage Range within which the device is not destroyed

V_{SUP_NON_OP}

I_{BUS_LIM}

-0.3

V

Current Limitation for Driver Dominant State

Driver ON, V_BUS= 18 V

mA

40

-1.0

–

90

–

200

–

Input Leakage Current at the receiver

Driver off; V_BUS= 0 V; V_BAT= 12 V

I_{BUS_PAS_DOM}

I_{BUS_PAS_REC}

I_{BUS_NO_GND}

mA

µA

Leakage Output Current to GND

Driver Off; 8.0 V < V_BAT< 18 V; 8.0 V < V_BUS< 18 V; V_BUS≥ V_BAT

–

20

1.0

Control unit disconnected from ground⁽⁴⁰⁾

mA

GND_DEVICE= V_SUP; V_BAT= 12 V; 0 < V

< 18 V

-1.0

–

BUS

V

Disconnected; V_{SUP_DEVICE}= GND; 0 V < V

< 18 V⁽⁴¹⁾

BUS

I_{BUSNO_BAT}

V_BUSDOM

V_BUSREC

µA

BAT

–

100

0.4

Receiver Dominant State

Receiver Recessive State

V_SUP

0.6

0.475

–

Receiver Threshold Center

(V_{TH_DOM}+ V_{TH_REC})/2

V_{BUS_CNT}

0.5

0.525

Receiver Threshold Hysteresis

V_HYS

V_SUP

(V_{TH_REC}- V_{TH_DOM}

)

–

0.175

Voltage Drop at the serial Diode in pull-up path

V_SERDIODE

V_{SHIFT_BAT}

V_{SHIFT_GND}

0.4

0

1.0

V

VBAT_SHIFT

GND_SHIFT

Notes

10%

V_BAT

0

39. Parameters guaranteed for 7.0 V ≤ V_SUP≤ 18 V.

40. Loss of local ground must not affect communication in the residual network.

41. Node has to sustain the current that can flow under this condition. Bus must remain operational under this condition.

33910

Analog Integrated Circuit Device Data

Freescale Semiconductor

13

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 5. Static Electrical Characteristics (continued)

Characteristics noted under conditions 5.5 V ≤ V_SUP≤ 18 V, -40°C ≤ T_A≤ 125°C for the 33910 and -40°C ≤ T_A≤ 85°C for the

34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at T_A= 25°C under nominal

conditions, unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

LIN PHYSICAL LAYER, TRANSCEIVER (LIN) (CONTINUED)⁽³⁹⁾

LIN Wake-up threshold from Stop or Sleep Mode⁽⁴²⁾

V_BUSWU

R_SLAVE

5.3

30

5.8

60

180

–

V

LIN Pull-up Resistor to V

SUP

20

140

–

kΩ

°C

Over-temperature Shutdown⁽⁴³⁾

Over-temperature Shutdown Hysteresis

Notes

T_LINSD

160

10

T_{LINSD_HYS}

42. This parameter is 100% tested on an Automatic Tester. However, since it has not been monitored during reliability stresses, Freescale

does not guarantee this parameter during the product's life time.

43. When over-temperature shutdown occurs, the LIN bus goes in recessive state and the flag LINOT in LINSR is set.

33910

Analog Integrated Circuit Device Data

Freescale Semiconductor

14

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 6. Dynamic Electrical Characteristics

Characteristics noted under conditions 5.5 V ≤ V_SUP≤ 18 V, -40°C ≤ T_A≤ 125°C for the 33910 and -40°C ≤ T_A≤ 85°C for the

34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at T_A= 25°C under nominal

conditions, unless otherwise noted.

Characteristic

SPI INTERFACE TIMING (SEE Figure 13, PAGE 22)

SPI Operating Frequency

Symbol

Min

Typ

Max

Unit

f

t

–

4.0

N/A

MHz

ns

SPIOP

SCLK Clock Period

250

110

100

40

CLK

PS

SCLK Clock High Time⁽⁴⁴⁾

t

ns

SCLKH

W

SCLK Clock Low Time⁽⁴⁴⁾

t

ns

SCLKL

W

Falling Edge of CS to Rising Edge of SCLK⁽⁴⁴⁾

Falling Edge of SCLK to CS Rising Edge⁽⁴⁴⁾

MOSI to Falling Edge of SCLK⁽⁴⁴⁾

Falling Edge of SCLK to MOSI⁽⁴⁴⁾

MISO Rise Time⁽⁴⁴⁾

t

ns

LEAD

t_LAG

ns

t

ns

SISU

t

40

ns

SIH

t_RSO

ns

C = 220 pF

L

–

40

–

MISO Fall Time⁽⁴⁴⁾

t

ns

FSO

C = 220 pF

L

Time from Falling or Rising Edges of CS to:⁽⁴⁴⁾

- MISO Low-impedance

t

0.0

–

50

SOEN

- MISO High-impedance

t

SODIS

Time from Rising Edge of SCLK to MISO Data Valid⁽⁴⁴⁾

t

ns

VALID

0.2 x V_DD≤ MISO ≥ 0.8 x V_DD, C_L= 100 pF

0.0

–

75

RST OUTPUT PIN

Reset Low-level Duration After V_DDHigh (see Figure 12, page 22)

Reset Deglitch Filter Time

t

0.65

350

1.0

1.35

900

ms

ns

RST

t

480

RSTDF

WINDOW WATCHDOG CONFIGURATION PIN (WDCONF)

Watchdog Time Period⁽⁴⁵⁾

t

ms

PWD

External Resistor R_EXT= 20 kΩ (1%)

External Resistor R_EXT= 200 kΩ (1%)

Without External Resistor R_EXT(WDCONF Pin Open)

8.5

79

10

94

11.5

108

205

110

150

Notes

44. This parameter is guaranteed by process monitoring but not production tested.

45. Watchdog timing period calculation formula: t_PWD[ms] = [0.466 * (R_EXT- 20)] + 10 with (R_EXTin kΩ)

33910

Analog Integrated Circuit Device Data

Freescale Semiconductor

15

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 6. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions 5.5 V ≤ V_SUP≤ 18 V, -40°C ≤ T_A≤ 125°C for the 33910 and -40°C ≤ T_A≤ 85°C for the

34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at T_A= 25°C under nominal

conditions, unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

L1 INPUT

L1 Filter Time Deglitcher⁽⁴⁶⁾

t

8.0

20

38

μs

WUF

STATE MACHINE TIMING

Delay Between CS LOW-to-HIGH Transition (at End of SPI Stop Command)

and Stop Mode Activation⁽⁴⁶⁾

t_STOP

μs

–

5.0

205

270

+35

Normal Request Mode Timeout (see Figure 12, page 22)

Cyclic Sense ON Time from Stop and Sleep Mode⁽⁴⁷⁾

Cyclic Sense Accuracy⁽⁴⁶⁾

t

110

130

-35

150

200

ms

µs

%

NRTOUT

T_ON

Delay Between SPI Command and HS Turn On⁽⁴⁸⁾

9.0 V < V_SUP< 27 V

t_S-ON

t_S-OFF

t_SNR2N

μs

–

10

Delay Between SPI Command and HS Turn Off⁽⁴⁸⁾

9.0 V < V_SUP< 27 V

μs

Delay Between Normal Request and Normal Mode After a Watchdog Trigger

Command (Normal Request Mode)⁽⁴⁶⁾

μs

Delay Between CS Wake-up (CS LOW to HIGH) in Stop Mode and:

Normal Request Mode, VDD ON and RST HIGH

First Accepted SPI Command

t_WUCS

t_WUSPI

9.0

90

15

—

80

N/A

Minimum Time Between Rising and Falling Edge on the CS

t₂

4.0

—

μs

CS

J2602 DEGLITCHER

V_SUPDeglitcher⁽⁴⁹⁾

(DIS_J2602 = 0)

t_{J2602_DEG}

35

50

70

Notes

46. This parameter is guaranteed by process monitoring but not production tested.

47. This parameter is 100% tested on an Automatic Tester. However, since it has not been monitored during reliability stresses, Freescale

does not guarantee this parameter during the product's life time.

48. Delay between turn on or off command (rising edge on CS) and HS ON or OFF, excluding rise or fall time due to external load.

49. This parameter has not been monitoring during operating life test.

33910

Analog Integrated Circuit Device Data

Freescale Semiconductor

16

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 6. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions 5.5 V ≤ V_SUP≤ 18 V, -40°C ≤ T_A≤ 125°C for the 33910 and -40°C ≤ T_A≤ 85°C for the

34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at T_A= 25°C under nominal

conditions, unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR NORMAL SLEW RATE - 20.0KBIT/SEC ACCORDING TO LIN PHYSICAL

LAYER SPECIFICATION^{(50), (51)}

Duty Cycle 1:

D1

D2

TH_REC(MAX)= 0.744 * V_SUP

TH_DOM(MAX)= 0.581 * V_SUP

0.396

—

D1 = t_{BUS_REC(MIN)}/(2 x t_BIT), t_BIT= 50 µs, 7.0 V ≤ V_SUP≤ 18 V

Duty Cycle 2:

TH_REC(MIN)= 0.422 * V_SUP

TH_DOM(MIN)= 0.284 * V_SUP

—

0.581

D2 = t_{BUS_REC(MAX)}/(2 x t_BIT), t_BIT= 50 µs, 7.6 V ≤ V_SUP≤ 18 V

LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR SLOW SLEW RATE - 10.4KBIT/SEC ACCORDING TO LIN PHYSICAL LAYER

SPECIFICATION^{(50), (52)}

Duty Cycle 3:

D3

TH_REC(MAX)= 0.778 * V_SUP

TH_DOM(MAX)= 0.616 * V_SUP

0.417

—

D3 = t_{BUS_REC(MIN)}/(2 x t_BIT), t_BIT= 96 µs, 7.0 V ≤ V_SUP≤ 18 V

Duty Cycle 4:

D4

TH_REC(MIN)= 0.389 * V_SUP

TH_DOM(MIN)= 0.251 * V_SUP

—

0.590

D4 = t_{BUS_REC(MAX)}/(2 x t_BIT), t_BIT= 96 µs, 7.6 V ≤ V_SUP≤ 18 V

Notes

50. Bus load R_BUSand C_BUS1.0 nF / 1.0 kΩ, 6.8 nF / 660 Ω, 10 nF / 500 Ω. Measurement thresholds: 50% of TXD signal to LIN signal

threshold defined at each parameter. See Figure 6, page 20.

51. See Figure 7, page 20.

52. See Figure 8, page 20.

33910

Analog Integrated Circuit Device Data

Freescale Semiconductor

17

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 6. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions 5.5 V ≤ V_SUP≤ 18 V, -40°C ≤ T_A≤ 125°C for the 33910 and -40°C ≤ T_A≤ 85°C for the

34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at T_A= 25°C under nominal

conditions, unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

V/μs

μs

LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR FAST SLEW RATE

LIN Fast Slew Rate (Programming Mode)

SR

—

20

—

FAST

LIN PHYSICAL LAYER: CHARACTERISTICS AND WAKE-UP TIMINGS⁽⁵³⁾

Propagation Delay and Symmetry⁽⁵⁴⁾

t_{REC_PD}

Propagation Delay of Receiver, t_{REC_PD}=MAX (t_{REC_PDR}, t_{REC_PDF}

Symmetry of Receiver Propagation Delay, t_{REC_PDF}- t_{REC_PDR}

)

—

4.2

—

6.0

2.0

t_{REC_SYM}

-2.0

Bus Wake-Up Deglitcher (Sleep and Stop Modes)^{(55)(59) (56)}

t_PROPWL

42

70

95

μs

Bus Wake-Up Event Reported

From Sleep Mode⁽⁵⁷⁾

t_{WAKE_SLEEP}

t_{WAKE_STOP}

—

1500

35

From Stop Mode⁽⁵⁸⁾

9.0

27

TXD Permanent Dominant State Delay

t_TXDDOM

0.65

1.0

1.35

s

PULSE WIDTH MODULATION INPUT PIN (PWMIN)

PWMIN pin⁽⁵⁹⁾

f_PWMIN

kHz

Max. frequency to drive HS output pins

10

Notes

53. V_SUPfrom 7.0 to 18 V, bus load R_BUSand C_BUS1.0 nF / 1.0 kΩ, 6.8 nF / 660 Ω, 10 nF / 500 Ω. Measurement thresholds: 50% of TXD

signal to LIN signal threshold defined at each parameter. See Figure 6, page 20.

54. See Figure 9, page 21

55. See Figure 10, page 21 for Sleep and Figure 11, page 21 for Stop Mode.

56. This parameter is tested on automatic tester but has not been monitoring during operating life test.

57. The measurement is done with 1.0 µF capacitor and 0 mA current load on V_DD. The value takes into account the delay to charge the

capacitor. The delay is measured between the bus wake-up threshold (V_BUSWU) rising edge of the LIN bus and when V reaches 3.0 V.

DD

See Figure 10, page 21. The delay depends of the load and capacitor on V_DD

.

58. In Stop Mode, the delay is measured between the bus wake-up threshold (V_BUSWU) and the falling edge of the IRQ pin. See Figure 11,

page 21.

59. This parameter is guaranteed by process monitoring but not production tested.

33910

Analog Integrated Circuit Device Data

Freescale Semiconductor

18

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

33910

TRANSIENT PULSE

GENERATOR

1.0 nF

LIN

(

NOTE

)

GND

PGND LGND AGND

Note Waveform per ISO 7637-2. Test Pulses 1, 2, 3a, 3b.

Figure 4. Test Circuit for Transient Test Pulses (LIN)

33910

Transient Pulse

Generator

(Note)

1.0 nF

L1

10 kΩ

GND

PGND LGND AGND

Note Waveform per ISO 7637-2. Test Pulses 1, 2, 3a, 3b,.

Figure 5. Test Circuit for Transient Test Pulses (L1)

V_SUP

R0

LIN

TXD

RXD

R0 AND C0 COMBINATIONS:

• 1.0 KΩ and 1.0 nF

• 660 Ω and 6.8 nF

• 500 Ω and 10 nF

C0

Figure 6. Test Circuit for LIN Timing Measurements

33910

Analog Integrated Circuit Device Data

Freescale Semiconductor

19

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

TXD

t_BIT

t

BUS_REC(MIN)

BUS_DOM(MAX)

V_{LIN_REC}

74.4% V_SUP

Thresholds of

receiving node 1

TH

REC(MAX)

DOM(MAX)

58.1% V

SUP

TH

LIN

Thresholds of

receiving node 2

42.2% V

28.4% V

SUP

TH

REC(MIN)

SUP

TH

DOM(MIN)

t

BUS_DOM(MIN)

t

BUS_REC(MAX)

RXD

Output of receiving Node 1

t

REC_PDF(1)

t

REC_PDR(1)

RXD

Output of receiving Node 2

t

REC_PDF(2)

t

REC_PDR(2)

Figure 7. LIN Timing Measurements for Normal Slew Rate

TXD

t_BIT

t

BUS_REC(MIN)

BUS_DOM(MAX)

V_{LIN_REC}

77.8% V_SUP

Thresholds of

receiving node 1

TH

REC(MAX)

DOM(MAX)

61.6% V

SUP

TH

LIN

Thresholds of

receiving node 2

38.9% V

25.1% V

SUP

TH

REC(MIN)

SUP

TH

DOM(MIN)

t

BUS_DOM(MIN)

t

BUS_REC(MAX)

RXD

Output of receiving Node 1

t

REC_PDF(1)

t

REC_PDR(1)

RXD

Output of receiving Node 2

t

REC_PDF(2)

t

REC_PDR(2)

Figure 8. LIN Timing Measurements for Slow Slew Rate

33910

Analog Integrated Circuit Device Data

Freescale Semiconductor

20

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

V_{LIN_REC}

0.6% V

0.4% V

SUP

V

BUSREC

V

SUP

LIN BUS SIGNAL

SUP

V

BUSDOM

RXD

t

REC_PDF

REC_PDR

Figure 9. LIN Receiver Timing

V

LIN_REC

LIN

5.0 V

DOMINANT LEVEL

V_BUSWU

3.0 V

VDD

t

WAKE_SLEEP

t

WL

PROP

Figure 10. LIN Wake-Up Sleep Mode Timing

V

LIN_REC

LIN

5.0 V

V_BUSWU

DOMINANT LEVEL

t

IRQ

WAKE_STOP

t

WL

PROP

Figure 11. LIN Wake-up Stop Mode Timing

33910

Analog Integrated Circuit Device Data

Freescale Semiconductor

21

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

V

SUP

V

DD

RST

t

NRTOUT

t

RST

Figure 12. Power On Reset and Normal Request Timeout Timing

t

PSCLK

CS

t

WSCLKH

LEAD

t

LAG

SCLK

t

WSCLKL

t

SIH

SISU

MOSI

MISO

UNDEFINED

D0

DON’T CARE

D7

DON’T CARE

t

VALID

t

SODIS

t

SOEN

D0

D7

DON’T CARE

Figure 13. SPI Timing Characteristics

33910

Analog Integrated Circuit Device Data

Freescale Semiconductor

22

FUNCTIONAL DESCRIPTION

INTRODUCTION

FUNCTIONAL DESCRIPTION

INTRODUCTION

The 33910 was designed and developed as a highly

integrated and cost-effective solution for automotive and

industrial applications. For automotive body electronics, the

33910 is well suited to perform keypad applications via the

LIN bus.

include a Hall Sensor port supply, and one wake-up capable

pin. An internal voltage regulator provides power to a MCU

device.

Also included in this device is a LIN physical layer, which

communicates using a single wire. This enables this device

to be compatible with 3-wire bus systems, where one wire is

used for communication, one for battery, and one for ground.

Power switches are provided on the device configured as

high side outputs. Other ports are also provided, which

FUNCTIONAL PIN DESCRIPTION

See Figure 1, 33910 Simplified Application Diagram,

page 1, for a graphic representation of the various pins

referred to in the following paragraphs. Also, see the pin

diagram on page 4 for a description of the pin locations in the

package.

MASTER OUT SLAVE IN PIN (MOSI)

The MOSI digital pin receives SPI data from the MCU. This

data input is sampled on the negative edge of SCLK.

MASTER IN SLAVE OUT PIN (MISO)

The MISO pin sends data to an SPI-enabled MCU. It is a

digital tri-state output used to shift serial data to the

microcontroller. Data on this output pin changes on the

positive edge of the SCLK. When CS is High, this pin will

remain in the high-impedance state.

RECEIVER OUTPUT PIN (RXD)

The RXD pin is a digital output. It is the receiver output of

the LIN interface and reports the state of the bus voltage:

RXD Low when LIN bus is dominant, RXD High when LIN bus

is recessive.

CHIP SELECT PIN (CS)

TRANSMITTER INPUT PIN (TXD)

CS is an active low digital input. It must remain low during

a valid SPI communication and allow for several devices to

be connected in the same SPI bus without contention. A

rising edge on CS signals the end of the transmission and the

moment the data shifted in is latched. A valid transmission

must consist of 8 bits only.

The TXD pin is a digital input. It is the transmitter input of

the LIN interface and controls the state of the bus output

(dominant when TXD is Low, recessive when TXD is High).

This pin has an internal pull-up to force recessive state in

case the input is left floating.

While in STOP Mode, a low-to-high level transition on this

pin will generate a wake-up condition for the 33910.

LIN BUS PIN (LIN)

The LIN pin represents the single-wire bus transmitter and

receiver. It is suited for automotive bus systems and is

compliant to the LIN bus specification 2.0, 2.1, and SAE

J2602-2.

ANALOG MULTIPLEXER PIN (ADOUT0)

The ADOUT0 pin can be configured via the SPI to allow

the MCU A/D converter to read the several inputs of the

Analog Multiplexer, including the VSENSE and L1 input

voltages, and the internal junction temperature.

The LIN interface is only active during Normal Mode. See

Table 7, Operating Modes Overview.

SERIAL DATA CLOCK PIN (SCLK)

PWM INPUT CONTROL PIN (PWMIN)

The SCLK pin is the SPI clock input. MISO data changes

on the positive transition of the SCLK. MOSI is sampled on

the negative edge of the SCLK.

This digital input can control the high sides drivers in

Normal Request and Normal Mode.

To enable PWM control, the MCU must perform a write

operation to the High Side Control Register (HSCR).

This pin has an internal 20 μA current pull-up.

33910

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23

FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

input for the analog multiplexer. When used to sense voltage

outside the module, a 33 kohm series resistor must be used

on the input.

RESET PIN (RST)

This bidirectional pin is used to reset the MCU in case the

33910 detects a reset condition, or to inform the 33910 that

the MCU has just been reset. After release of the RST pin,

Normal Request Mode is entered.

When used as wake-up input L1 can be configured to

operate in cyclic-sense mode. In this mode one or both of the

high side switches are configured to be periodically turned on

and sample the wake-up input. If a state change is detected

between two cycles a wake-up is initiated. The 33910 can

also wake-up from Stop or Sleep by a simple state change on

L1.

The RST pin is an active low filtered input and output

formed by a weak pull-up and a switchable pull-down

structure which allows this pin to be shorted either to V_DDor

to GND during software development, without the risk of

destroying the driver.

When used as analog input, the voltage present on the L1

pin is scaled down by an selectable internal voltage divider

and can be routed to the ADOUT0 output through the analog

multiplexer.

INTERRUPT PIN (IRQ)

The IRQ pin is a digital output used to signal events or

faults to the MCU while in Normal and Normal Request Mode

or to signal a wake-up from Stop Mode. This active low output

will transition to high only after the interrupt is acknowledged

by a SPI read of the respective status bits.

Note: If L1 input is selected in the analog multiplexer, it will

be disabled as digital input and remains disabled in low

power mode. No wake-up feature is available in that

condition.

When the L1 input is not selected in the analog

multiplexer, the voltage divider is disconnected from that

input.

WATCHDOG CONFIGURATION PIN (WDCONF)

The WDCONF pin is the configuration pin for the internal

watchdog. A resistor can be connected to this pin to configure

the window watchdog period. When connected directly to

ground, the watchdog will be disabled. When this pin is left

open, the watchdog period is fixed to its lower precision

internal default value (150 ms typical).

HIGH SIDE OUTPUT PINS (HS1 AND HS2)

These two high side switches are able to drive loads such

as relays or lamps. Their structures are connected to the VS2

supply pin. The pins are short-circuit protected and both

outputs are also protected against overheating.

GROUND CONNECTION PINS (AGND, PGND,

LGND)

HS1 and HS2 are controlled by SPI and can respond to a

signal applied to the PWMIN input pin.

The AGND, PGND and LGND pins are the Analog and

Power ground pins.

HS1 and HS2 outputs can also be used during low-power

mode for the cyclic-sense of the wake inputs.

The AGND pin is the ground reference of the voltage

regulator module.

POWER SUPPLY PINS (VS1 AND VS2)

The PGND and LGND pins are used for high current load

return as in the LIN interface pin.

Those are the battery level voltage supply pins. In an

application, VS1 and VS2 pins must be protected against

reverse battery connection and negative transient voltages

with external components. These pins sustain standard

automotive voltage conditions such as a load dump at 40 V.

Note: PGND, AGND and LGND pins must be connected

together.

DIGITAL/ANALOG PIN (L1)

The high side switches (HS1 and HS2) are supplied by the

VS2 pin. All other internal blocks are supplied by the VS1 pin.

The L1 pin is multi purpose input. It can be used as a digital

input, which can be sampled by reading the SPI and used for

wake-up when 33910 is in low power mode or used as analog

33910

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FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

The HVDD pin needs to be connected to an external

capacitor to stabilize the regulated output voltage.

VOLTAGE SENSE PIN (VSENSE)

This input can be connected directly to the battery line. It

is protected against battery reverse connection. The voltage

present in this input is scaled down by an internal voltage

divider, and can be routed to the ADOUT0 output pin and

used by the MCU to read the battery voltage.

+5V MAIN REGULATOR OUTPUT PIN (VDD)

An external capacitor has to be placed on the VDD pin to

stabilize the regulated output voltage. The VDD pin is

intended to supply a microcontroller. The pin is current limited

against shorts to GND and over-temperature protected.

The ESD structure on this pin allows for excursion up to

+40 V and down to -27 V, allowing this pin to be connected

directly to the battery line. It is strongly recommended to

connect a 10 kohm resistor in series with this pin for

protection purposes.

During Stop Mode, the voltage regulator does not operate

with its full drive capabilities and the output current is limited.

During Sleep Mode, the regulator output is completely shut

down.

HALL SENSOR SWITCHABLE SUPPLY PIN (HVDD)

This pin provides a switchable supply for external hall

sensors. While in Normal Mode, this current limited output

can be controlled through the SPI.

33910

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FUNCTIONAL DEVICE OPERATIONS

OPERATIONAL MODES

FUNCTIONAL DEVICE OPERATIONS

OPERATIONAL MODES

The VDD regulator is ON and delivers its full current

capability.

If an external resistor is connected between the WDCONF

pin and the Ground, the window watchdog function will be

enabled.

INTRODUCTION

The 33910 offers three main operating modes: Normal

(Run), Stop, and Sleep (Low Power). In Normal Mode, the

device is active and is operating under normal application

conditions. The Stop and Sleep Modes are low power modes

with wake-up capabilities.

The wake-up input (L1) can be read as digital input or have

its voltage routed through the analog-multiplexer.

In Stop Mode, the voltage regulator still supplies the MCU

with V_DD(limited current capability), while in Sleep Mode the

voltage regulator is turned off (V_DD= 0 V).

The LIN interface has slew rate and timing compatible with

the LIN protocol specification 2.0, 2.1 and SAEJ2602. The

LIN bus can transmit and receive information.

Wake-up from Stop Mode is initiated by a wake-up

interrupt. Wake-up from Sleep Mode is done by a reset and

the voltage regulator is turned back on.

The high side switches are active and have PWM

capability according to the SPI configuration.

The selection of the different modes is controlled by the

MOD1:2 bits in the Mode Control Register (MCR).

The interrupts are generated to report failures for V_SUP

over/under-voltage, thermal shutdown, or thermal shutdown

prewarning on the main regulator.

Figure 14 describes how transitions are done between the

different operating modes. Table 7, 28, gives an overview of

the operating modes.

SLEEP MODE

The Sleep Mode is a low power mode. From Normal

Mode, the device enters into Sleep Mode by sending one SPI

command through the Mode Control Register (MCR), or (V_DD

low > 150 ms) with V_SUV= 0. When in Reset Mode, a V_DD

RESET MODE

The 33910 enters the Reset Mode after a power up. In this

mode, the RST pin is low for 1.0 ms (typical value). After this

delay, it enters the Normal Request Mode and the RST pin is

driven high.

under-voltage condition with no V_SUPunder-voltage (V_SUV

=

0) will send the device to Sleep Mode. All blocks are in their

lowest power consumption condition. Only some wake-up

sources (wake-up input with or without cyclic sense, forced

wake-up and LIN receiver) are active. The 5.0 V regulator is

OFF. The internal low-power oscillator may be active if the IC

is configured for cyclic-sense. In this condition, one of the

high side switches is turned on periodically and the wake-up

input is sampled.

The Reset Mode is entered if a reset condition occurs (V_DD

low, watchdog trigger fail, after wake-up from Sleep Mode,

Normal Request Mode timeout occurs).

NORMAL REQUEST MODE

This is a temporary mode automatically accessed by the

device after the Reset Mode, or after a wake-up from Stop

Mode.

Wake-up from Sleep Mode is similar to a power-up. The

device goes in Reset Mode except that the SPI will report the

wake-up source and the BATFAIL flag is not set.

In Normal Request Mode, the VDD regulator is ON, the

RESET pin is High, and the LIN is operating in RX Only

Mode.

STOP MODE

As soon as the device enters in the Normal Request Mode

an internal timer is started for 150 ms (typical value). During

these 150 ms, the MCU must configure the Timing Control

Register (TIMCR) and the Mode Control Register (MCR) with

MOD2 and MOD1 bits set = 0, to enter the Normal Mode. If

within the 150 ms timeout, the MCU does not command the

33910 to Normal Mode, it will enter in Reset Mode. If the

WDCONF pin is grounded in order to disable the watchdog

function, it goes directly in Normal Mode after the Reset

Mode.

The Stop Mode is the second low power mode, but in this

case the 5.0 V regulator is ON with limited current drive

capability. The application MCU is always supplied while the

33910 is operating in Stop Mode.

The device can enter into Stop Mode only by sending the

SPI command. When the application is in this mode, it can

wake-up from the 33910 side (for example: cyclic sense,

force wake-up, LIN bus, wake inputs) or the MCU side (CS,

RST pins). Wake-up from Stop Mode will transition the 33910

to Normal Request Mode and generates an interrupt except

if the wake-up event is a low to high transition on the CS pin

or comes from the RST pin.

NORMAL MODE

In Normal Mode, all 33910 functions are active and can be

controlled by the SPI interface and the PWMIN pin.

33910

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FUNCTIONAL DEVICE OPERATIONS

OPERATIONAL MODES

Normal Request Timeout Expired (t_NRTOUT

)

Normal Request timeout expired (NR_TOUT

)

V

Low

V

DD

V_DDHigh and

Power Up

Reset Delay (t

) Expired

V_DDHigh and Reset Delay (t_RST) expired

RST

Power

Down

Normal

Request

Reset

V_DDLow

Normal

WD Failed

WD failed

V_DDLL_owO₍W_>NR(>t_N

_reT) Expired

d

V_DD

)

_TOUTR

e

T

x

O

pi

U

and VSUV = 0

Sleep Command

SLEEP Command

W_Wak_ae_ke-_-u_Up_p(_(RR_ee_ss_ete₎t)

Sleep

Stop

V_VLow

_DDLow

DD

Legend

WD: Watchdog

Notes:

WD Disabled: Watchdog disabled (WDCONF pin connected to GND)

WD - means Watchdog

WD Trigger: Watchdog is triggered by SPI command

WD disabled - means Watchdog disabled (WDCONF terminal connected to GND)

WD Failed: No watchdog trigger or trigger occurs in closed window

WD trigger – means Watchdog is triggered by SPI command

Stop Command: Stop command sent via SPI

WD failed – means no Watchdog trigger or trigger occurs in closed window

Sleep Command: Sleep command sent via SPI

STOP Command - means STOP command sent via SPI

Wake-up from Stop Mode: L1 state change, LIN bus wake-up, Periodic wake-up, CS rising edge wake-up or RST wake-up.

SLEEP Command - means SLEEP command send via SPI

Wake-up from Sleep Mode: L1 state change, LIN bus wake-up, Periodic wake-up.

Wake-Up - means L1 or L2 state change or LIN bus wake up or SS rising edge

Figure 14. Operating Modes and Transitions

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FUNCTIONAL DEVICE OPERATIONS

OPERATIONAL MODES

Table 7. Operating Modes Overview

Normal

Mode

Function

Reset Mode Normal Request Mode

Stop Mode

Sleep Mode

VDD

HVDD

HSx

Full

SPI⁽⁶⁰⁾

Full

SPI

Stop

-

SPI/PWM⁽⁶¹⁾

SPI

SPI/PWM

SPI

Note⁽⁶²⁾

-

Note⁽⁶³⁾

-

Analog Mux

L1

-

Input

Wake-up

LIN

-

Rx-Only

Full/Rx-Only Rx-Only/Wake-up Wake-up

Watchdog

-

150 ms (typ.) timeout

V_SUP/V_DD

On⁽⁶⁴⁾/Off

V_SUP/V_DD

-

Voltage

V_SUP/V_DD

V_DD

Monitoring

Notes

60. Operation can be enabled/controlled by the SPI.

61. Operation can be controlled by the PWMIN input.

62. HSx switches can be configured for cyclic sense operation in Stop Mode.

63. HSx switches can be configured for cyclic sense operation in Sleep Mode.

64. Windowing operation when enabled by an external resistor.

Low-voltage Interrupt:

INTERRUPTS

Interrupts are used to signal a microcontroller that a

peripheral needs to be serviced. The interrupts which can be

generated, change according to the operating mode. While in

Normal and Normal Request Modes, the 33910 signals

through interrupts special conditions which may require a

MCU software action. Interrupts are not generated until all

pending wake-up sources are read in the Interrupt Source

Register (ISR).

Signals when the supply line (VS1) voltage drops below

the VSUV threshold (V_SUV).

High-voltage Interrupt:

Signals when the supply line (VS1) voltage increases

above the VSOV threshold (V_SOV).

Over-temperature Prewarning:

While in Stop Mode, interrupts are used to signal wake-up

events. Sleep Mode does not use interrupts. Wake-up is

performed by powering-up the MCU. In Normal and Normal

Request Mode the wake-up source can be read by SPI.

Signals when the 33910 temperature has reached the pre-

shutdown warning threshold. It is used to warn the MCU that

an over-temperature shutdown in the main 5.0 V regulator is

imminent.

The interrupts are signaled to the MCU by a low logic level

of the IRQ pin, which will remain low until the interrupt is

acknowledged by a SPI read command of the ISR register.

The IRQ pin will then be driven high.

LIN Over-temperature Shutdown / TXD Stuck At

Dominant / RXD Short-circuit:

These signal fault conditions within the LIN interface will

cause the LIN driver to be disabled. In order to restart the

operation, the fault must be removed and TXD must go

recessive.

Interrupts are only asserted while in Normal, Normal

Request and Stop Mode. Interrupts are not generated while

the RST pin is low.

The following is a list of the interrupt sources in Normal and

Normal Request Modes. Some of these can be masked by

writing to the SPI - Interrupt Mask Register (IMR).

High Side Over-temperature Shutdown:

Signals a shutdown in the high side outputs.

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FUNCTIONAL DEVICE OPERATIONS

OPERATIONAL MODES

In order to select and activate direct wake-up from L1

input, the Wake-up Control Register (WUCR) must be

configured with appropriate L1WE input enabled or disabled.

The wake-up input’s state is read through the Wake-up

Status Register (WUSR).

RESET

To reset a MCU the 33910 drives the RST pin low for the

time the reset condition lasts.

After the reset source is removed, the state machine will

drive the RST output low for at least 1.0 ms (typical value)

before driving it high.

L1 input is also used to perform cyclic-sense wake-up.

Note: Selecting an L1 input in the analog multiplexer

before entering low power mode will disable the wake-up

capability of the L1 input

In the 33910, four main reset sources exist:

5.0 V Regulator Low-voltage-Reset (V_RSTTH

)

The 5.0 V regulator output V_DDis continuously monitored

against brown outs. If the supply monitor detects that the

voltage at the VDD pin has dropped below the reset threshold

V_RSTTHthe 33910 will issue a reset. In case of over-

temperature, the voltage regulator will be disabled and the

voltage monitoring will issue a VDDOT Flag independently of

the V_DDvoltage.

Wake-up from Wake-up input (L1) with cyclic sense timer

enabled

The SBCLIN can wake-up at the end of a cyclic sense

period if on the wake-up input line (L1) a state change occurs.

One or both HSx switch can be activated in Sleep or Stop

Modes from an internal timer. Cyclic sense and force wake-

up are exclusive. If cyclic sense is enabled, the force wake-

up can not be enabled.

Window Watchdog Overflow

In order to select and activate the cyclic sense wake-up

from the L1 input, before entering in low power modes (Stop

or Sleep Modes), the following SPI set-up has to be

performed:

If the watchdog counter is not properly serviced while its

window is open, the 33910 will detect an MCU software run-

away and will reset the microcontroller.

In WUCR: select the L1 input to WU-enable.

In HSCR: enable the desired HSx.

Wake-up From Sleep Mode

During Sleep Mode, the 5V regulator is not active, hence

all wake-up requests from Sleep Mode require a power-up/

reset sequence.

• In TIMCR: select the CS/WD bit and determine the

cyclic sense period with CYSTx bits.

• Perform Goto Sleep/Stop command.

External Reset

Forced Wake-up

The 33910 has a bidirectional reset pin which drives the

device to a safe state (same as Reset Mode) for as long as

this pin is held low. The RST pin must be held low long

enough to pass the internal glitch filter and get recognized by

the internal reset circuit. This functionality is also active in

Stop Mode.

The 33910 can wake-up automatically after a

predetermined time spent in Sleep or Stop Mode. Cyclic

sense and Forced wake-up are exclusive. If Forced wake-up

is enabled, the Cyclic Sense can not be enabled.

To determine the wake-up period, the following SPI set-up

has to be sent before entering in low power modes:

After the RST pin is released, there is no extra t_RSTto be

considered.

• In TIMCR: select the CS/WD bit and determine the low

power mode period with CYSTx bits.

WAKE-UP CAPABILITIES

• In HSCR: all HSx bits must be disabled.

Once entered into one of the low-power modes (Sleep or

Stop) only wake-up sources can bring the device into Normal

Mode operation.

CS Wake-up

While in Stop Mode, a rising edge on the CS will cause a

wake-up. The CS wake-up does not generate an interrupt,

and is not reported on SPI.

In Stop Mode, a wake-up is signaled to the MCU as an

interrupt, while in Sleep Mode the wake-up is performed by

activating the 5.0 V regulator and resetting the MCU. In both

cases the MCU can detect the wake-up source by accessing

the SPI registers and reading the Interrupt Source Register.

There is no specific SPI register bit to signal a CS wake-up or

external reset. If necessary this condition is detected by

excluding all other possible wake-up sources.

LIN Wake-up

While in the low-power mode, the 33910 monitors the

activity on the LIN bus. A dominant pulse larger than t_PROPWL

followed by a dominant to recessive transition will cause a

LIN wake-up. This behavior protects the system from a short

to ground bus condition. The bit RXONLY = 1 from LINCR

Register disables the LIN wake-up from Stop Mode.

Wake-up from Wake-up input (L1) with cyclic sense

disabled

The wake-up line is dedicated to sense state changes of

external switch and wake-up the MCU (in Sleep or Stop

Mode).

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FUNCTIONAL DEVICE OPERATIONS

OPERATIONAL MODES

RST Wake-up

WINDOW CLOSED

NO WATCHDOG CLEAR

ALLOWED

WINDOW OPEN

FOR WATCHDOG

CLEAR

While in Stop Mode, the 33910 can wake-up when the

RST pin is held low long enough to pass the internal glitch

filter. Then, the 33910 will change to Normal Request or

Normal Modes depending on the WDCONF pin

configuration. The RST wake-up does not generate an

interrupt and is not reported via SPI.

From Stop Mode, the following wake-up events can be

configured:

WD TIMING X 50%

• Wake-up from L1 input without cyclic sense

• Cyclic sense wake-up inputs

• Force wake-up

WD PERIOD (t

)

PWD

WD TIMING SELECTED BY RESISTOR

ON WDCONF PIN

• CS wake-up

• LIN wake-up

• RST wake-up

Figure 15. Window Watchdog Operation

To disable the watchdog function in Normal Mode the user

must connect the WDCONF pin to ground. This measure

effectively disables Normal Request Mode. The WDOFF bit

in the Watchdog Status Register (WDSR) will be set. This

condition is only detected during Reset Mode.

From Sleep Mode, the following wake-up events can be

configured:

• Wake-up from L1 input without cyclic sense

• Cyclic sense wake-up inputs

• Force wake-up

If neither a resistor nor a connection to ground is detected,

the watchdog falls back to the internal lower precision

timebase of 150 ms (typ.) and signals the faulty condition

through the Watchdog Status Register (WDSR).

• LIN wake-up

WINDOW WATCHDOG

The 33910 includes a configurable window watchdog

which is active in Normal Mode. The watchdog can be

configured by an external resistor connected to the WDCONF

pin. The resistor is used to achieve higher precision in the

timebase used for the watchdog.

The watchdog timebase can be further divided by a

prescaler which can be configured by the Timing Control

Register (TIMCR). During Normal Request Mode, the

window watchdog is not active but there is a 150 ms (typ.)

timeout for leaving the Normal Request Mode. In case of a

timeout, the 33910 will enter into Reset Mode, resetting the

microcontroller before entering again into Normal Request

Mode.

SPI clears are performed by writing through the SPI in the

MOD bits of the Mode Control Register (MCR).

During the first half of the SPI timeout, watchdog clears are

not allowed, but after the first half of the SPI timeout window,

the clear operation opens. If a clear operation is performed

outside the window, the 33910 will reset the MCU, in the

same way as when the watchdog overflows.

FAULTS DETECTION MANAGEMENT

The 33910 has the capability to detect faults like an over

or under-voltage on VS1, TxD in permanent Dominant State,

Over-temperature on HS, LIN. It is able to take corrective

actions accordingly. Most of faults are monitoring through

SPI and the Interrupt pin. The microcontroller can also take

actions.

The following table summarizes all fault sources the

device is able to detect with associated conditions. The status

for a device recovery and the SPI or pins monitoring are also

described.

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FUNCTIONAL DEVICE OPERATIONS

OPERATIONAL MODES

Table 8. Fault Detection Management Conditions

MONITORING⁽⁶⁶⁾

BLOCK

FAULT

MODE

CONDITION

FALLOUT

RECOVERY

REG (FLAG,

BIT)

INTERRUPT

V

<3.0 V (typ)

SUP

All modes

-

Condition gone

VSR (BATFAIL, 0)

-

BATTERY FAIL

then power-up

IRQ low +

In Normal mode, HS

> 19.25 V (typ) shutdown if bit

Condition gone, to

re-enable HSwrite to VSR (VSOV,3)

HSCR registers

VSUP OVER-

VOLTAGE

V

ISR (0101)

(67)

SUP

HVSE=1 (reg MCR)

Normal, Normal

Request

IRQ low + ISR

(0101)

VSUP UNDER-

VOLTAGE

V

< 6.0 V (typ)

-

VSR (VSUV,2)

Power Supply

VDD UNDER-

VOLTAGE

(65)

All except Sleep

< 4.5 V (typ)

Reset

-

DD

Condition gone

Temperature >

115°C (typ)

IRQ low + ISR

(0101)

VDD OVER-TEMP

PREWARNING

-

VSR (VDDOT,1)

All except Low

Power modes

Temperature >

170°C (typ)

VDD shutdown,

Reset then Sleep

VDD OVER-

TEMPERATURE

-

RXD pin shorted to

GND or 5 V

LINSR,

(RXSHORT,3)

RXD PIN SHORT

CIRCUIT

LIN trans shutdown

LIN transmitter re-

enabled once the

LINSR (TXDOM,2)

conditionisgoneand

TXD PIN

PERMANENT

DOMINANT

Normal, Normal

Request

TXD pin low for more

than 1s (typ)

IRQ low + ISR

(0100)

LIN

(67)

LIN transmitter

shutdown

TXD is high

Temperature >

160°C (typ)

LIN DRIVER OVER-

TEMPERATURE

LINSR (LINOT,1)

Condition gone, to

All flags in HSSR

re-enable HS write to

are set

HIGH SIDE DRIVERS

OVER-

TEMPERATURE

Temperature >

160°C (typ)

Both HS thermal

shutdown

IRQ low + ISR

(0010)

(67)

HSCR reg

HS1 OPEN-LOAD

DETECTION

HSSR (HS1OP,1)

Current through HSx

< 5.0 mA (typ)

-

Normal, Normal

Request

High Side

HS2 OPEN-LOAD

DETECTION

HSSR (HS2OP,3)

Condition gone

-

HS1 OVER-

CURRENT

HSSR (HS1CL,0)

Current through HSx

tends to rise above

the current limit

60 mA (min)

HSx on with limited

current capability

60 mA (min)

HS2 OVER-

CURRENT

HSSR (HS2CL,2)

The MCU did not

command the device

to Normal mode

within the 150 ms

timeout after reset

NORMAL REQUEST

TIME-OUT EXPIRED

Normal Request

Reset

-

Watchdog

WD timeout or WD

clear within the

window closed

-

WATCHDOG

TIMEOUT

Normal

WDSR (WDTO, 3)

WD internal lower

precision timebase

150 ms (typ)

Connect WDCONF

to a resistor or to

GND

WDCONF pin is

floating

WDSR (WDERR, 2)

WATCHDOG ERROR

Notes

65.

When in Reset mode a VDD under-voltage condition combined with no V

under-voltage (VSUV=0) will send the device to Sleep mode.

SUP

66.

67.

Registers to be read when back in Normal Request or Normal Mode depending on the fault. Interrupts only generated in Normal, Normal Request and Stop modes

Unless masked, If masked IRQ remains high and the ISR flags are not set.

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FUNCTIONAL DEVICE OPERATIONS

OPERATIONAL MODES

The graph below illustrates the internal chip temp sense

obtained per characterization at 3 temperatures with 3

different lots and 30 samples.

TEMPERATURE SENSE GAIN

The analog multiplexer can be configured via SPI to allow

the ADOUT0 pin to deliver the internal junction temperature

of the device.

Temperature Sense Analog Output Voltage

5

4.5

4

3.5

3

2.5

2

-50

0

50

100

150

Temperature (°C)

Figure 16. Temperature Sense Gain

The high side switches are controlled by the bits HS1:2 in

the High Side Control Register (HSCR).

HIGH SIDE OUTPUT PINS HS1 AND HS2

These outputs are two high side drivers intended to drive

small resistive loads or LEDs incorporating the following

features:

PWM Capability (direct access)

Each high side driver offers additional (to the SPI control)

direct control via the PWMIN pin.

• PWM capability (software maskable)

• Open load detection

If both the bits HS1 and PWMHS1 are set in the High Side

Control Register (HSCR), then the HS1 driver is turned on if

the PWMIN pin is high and turned of if the PWMIN pin is low.

This applies to HS2 configuring HS2 and PWMHS2 bits.

• Current limitation

• Over-temperature shutdown (with maskable interrupt)

• High-voltage shutdown (software maskable)

• Cyclic sense

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FUNCTIONAL DEVICE OPERATIONS

OPERATIONAL MODES

Interrupt

Control

Module

V_DD

HVSE

V_DD

PWMIN

PWMHSx

VS2

MOD1:2

HSx

High Side Driver

charge pump

open load detection

current limitation

on/off

Control

HSxOP

HSxCL

Status

over-temperture shutdown (interrupt maskable)

high voltage shutdown (maskable)

HSx

Wakeup

Module

Figure 17. High Side Drivers HS1 and HS2

Open Load Detection

A write to the High Side Control Register (HSCR), when

the over-temperature condition is gone, will re-enable the

high side drivers.

Each high side driver signals an open load condition if the

current through the high side is below the open load current

threshold.

High-voltage Shutdown

The open load condition is indicated with the bits HS1OP

and HS2OP in the High Side Status Register (HSSR).

In case of a high voltage condition and if the high voltage

shutdown is enabled (bit HVSE in the Mode Control Register

(MCR) is set both high side drivers are shut down.

Current Limitation

A write to the High Side Control Register (HSCR), when

the high voltage condition is gone, will re-enable the high side

drivers.

Each high side driver has an output current limitation. In

combination with the over-temperature shutdown the high-

side drivers are protected against over-current and short-

circuit failures.

Sleep And Stop Mode

When the driver operates in the current limitation area, it is

indicated with the bits HS1CL and HS2CL in the HSSR.

The high side drivers can be enabled to operate in Sleep

and Stop Mode for cyclic sensing. Also see Table 7,

Operating Modes Overview.

Note: If the driver is operating in current limitation mode,

excessive power might be dissipated.

LIN PHYSICAL LAYER

Over-temperature Protection (HS Interrupt)

The LIN bus pin provides a physical layer for single-wire

communication in automotive applications. The LIN physical

layer is designed to meet the LIN physical layer specification

and has the following features:

Both high side drivers are protected against over-

temperature. In case of an over-temperature condition both

high side drivers are shut down and the event is latched in the

Interrupt Control Module. The shutdown is indicated as HS

Interrupt in the Interrupt Source Register (ISR).

• LIN physical layer 2.0, 2.1 and SAEJ2602 compliant

• Slew rate selection

• Over-temperature shutdown

• Advanced diagnostics

A thermal shutdown of the high side drivers is indicated by

setting all HSxOP and HSxCL bits simultaneously.

If the bit HSM is set in the Interrupt Mask Register (IMR),

then an interrupt (IRQ) is generated.

The LIN driver is a low side MOSFET with thermal

shutdown. An internal pull-up resistor with a serial diode

structure is integrated, so no external pull-up components are

33910

Analog Integrated Circuit Device Data

Freescale Semiconductor

33

FUNCTIONAL DEVICE OPERATIONS

OPERATIONAL MODES

required for the application in a slave node. The fall time from

dominant to recessive and the rise time from recessive to

dominant is controlled. The symmetry between both slopes is

guaranteed.

LIN Pin

The LIN pin offers a high susceptibility immunity level from

external disturbance, guaranteeing communication during

external disturbance.

WAKE-UP

MODULE

LIN

Wake-up

MOD1:2

LSR0:1

VS1

LIN DRIVER

J2602

RXONLY

RXSHORT

TXDOM

LINOT

Slope and Slew Rate Control

Over-temperature Shutdown (interrupt maskable)

30 K

LIN

TXD

RXD

SLOPE

CONTROL

LGND

WAKE-UP

FILTER

RECEIVER

Figure 18. LIN Interface

Slew Rate Selection

V_SUPdown to 4.6 V (typical value) and then the

communication is interrupted.

The slew rate can be selected for optimized operation at

10.4 and 20 kBit/s as well as a fast baud rate for test and

programming. The slew rate can be adapted with the bits

LSR1:0 in the LIN Control Register (LINCR). The initial slew

rate is optimized for 20 kBit/s.

The (DIS_J2602) bit is set per default to 0.

Over-temperature Shutdown (LIN Interrupt)

The output low side FET is protected against over-

temperature conditions. In case of an over-temperature

condition, the transmitter will be shut down and the LINOT bit

in the LIN Status Register (LINSR) is set.

J2602 Conformance

To be compliant with the SAE J2602-2 specification, the

J2602 feature has to be enabled in the LINCR Register (bit

DIS_J2602 sets to 0). The LIN transmitter is disabled in case

of a V_SUPunder-voltage condition occurs and TXD is in

Recessive State: the LIN bus goes in Recessive State and

RXD goes high. The LIN transmitter is not disabled if TXD is

in Dominant State. A deglitcher on V_SUP(t_{J2602_DEG}) is

implemented to avoid false switching.

If the LINM bit is set in the Interrupt Mask Register (IMR),

an Interrupt IRQ will be generated.

The transmitter is automatically re-enabled once the

condition is gone and TXD is high.

RXD Short-circuit Detection (LIN Interrupt)

The LIN transceiver has a short-circuit detection for the

RXD output pin. If the device transmits and in case of a short-

circuit condition, either 5.0 V or Ground, the RXSHORT bit in

If the (DIS_J2602) bit is set to 1, the J2602 feature is

disabled and the communication TXD-LIN-RXD works for

33910

Analog Integrated Circuit Device Data

Freescale Semiconductor

34

FUNCTIONAL DEVICE OPERATIONS

OPERATIONAL MODES

the LIN Status Register (LINSR) is set and the transmitter is

shut down.

LIN Receiver Operation Only

While in Normal Mode, the activation of the RXONLY bit

disables the LIN TXD driver. In case of a LIN error condition,

this bit is automatically set. If Stop mode is selected with this

bit set, the LIN wake-up functionality is disabled and the RXD

pin will reflect the state of the LIN bus.

If the LINM bit is set in the Interrupt Mask Register (IMR),

an Interrupt IRQ will be generated.

The transmitter is automatically re-enabled once the

condition is gone (transition on RXD) and TXD is high.

A read of the LIN Status Register (LINSR) without the RXD

pin short-circuit condition will clear the bit RXSHORT.

STOP Mode And Wake-up Feature

During Stop Mode operation, the transmitter of the

physical layer is disabled. The receiver is still active and able

to detect wake-up events on the LIN bus line.

TXD Dominant Detection (LIN Interrupt)

The LIN transceiver monitors the TXD input pin to detect a

stuck in dominant (0 V) condition. In case of a stuck condition

(TXD pin 0 V for more than 1 second (typ.)), the transmitter is

shut down and the TXDOM bit in the LIN Status Register

(LINSR) is set.

A dominant level longer than T_PROPWLfollowed by a rising

edge will generate a wake-up interrupt, and will be reported

in the Interrupt Source Register (ISR). Also see Figure 11,

page 21.

If the LINM bit is set in the IMR, an Interrupt IRQ will be

generated.

SLEEP Mode And Wake-up Feature

During Sleep Mode operation, the transmitter of the

physical layer is disabled. The receiver must be active to

detect wake-up events on the LIN bus line.

The transmitter is automatically re-enabled once TXD is

high.

A read of the LIN Status Register (LINSR) with the TXD pin

at 5.0 V will clear the bit TXDOM.

A dominant level longer than T_PROPWLfollowed by a rising

edge will generate a system wake-up (Reset), and will be

reported in the Interrupt Source Register (ISR). Also see

Figure 10, page 21.

33910

Analog Integrated Circuit Device Data

Freescale Semiconductor

35

FUNCTIONAL DEVICE OPERATIONS

LOGIC COMMANDS AND REGISTERS

• MISO—Master-in Slave-out

• SCLK—Serial Clock

33910 SPI INTERFACE AND CONFIGURATION

The serial peripheral interface creates the communication

link between a microcontroller (master) and the 33910.

A complete data transfer via the SPI consists of 1 byte.

The master sends 4 bits of address (A3:A0) + 4 bits of control

information (C3:C0) and the slave replies with 4 system

status bits (VMS,LINS,HSS,n.d.) + 4 bits of status information

(S3:S0).

The interface consists of four pins (see Figure 19):

•

CS—Chip Select

• MOSI—Master-out Slave-in

CS

Register Write Data

A0 C3 C2

MOSI

MISO

A3

A2

A1

C1

C0

S0

Register Read Data

VMS LINS HSS S3 S2

-

S1

SCLK

Read Data Latch

Write Data Latch

Rising: 33910 changes MISO/

MCU changes MOSI

Falling: 33910 samples MOSI/

MCU samples MISO

Figure 19. SPI Protocol

During the inactive phase of the CS (HIGH), the new data

transfer is prepared.

The rising edge of the Chip Select CS indicates the end of

the transfer and latches the write data (MOSI) into the

register. The CS high forces MISO to the high-impedance

state.

The falling edge of the CS indicates the start of a new data

transfer and puts the MISO in the low-impedance state and

latches the analog status data (Register read data).

Register reset values are described along with the reset

condition. Reset condition is the condition causing the bit to

be set to its reset value. The main reset conditions are:

With the rising edge of the SPI clock (SCLK), the data is

moved to MISO/MOSI pins. With the falling edge of the SPI

clock (SCLK), the data is sampled by the receiver.

- Power-On Reset (POR): the level at which the logic is

reset and BATFAIL flag sets.

The data transfer is only valid if exactly 8 sample clock

edges are present during the active (low) phase of CS.

- Reset Mode

- Reset done by the RST pin (ext_reset)

33910

Analog Integrated Circuit Device Data

Freescale Semiconductor

36

FUNCTIONAL DEVICE OPERATIONS

LOGIC COMMANDS AND REGISTERS

SPI REGISTER OVERVIEW

Table 9. System Status Register

BIT

Adress(A3:A0)

Register Name / Read/Write Information

SYSSR - System Status Register

7

6

5

4

$0 - $F

R

VMS

LINS

HSS

-

Table 10 summarizes the SPI Register content for Control Information (C3:C0)=W and status information (S3:S0) = R.

Table 10. SPI Register Overview

BIT

Adress(A3:A0)

Register Name / Read/Write Information

3

HVSE

VSOV

0

2

0

1

0

MOD1

BATFAIL

L1WE

L1

MCR - Mode Control Register

VSR - Voltage Status Register

WUCR - Wake-up Control Register

WUSR - Wake-up Status Register

LINCR - LIN Control Register

LINSR - LIN Status Register

W

R

MOD2

VDDOT

0

$0

$1

$2

$3

$4

$5

$6

$7

VSUV

0

R

W

R

-

R

-

L1

W

R

DIS_J2602

RXSHORT

PWMHS2

HS2OP

RXONLY

TXDOM

PWMHS1

HS2CL

WD2

LSR1

LINOT

HS2

LSR0

0

LINSR - LIN Status Register

R

0

HSCR - High Side Control Register

HSSR - High Side Status Register

W

R

HS1

HS1OP

WD1

CYST1

WDOFF

MX1

HS1CL

WD0

CYST0

WDWO

MX0

R

TIMCR - Timing Control Register

W

CS/WD

$A

CYST2

WDERR

MX2

WDSR - Watchdog Status Register

AMUXCR - Analog Multiplexer Control Register

CFR - Configuration Register

R

WDTO

L1DS

HVDD

HSM

$B

$C

$D

W

R

CYSX8

0

IMR - Interrupt Mask Register

LINM

ISR1

VMM

ISR0

$E

$F

ISR - Interrupt Source Register

ISR3

ISR2

ISR - Interrupt Source Register

R

ISR3

ISR2

33910

Analog Integrated Circuit Device Data

Freescale Semiconductor

37

FUNCTIONAL DEVICE OPERATIONS

LOGIC COMMANDS AND REGISTERS

REGISTER DEFINITIONS

HS1CL

HS1OP

HS2CL

HS2OP

System Status Register - SYSSR

HSS

The System Status Register (SYSSR) is always

transferred with every SPI transmission and gives a quick

system status overview. It summarizes the status of the

Voltage Monitor Status (VMS), LIN Status (LINS) and High

Side Status (HSS).

Figure 22. High Side Status

Mode Control Register - MCR

Table 11. System Status Register

The Mode Control Register (MCR) allows switching

between the operation modes and to configure the 33910.

Writing the MCR will return the VSR.

S7

S6

S5

S4

Read

VMS

LINS

HSS

-

Table 12. Mode Control Register - $0

VMS - Voltage Monitor Status

C3

C2

C1

C0

This read-only bit indicates that one or more bits in the

VSR are set.

Write

HVSE

0

MOD2

MOD1

1 = Voltage Monitor bit set

0 = None

Reset

Value

1

0

-

Reset

Condition

POR

BATFAIL

VDDOT

VMS

HVSE - High-Voltage Shutdown Enable

VSUV

VSOV

This write-only bit enables/disables automatic shutdown of

the high side drivers during a high-voltage VSOV condition.

1 = automatic shutdown enabled

0 = automatic shutdown disabled

Figure 20. Voltage Monitor Status

LINS - LIN Status

MOD2, MOD1 - Mode Control Bits

This read-only bit indicates that one or more bits in the

LINSR are set.

These write-only bits select the operating mode and allow

clearing the watchdog in accordance with Table 10 Mode

Control Bits.

1 = LIN Status bit set

0 = None

Table 13. Mode Control Bits

MOD2

MOD1

Description

0

1

0

1

0

1

Normal Mode

Stop Mode

LINOT

LINS

TXDOM

Sleep Mode

RXSHORT

Normal Mode + Watchdog Clear

Figure 21. LIN Status

Voltage Status Register - VSR

Returns the status of the several voltage monitors. This

register is also returned when writing to the Mode Control

Register (MCR).

HSS - High Side Switch Status

This read-only bit indicates that one or more bits in the

HSSR are set.

Table 14. Voltage Status Register - $0/$1

1 = High Side Status bit set

0 = None

S3

S2

S1

S0

Read

VSOV

VSUV

VDDOT

BATFAIL

33910

Analog Integrated Circuit Device Data

Freescale Semiconductor

38

FUNCTIONAL DEVICE OPERATIONS

LOGIC COMMANDS AND REGISTERS

VSOV - V_SUPOver-voltage

Table 15. Wake-Up Control Register - $2

This read-only bit indicates an over-voltage condition on

the VS1 pin.

C3

C2

C1

C0

1 = Over-voltage condition.

0 = Normal condition.

Write

0

L1WE

Reset

Value

1

VSUV - V_SUPUnder-voltage

This read-only bit indicates an under-voltage condition on

the VS1 pin.

Reset

Condition

POR, Reset Mode or ext_reset

1 = Under-voltage condition.

0 = Normal condition.

L1WE - Wake-up Input Enable

This write-only bit enables/disables the L1 input. In Stop

and Sleep Mode the L1WE bit activates the L1 input for wake-

up. If the L1 input is selected on the analog multiplexer, the

L1WE is masked to 0.

VDDOT - Main Voltage Regulator Over-temperature

Warning

This read-only bit indicates that the main voltage regulator

temperature reached the Over-temperature Prewarning

Threshold.

1 = Wake-up Input enabled.

0 = Wake-up Input disabled.

1 = Over-temperature Prewarning

0 = Normal

Wake-up Status Register - WUSR

This register is used to monitor the digital wake-up input

and is also returned when writing to the WUCR.

BATFAIL - Battery Fail Flag.

This read-only bit is set during power-up and indicates that

the 33910 had a Power-On-Reset (POR).

Table 16. Wake-up Status Register - $2/$3

S3

S2

S1

S0

Any access to the MCR or VSR will clear the BATFAIL flag.

1 = POR Reset has occurred

Read

-

L1

0 = POR Reset has not occurred

L1 - Wake-up input 1

Wake-Up Control Register - WUCR

This read-only bit indicates the status of the L1 input. If the

L1 input is not enabled, then the Wake-up status will return 0.

This register is used to control the digital wake-up input.

Writing the WUCR will return the Wake-Up Status Register

(WUSR).

After a wake-up from Stop or Sleep Mode this bit also

allows to verify the L1 input has caused the wake-up, by first

reading the Interrupt Status Register (ISR) and then reading

the WUSR. The source of the wake-up is only reported on the

first WUCR or WUSR access.

1 = L1 pin high, or L1 is the source of the wake-up.

0 = L1 pin low, disabled or selected as an analog input.

33910

Analog Integrated Circuit Device Data

Freescale Semiconductor

39

FUNCTIONAL DEVICE OPERATIONS

LOGIC COMMANDS AND REGISTERS

LIN Control Register - LINCR

Table 18. LIN Slew Rate Control

This register controls the LIN physical interface block.

Writing the LIN Control Register (LINCR) returns the LIN

Status Register (LINSR).

LSR1

LSR0

Description

0

1

0

1

0

1

Normal Slew Rate (up to 20 kb/s)

Slow Slew Rate (up to 10 kb/s)

Fast Slew Rate (up to 100 kb/s)

Reserved

Table 17. LIN Control Register - $4

C3

C2

C1

C0

Write

DIS_J2602

RXONLY

LSR1

LSR0

LIN Status Register - LINSR

Reset

Value

0

This register returns the status of the LIN physical

interface block and is also returned when writing to the

LINCR.

POR, Reset

Mode, ext_reset

or LIN failure

gone*

Reset

Condition

POR

Table 19. LIN Status Register - $4/$5

S3

S2

S1

S0

* LIN failure gone: if LIN failure (overtemp, TXD/RXD short) was set,

the flag resets automatically when the failure is gone.

Read

RXSHORT

TXDOM

LINOT

0

J2602 - LIN Dominant Voltage Select

RXSHORT - RXD Pin Short-circuit

This write-only bit controls the J2602 circuitry. If the

circuitry is enabled (bit sets to 0), the TXD-LIN-RXD

communication works down to the battery under-voltage

condition is detected. Below, the bus is in recessive state. If

the circuitry is disabled (bit sets to 1), the communication

TXD-LIN-RXD works down to 4.6 V (typical value).

This read-only bit indicates a short-circuit condition on the

RXD pin (shorted either to 5.0 V or to Ground). The short-

circuit delay must be a worst case of 8.0 µs to be detected

and to shut down the driver. To clear this bit, it must be read

after the condition is gone (transition detected on RXD pin).

The LIN driver is automatically re-enabled once the condition

is gone and TXD is high.

0 = Enabled J2602 feature.

1 = Disabled J2602 feature.

1 = RXD short-circuit condition.

0 = None.

RXONLY - LIN Receiver Operation Only

This write-only bit controls the behavior of the LIN

transmitter.

TXDOM - TXD Permanent Dominant

This read-only bit signals the detection of a TXD pin stuck

at dominant (Ground) condition and the resultant shutdown in

the LIN transmitter. This condition is detected after the TXD

pin remains in dominant state for more than 1 second (typical

value).

In Normal Mode, the activation of the RXONLY bit disables

the LIN transmitter. In case of a LIN error condition, this bit is

automatically set.

In Stop Mode this bit disables the LIN wake-up

functionality, and the RXD pin will reflect the state of the LIN

bus.

To clear this bit, it must be read after TXD has gone high.

The LIN driver is automatically re-enabled once TXD goes

High.

1 = only LIN receiver active (Normal Mode) or LIN wake-

up disabled (Stop Mode).

1 = TXD stuck at dominant fault detected.

0 = None.

0 = LIN fully enabled.

LSRx - LIN Slew-Rate

LINOT - LIN Driver Over-temperature

This write-only bit controls the LIN driver slew-rate in

accordance with Table 18.

This read-only bit signals that the LIN transceiver was

shutdown due to over-temperature. The transmitter is

automatically re-enabled after the over-temperature

condition is gone and TXD is high. The LINOT bit is cleared

after SPI read once the condition is gone.

1 = LIN over-temperature shutdown

0 = None

33910

Analog Integrated Circuit Device Data

Freescale Semiconductor

40

FUNCTIONAL DEVICE OPERATIONS

LOGIC COMMANDS AND REGISTERS

High Side Control Register - HSCR

Timing Control Register - TIMCR

This register controls the operation of the high side drivers.

Writing to this register returns the High Side Status Register

(HSSR).

This register allows to configure the watchdog, the cyclic

sense and Forced Wake-up periods. Writing to the Timing

Control Register (TIMCR) will also return the Watchdog

Status Register (WDSR).

Table 20. High Side Control Register - $6

Table 22. Timing Control Register - $A

C3

C2

C1

C0

C3

C2

C1

C0

Write

PWMHS2 PWMHS1

HS2

HS1

WD2

WD1

WD0

Reset

Value

Write

CS/WD

0

CYST2

CYST1

CYST0

Reset

Condition

POR, Reset Mode, ext_reset, HSx

over-temp or (VSOV & HVSE)

Reset

Value

POR

-

0

Reset

Condition

PWMHSx - PWM Input Control Enable.

POR

This write-only bit enables/disables the PWMIN input pin

to control the respective high side switch. The corresponding

high side switch must be enabled (HSx bit).

CS/WD - Cyclic Sense or Watchdog prescaler select

This write-only bit selects which prescaler is being written

to, the Cyclic Sense/Forced Wake-up prescaler or the

Watchdog prescaler.

1 = PWMIN input controls HSx output.

0 = HSx is controlled only by SPI.

1 = Cyclic Sense/Forced Wake-up Prescaler selected

0 = Watchdog Prescaler select

HSx - HSx Switch Control.

This write-only bit enables/disables the corresponding

high side switch.

WDx - Watchdog Prescaler

1 = HSx switch on.

0 = HSx switch off.

This write-only bits selects the divider for the watchdog

prescaler and therefore selects the watchdog period in

accordance with Table . This configuration is valid only if

windowing watchdog is active.

High Side Status Register - HSSR

This register returns the status of the high side switches

and is also returned when writing to the HSCR.

Table 23. Watchdog Prescaler

WD2

WD1

WD0

Prescaler Divider

Table 21. High Side Status Register - $6/$7

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

S3

S2

S1

S0

4

Read

HS2OP

HS2CL

HS1OP

HS1CL

6

High Side thermal shutdown

8

A thermal shutdown of the high side drivers is indicated by

setting all HSxOP and HSxCL bits simultaneously.

10

12

14

HSxOP - High Side Switch Open-Load Detection

This read-only bit signals that the high side switches are

conducting current below a certain threshold indicating

possible load disconnection.

CYSTx - Cyclic Sense Period Prescaler Select

This write-only bits selects the interval for the wake-up

cyclic sensing together with the bit CYSX8 in the

Configuration Register (CFR) (see page 43).

1 = HSx Open Load detected (or thermal shutdown)

0 = Normal

This option is only active if one of the high side switches is

enabled when entering in Stop or Sleep Mode. Otherwise, a

timed wake-up is performed after the period shown in Table .

HSxCL - High Side Current Limitation

This read-only bit indicates that the respective high side

switch is operating in current limitation mode.

Table 24. Cyclic Sense and Force Wake-up Interval

1 = HSx in current limitation (or thermal shutdown)

0 = Normal

CYSX8⁽⁶⁸⁾CYST2

CYST1

CYST0

Interval

X

0

No cyclic sense⁽⁶⁹⁾

33910

Analog Integrated Circuit Device Data

Freescale Semiconductor

41

FUNCTIONAL DEVICE OPERATIONS

LOGIC COMMANDS AND REGISTERS

Table 24. Cyclic Sense and Force Wake-up Interval

timeouts are disabled and the device automatically enters

Normal Mode out of Reset. This might be necessary for

software debugging and for programming the Flash memory.

CYSX8⁽⁶⁸⁾CYST2

CYST1

CYST0

Interval

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

20 ms

40 ms

1 = Watchdog is disabled

0 = Watchdog is enabled

0

60 ms

WDWO - Watchdog Window Open

0

80 ms

This read-only bit signals when the watchdog window is

open for clears. The purpose of this bit is for testing. Should

be ignored in case WDERR is High.

0

100 ms

120 ms

140 ms

160 ms

320 ms

480 ms

640 ms

800 ms

960 ms

1120 ms

0

1 = Watchdog window open

0 = Watchdog window closed

1

Analog Multiplexer Control Register - MUXCR

1

This register controls the analog multiplexer and selects

the divider ration for the L1 input divider.

1

Table 26. Analog Multiplexer Control Register -$C

C3

C2

C1

C0

Notes

68. bit CYSX8 is located in Configuration Register (CFR)

69. No Cyclic Sense and no Force Wake-up available.

Write

L1DS

MX2

MX1

MX0

Reset

Value

1

0

Watchdog Status Register - WDSR

Reset

Condition

This register returns the Watchdog status information and

is also returned when writing to the TIMCR.

POR

POR, Reset Mode or ext_reset

Table 25. Watchdog Status Register - $A/$B

L1DS - L1 Analog Input Divider Select

This write-only bit selects the resistor divider for the L1

analog input. Voltage is internally clamped to VDD.

S3

S2

S1

S0

Read

WDTO

WDERR WDOFF

WDWO

0 = L1 Analog divider: 1

1 = L1 Analog divider: 3.6 (typ.)

WDTO - Watchdog Timeout

MXx - Analog Multiplexer Input Select

This read-only bit signals the last reset was caused by

either a watchdog timeout or by an attempt to clear the

Watchdog within the window closed.

These write-only bits selects which analog input is

multiplexed to the ADOUT0 pin according to Table .

Any access to this register or the Timing Control Register

(TIMCR) will clear the WDTO bit.

When disabled or when in Stop or Sleep Mode, the output

buffer is not powered and the ADOUT0 output is left floating

to achieve lower current consumption.

1 = Last reset caused by watchdog timeout

0 = None

Table 27. Analog Multiplexer Channel Select

WDERR - Watchdog Error

MX2

MX1

MX0

Meaning

This read-only bit signals the detection of a missing

watchdog resistor. In this condition the watchdog is using the

internal, lower precision timebase. The Windowing function is

disabled.

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Disabled

Reserved

Die Temperature Sensor

VSENSE input

L1 input

1 = WDCONF pin resistor missing

0 = WDCONF pin resistor not floating

Reserved

WDOFF - Watchdog Off

Reserved

This read-only bit signals that the watchdog pin connected

to Ground and therefore disabled. In this case watchdog

Reserved

33910

Analog Integrated Circuit Device Data

Freescale Semiconductor

42

FUNCTIONAL DEVICE OPERATIONS

LOGIC COMMANDS AND REGISTERS

Configuration Register - CFR

HSM - High Side Interrupt Mask

This register controls the Hall Sensor Supply enable/

disable and the cyclic sense timing multiplier.

This write-only bit enables/disables interrupts generated in

the high side block.

1 = HS Interrupts Enabled

0 = HS Interrupts Disabled

Table 28. Configuration Register - $D

C3

C2

C1

C0

LINM - LIN Interrupts Mask

Write

HVDD

CYSX8

0

This write-only bit enables/disables interrupts generated in

the LIN block.

Reset

Value

0

1 = LIN Interrupts Enabled

0 = LIN Interrupts Disabled

POR, Reset

Mode or

ext_reset

Reset

Condition

POR

VMM - Voltage Monitor Interrupt Mask

This write-only bit enables/disables interrupts generated in

the Voltage Monitor block. The only maskable interrupt in the

Voltage Monitor Block is the V_SUPover-voltage interrupt.

HVDD - Hall Sensor Supply Enable

This write-only bit enables/disables the state of the hall

sensor supply.

1 = Interrupts Enabled

0 = Interrupts Disabled

1 = HVDD on

0 = HVDD off

Interrupt Source Register - ISR

CYSX8 - Cyclic Sense Timing x 8.

This register allows the MCU to determine the source of

the last interrupt or wake-up respectively. A read of the

register acknowledges the interrupt and leads IRQ pin to

high, in case there are no other pending interrupts. If there

are pending interrupts, IRQ will be driven high for 10µs and

then be driven low again.

This write-only bit influences the cyclic sense and Forced

Wake-up period as shown in Table .

1 = Multiplier enabled

0 = None

Interrupt Mask Register - IMR

This register is also returned when writing to the Interrupt

Mask Register (IMR).

This register allows masking of some of the interrupt

sources. No interrupt will be generated to the MCU and no

flag will be set in the ISR register. The 5.0V Regulator over-

temperature prewarning interrupt and Under-voltage (VSUV)

interrupts can not be masked and will always cause an

interrupt.

Table 30. Interrupt Source Register - $E/$F

S3

S2

S1

S0

Read

ISR3

ISR2

ISR1

ISR0

Writing to the IMR will return the ISR.

ISRx - Interrupt Source Register

Table 29. Interrupt Mask Register - $E

These read-only bits indicate the interrupt source following

Table . If no interrupt is pending then all bits are 0.

C3

C2

C1

C0

In case more than one interrupt is pending, the interrupt

sources are handled sequentially multiplex.

Write

HSM

0

LINM

VMM

Reset

Value

1

Reset

Condition

POR

33910

Analog Integrated Circuit Device Data

Freescale Semiconductor

43

FUNCTIONAL DEVICE OPERATIONS

LOGIC COMMANDS AND REGISTERS

Table 31. Interrupt Sources

ISR3 ISR2 ISR1 ISR0

Interrupt Source

Priority

none maskable

maskable

0

1

0

1

0

1

0

1

0

1

no interrupt

none

L1 Wake-up from Stop and Sleep Mode

-

HS Interrupt (Over-temperature)

Reserved

highest

-

LIN Wake-up

LIN Interrupt (RXSHORT, TXDOM, LIN OT)

Voltage Monitor Interrupt

(High Voltage)

Voltage Monitor Interrupt

(Low Voltage and VDD over-temperature)

Forced Wake-up

0

1

0

-

lowest

33910

Analog Integrated Circuit Device Data

Freescale Semiconductor

44

TYPICAL APPLICATION

The 33910 can be configured in several applications. The figure below shows the 33910 in the typical Slave Node Application.

V

BAT

D1

C2

C1

VDD

IRQ

Interrupt

Control Module

LVI, HVI, HTI, OCI

Voltage Regulator

5V Output Module

C5

C4

C3

AGND

HVDD

Hall Sensor Supply

VDD

Reset

Control Module

LVR, HVR, HTR, WD,

RST

IRQ

RST

Window

R1

Watchdog Module

PWMIN

TIMER

High Side Control

Module

HS1

HS2

MISO

MOSI

SCLK

CS

Chip Temp Sense Module

VBAT Sense Module

SPI

&

CONTROL

SPI

VSENSE

MCU

R2

L1

Analog Input Module

ADOUT0

A/D

Wake Up Module

Digital Input Module

RXD

TXD

LIN Physical Layer

SCI

A/D

LIN

C6

Typical Component Values:

C1 = 47 µF; C2 = C4 = 100 nF; C3 = 10 µF; C5 = 220 pF

R1 = 10 kΩ; R2 = 20 kΩ-200 kΩ

R7

Recommended Configuration of the not Connected Pins (NC):

Pin 15, 16, 17, 19, 20, 21, 22 = GND

Pin 11 = open (floating)

Pin 28 = this pin is not internally connected and may be used for PCB routing optimization.

33910

Analog Integrated Circuit Device Data

Freescale Semiconductor

45

PACKAGING

PACKAGE DIMENSIONS

PACKAGING

PACKAGE DIMENSIONS

Important For the most current revision of the package, visit www.Freescale.com and select Documentation, then under

Available Documentation column select Packaging Information.

AC SUFFIX (PB-FREE)

32-PIN LQFP

98ASH70029A

REVISION D

33910

Analog Integrated Circuit Device Data

46

Freescale Semiconductor

IMPORTANT FOR THE MOST CURRENT REVISION OF THE PACK-

AGE, VISIT WWW.FREESCALE.COM AND SELECT DOCUMENTATION,

PACKAGE DIMENSIONS (Continued)

AC SUFFIX (PB-FREE)

32-PIN LQFP

98ASH70029A

REVISION D

33910

Analog Integrated Circuit Device Data

Freescale Semiconductor

47

REVISION HISTORY

Revision Date

Description of Changes

5/2007

9/2007

•

Initial Release

1.0

2.0

•

Several textual corrections

Page 11: “Analog Output offset Ratio” changed to “Analog Output offset” +/-22mV

Page 11: VSENSE Input Divider Ratio adjusted to 5,0/5,25/5,5

Page 12: Common mode input impedance corrected to 75kΩ

Page 13/15: LIN PHYSICAL LAYER parameters adjusted to final LIN specification release

9/2007

2/2008

11/2008

•

Revision number incremented at engineering request.

Changed Functional Block Diagram on page 24.

3.0

4.0

5.0

•

Datasheet updated according to the Pass1.2 silicon version electrical parameters

Add Maximum Rating on I_{BUS_NO_GND}parameter

Added L1, Temperature Sense Analog Output Voltage per characterization⁽³⁸⁾, Internal Chip

Temperature Sense Gain per characterization at 3 temperatures⁽³⁸⁾See Figure 16, Temperature Sense

Gain, VSENSE Input Divider Ratio (RATIOVSENSE=Vsense/Vadout0) per characterization⁽³⁸⁾, and

VSENSE Output Related Offset per characterization⁽³⁸⁾parameters

•

Added Temperature Sense Gain section

Minor corrections to ESD Capability, ⁽²⁰⁾, Cyclic Sense ON Time from Stop and Sleep Mode⁽⁴⁷⁾, Lin Bus

Pin (LIN), Serial Data Clock Pin (SCLK), Master Out Slave In Pin (MOSI), Master In Slave Out Pin

(MISO), Digital/analog Pin (L1), Normal Request Mode, Sleep Mode, LIN Over-temperature Shutdown

/ TXD Stuck At Dominant / RXD Short-circuit:, Fault Detection Management Conditions, Lin Physical

Layer, LIN Interface, Over-temperature Shutdown (LIN Interrupt), LIN Receiver Operation Only, SPI

Protocol, L1 - Wake-up input 1, LIN Control Register - LINCR, and RXSHORT - RXD Pin Short-circuit

Updated Freescale form and style

•

33910

Analog Integrated Circuit Device Data

Freescale Semiconductor

48

How to Reach Us:

Home Page:

www.freescale.com

Web Support:

http://www.freescale.com/support

USA/Europe or Locations Not Listed:

Freescale Semiconductor, Inc.

Technical Information Center, EL516

2100 East Elliot Road

Tempe, Arizona 85284

+1-800-521-6274 or +1-480-768-2130

www.freescale.com/support

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Technical Information Center

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+44 1296 380 456 (English)

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www.freescale.com/support

Information in this document is provided solely to enable system and software

implementers to use Freescale Semiconductor products. There are no express or

implied copyright licenses granted hereunder to design or fabricate any integrated

circuits or integrated circuits based on the information in this document.

Freescale Semiconductor reserves the right to make changes without further notice to

any products herein. Freescale Semiconductor makes no warranty, representation or

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Freescale Semiconductor assume any liability arising out of the application or use of any

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limitation consequential or incidental damages. “Typical” parameters that may be

provided in Freescale Semiconductor data sheets and/or specifications can and do vary

in different applications and actual performance may vary over time. All operating

parameters, including “Typicals”, must be validated for each customer application by

customer’s technical experts. Freescale Semiconductor does not convey any license

under its patent rights nor the rights of others. Freescale Semiconductor products are

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LDCForFreescaleSemiconductor@hibbertgroup.com

MC33910

Rev. 5.0

12/2008


型号：	MC33910
厂家：	Freescale
描述：	LIN System Basis Chip with High Side Drivers LIN系统基础芯片，高边驱动器驱动器
文件：	总49页 (文件大小：872K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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