MC33975ATEK [FREESCALE]
Multiple Switch Detection Interface with Suppressed Wake-up and 32 mA Wetting Current; 与抑制唤醒和32毫安湿电流多交换检测接口
| 型号： | MC33975ATEK |
| 厂家： | 
Freescale |
| 描述： | Multiple Switch Detection Interface with Suppressed Wake-up and 32 mA Wetting Current |
| 文件： | 总32页 (文件大小：883K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: MC33975
Rev 10.0, 8/2011
Freescale Semiconductor
Advance Information
Multiple Switch Detection
Interface with Suppressed
Wake-up and 32 mA Wetting
Current
33975
33975A
MULTIPLE SWITCH
DETECTION INTERFACE WITH
SUPPRESSED WAKE-UP
The 33975 Multiple Switch Detection Interface with Suppressed
Wake-up is designed to detect the closing and opening of up to 22
switch contacts. The switch status, either open or closed, is transferred
to the microprocessor unit (MCU) through a serial peripheral interface
(SPI). The device also features a 22-to-1 analog multiplexer for
reading inputs as analog.
The 33975 device has two modes of operation, Normal and Sleep.
Normal mode allows programming of the device and supplies switch
contacts with pull-up or pull-down current as it monitors the switch
change of state. The Sleep mode provides low quiescent current,
which makes the 33975 ideal for automotive and industrial products
requiring low sleep state currents.
Improvements are a programmable interrupt timer for Sleep mode
that can be disabled, switch detection currents of 32 mA and 4.0 mA
for switch-to-ground inputs, and an interrupt bit that can be reset.
EK SUFFIX (PB-FREE)
98ASA10556D
32-PIN SOICW EP
Features
• Designed to operate from 5.5 V ≤ VPWR ≤ 28 V
• Switch input voltage: (33975: -14 to 38 V) (33975A: -14 to 40 V)
• Interfaces to microprocessor using 3.3 V/5.0 V SPI protocol
• Selectable wake-up on change of state
ORDERING INFORMATION
Temperature
Device
Package
Range (T )
A
MC33975TEK/R2
MC33975ATEK/R2
• 14 switch-to-ground inputs
-40 °C to 125 °C
32 SOICW-EP
• 8 programmable inputs (switches to battery or ground)
• Selectable wetting current (32 mA or 4.0 mA for switch-to-ground
inputs)
• Sleep State current V
100 μA, VDD 20 μA
PWR
• Pb-free packaging designated by suffix code EK
VDD
POWER SUPPLY
LVI
VBAT
VDD
VBAT
33975
SP0
SP1
VPWR
VBAT
ENABLE
VDD
SP7
WAKE
SG0
SG1
MCU
SI
SCLK
CS
MOSI
WATCHDOG
RESET
SCLK
CS
SG12
SG13
SO
MISO
INT
INT
AMUX
AN0
GND
Figure 1. 33975 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2005 - 2011. All rights reserved.
DEVICE VARIATIONS
DEVICE VARIATIONS
Table 1. Device Variations
Reference
Location
Device
Switch Input Voltage Range
33975
5
5
-14 to 38 V
-14 to 40 V
DC
DC
33975A
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
2
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
5.0 V
V
PWR
V
V
SP0
PWR PWR
V
, V , 5.0V
DD
VPWR
VDD
PWR
32.0
mA
4.0
mA
POR
Bandgap
Sleep PWR
GND
SP0
SP1
SP2
SP3
SP4
SP5
SP6
SP7
To
+
4.0 V
Ref
2.0
mA
16.0
mA
‚
SPI
Comparator
V
V
SP7
PWR PWR
32.0
mA
4.0
mA
5.0 V
Oscillator
and
Clock Control
V
PWR
To
SPI
+
4.0 V
Ref
2.0
mA
16.0
mA
‚
Comparator
5.0 V
Temperature
Monitor and
Control
5.0 V
V
V
SG0
5.0 V
125 kΩ
PWR PWR
32.0
mA
4.0
mA
V
PWR
5.0 V
SG0
SG1
SG2
SG3
SG4
SG5
SG6
SG7
SG8
SG9
SG10
SG11
SG12
SG13
WAKE
To
+
4.0 V
Ref
‚
SPI
WAKE Control
Comparator
V
DD
SPI Interface
and Control
125 kΩ
INT
INT Control
VDD
MUX Interface
40 μA
CS
SCLK
SI
VDD
SO
V
V
SG13
PWR PWR
32.0
mA
4.0
mA
V
DD
Analog Mux
Output
+
‚
AMUX
To
SPI
+
4.0 V
Ref
‚
Comparator
Figure 2. 33975 Simplified Internal Block Diagram
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
PIN CONNECTIONS
PIN CONNECTIONS
GND
SI
SCLK
CS
SO
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDD
AMUX
INT
SP7
SP6
2
3
4
SP0
SP1
SP2
SP3
SG0
SG1
SG2
SG3
SG4
SG5
SG6
VPWR
5
6
7
SP5
SP4
8
9
SG7
SG8
SG9
SG10
SG11
SG12
SG13
WAKE
10
11
12
13
14
15
16
Figure 3. 33975 Pin Connections
Table 2. Pin Definitions
A functional description of each Pin can be found in the Functional Pin Description section on page 12.
Pin
Pin Name
Formal Name
Description
Ground for logic, analog, and switch-to-battery inputs
SPI control data input pin from MCU to 33975
SPI control clock input pin
1
2
3
4
GND
SI
Ground
SPI Slave In
Serial Clock
Chip Select
SCLK
CS
SPI control chip select input pin from MCU to 33975. Logic [0] allows data to be
transferred in
Programmable switch-to-battery or switch-to-ground input pins
5–8
25–28
SPn
SGn
Programmable Switches 0–3
Programmable Switches 4–7
Switch-to-ground input pins
9–15,
18–24
Switch-to-Ground Inputs 0–6
Switch-to-Ground Inputs 13–7
Battery supply input pin. This pin requires external reverse battery protection.
Open drain wake-up output is designed to control a power supply enable pin
Open-drain output to MCU is used to indicate input switch change of state
Analog multiplex output
16
17
29
30
31
32
VPWR
WAKE
INT
Battery Input
Wake-up
Interrupt
AMUX
VDD
Analog Multiplex Output
Voltage Drain Supply
SPI Slave Out
3.3/5.0 V supply sets SPI communication level for the SO driver
Provides digital data from 33975 to the MCU
SO
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
4
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 3. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these limits may cause malfunction or permanent
damage to the device.
Rating
Symbol
Value
Unit
ELECTRICAL RATINGS
VDD Supply Voltage
–
–
–
–
–
–
-0.3 to 7.0
-0.3 to 7.0
-0.3 to 40
-0.3 to 50
-0.3 to 45
V
V
V
V
V
V
DC
DC
DC
DC
DC
DC
CS, SI, SO, SCLK, INT, AMUX
WAKE
VPWR Supply Voltage
VPWR Supply Voltage at -40 °C
Switch Input Voltage Range
33975
-14 to 38
-14 to 40
33975A
Frequency of SPI Operation (VDD = 5.0 V)
ESD Voltage(1)
–
6.0
MHz
V
VESD
±2000
±2000
±200
Human Body Model(2)
Applies to all non-input Pins
Machine Model
Charge Device Model
Corner Pins
750
500
Interior Pins
THERMAL RATINGS
Operating Temperature
Ambient
°C
TA
TJ
-40 to 125
-40 to 150
-40 to 125
Junction
Case
TC
Storage Temperature
Power Dissipation(3)
Notes
T
-55 to 150
1.7
°C
STG
P
W
D
1. ESD testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), the Machine Model (CZAP
200 pF, RZAP = 0 Ω), and the Charge Device Model.
=
2. All Programmable Switches (SP) and Switch-to-Ground (SG) input pins when tested individually.
3. Maximum power dissipation at TJ =150 °C junction temperature with no heatsink used.
4. Thermal resistance between the die and the exposed die pad.
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 3. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these limits may cause malfunction or permanent
damage to the device.
Rating
Symbol
Value
Unit
ELECTRICAL RATINGS
Thermal Resistance
Junction to Ambient
°C/W
R
71
JA
θ
R
1.2
Between the die and the exposed die pad(4)
Peak Package Reflow Temperature During Reflow(5), (6)
Notes
θJC
°C
TPPRT
Note 6
5. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
6. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes
and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
6
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics
Characteristics noted under conditions of 3.0 V ≤ VDD ≤ 5.5 V, 8.0 V ≤ VPWR ≤ 28 V, -40 °C ≤ TC ≤ 125 °C, unless otherwise
noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25 °C.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER INPUT
Supply Voltage
V
Supply Voltage Range Quasi-functional(7)
Fully Operational
V
V
V
5.5
8.0
28
–
–
–
8.0
28
PWR
PWR
PWR
(
(
(
QF
FO
QF
)
)
)
Supply Voltage Range Quasi-functional(8)
38/40
Supply Voltage
V
V
PWR(POR)
VPWR Supply Voltage Power On Reset
4.2
–
4.6
4.0
5.0
8.0
Supply Current
I
mA
μA
PWR(ON)
All Switches Open, Normal Mode, Tri-state Disabled
Sleep State Supply Current
I
PWR(SS)
Scan Timer = 64 ms, Switches Open
40
70
–
100
5.5
Logic Supply Voltage
V
3.0
V
DD
Logic Supply Current
I
mA
DD
All Switches Open, Normal Mode
–
–
0.25
10
0.5
20
Sleep State Logic Supply Current
Scan Timer = 64 ms, Switches Open
I
μA
DD(SS)
SWITCH INPUT
Pulse Wetting Current Switch-to-Battery (Current Sink)
I
I
mA
mA
PULSE
PULSE
5.5 V ≤ VPWR ≤ 28 V
12
15
18
Pulse Wetting Current Switch-to-Ground (Current Source)
5.5 V ≤ VPWR ≤ 8.0 V
8.0 V ≤ VPWR ≤ 28 V
7.0
24
9.0
32
–
36
Sustain Current Switch-to-Battery Input (Current Sink)
I
I
mA
mA
SUSTAIN
SUSTAIN
5.5 V ≤ VPWR ≤ 28 V
1.8
2.1
2.4
Sustain Current Switch-to-Ground Input (Current Source)
5.5 V ≤ VPWR ≤ 8.0 V
8.0 V ≤ VPWR ≤ 28 V
0.5
3.6
1.0
4.0
–
4.4
Sustain Current Matching Between Channels on Switch-to-Ground Inputs
I
%
MATCH
–
2.0
5.0
ISUS(MAX)
I
SUS(MIN)
-
X 100
ISUS(MIN)
Notes
7. Device operational. Wetting and sustain currents are reduced. Operating the analog multiplexer below 8.0 V is not recommended.
8. Thermal considerations must be taken when operating the device above 28 V.
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions of 3.0 V ≤ VDD ≤ 5.5 V, 8.0 V ≤ VPWR ≤ 28 V, -40 °C ≤ TC ≤ 125 °C, unless otherwise
noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25 °C.
Characteristic
SWITCH INPUT (CONTINUED)
Symbol
Min
Typ
Max
Unit
Input Offset Current when Selected as Analog
I
-2.0
-10
1.4
2.5
2.0
10
μA
OFFSET
Input Offset Voltage when Selected as Analog
V
mV
OFFSET
V
(SP&SGINPUTS) to AMUX output
Analog Operational Amplifier Output Voltage
V
mV
V
OL
Sink 250 μA
–
10
30
Analog Operational Amplifier Output Voltage
V
OH
Source 250 μA
V
- 0.1
–
4.0
–
–
DD
Switch Detection Threshold
Temperature Monitor(9), (10)
Temperature Monitor Hysteresis(10)
Notes
V
T
3.70
155
5.0
4.3
185
15
V
TH
°C
°C
LIM
T
10
LIM(HYS
)
9. Thermal shutdown of 16mA and 32mA pull-up and pull-down current sources only. 4.0mA and 2.0mA current source/sink and all other
functions remain active.
10. This parameter is guaranteed by design; however it is not production tested.
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
8
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions of 3.0 V ≤ VDD ≤ 5.5 V, 8.0 V ≤ VPWR ≤ 28 V, -40 °C ≤ TC ≤ 125 °C, unless otherwise
noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25 °C.
Characteristic
Symbol
Min
Typ
Max
Unit
DIGITAL INTERFACE
Input Logic High Voltage Thresholds(11)
Input Logic Low Voltage Thresholds(11)
SCLK, SI, Tri-state SO Input Current
V
0.7 x VDD
GND - 0.3
–
–
VDD + 0.3
0.2 x VDD
V
V
IH
V
IL
I
I
μA
SCLK, SI,
I
0.0 V to V
DD
SO(TRI)
-10
-10
30
–
–
10
10
CS Input Current
I
I
μA
CS
CS
CS = V
DD
CS Pull-up Current
CS = 0.0 V
μA
–
–
100
SO High State Output Voltage
V
V
SO(HIGH)
I
= -200 μA
V
- 0.8
VDD
SO(HIGH)
DD
SO Low State Output Voltage
= 1.6 mA
V
V
SO(LOW)
I
–
–
0.4
SO(
HIGH)
Input Capacitance on SCLK, SI, Tri-state SO(12)
INT Internal Pull-up Current
C
–
–
20
pF
μA
V
IN
–
15
40
100
INT Voltage
V
HIGH
INT( )
INT = Open Circuit
VDD - 0.5
–
VDD
INT Voltage
V
V
LOW
INT( )
I
= 1.0 mA
–
0.2
40
0.4
INT
WAKE Internal Pull-Up current
I
20
100
μA
WAKE
(
PU
)
WAKE Voltage
V
V
WAKE
(
HIGH
)
WAKE = Open Circuit
4.0
–
4.3
0.2
5.3
0.4
WAKE Voltage
V
V
V
V
WAKE(LOW)
WAKE(MAX)
I
WAKE = 1.0 mA
WAKE Voltage(12)
Maximum Voltage Applied to WAKE Through External Pull-up
–
–
40
Notes
11. Upper and lower logic threshold voltage levels apply to SI, CS, and SCLK.
12. This parameter is guaranteed by design however, is not production tested.
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics
Characteristics noted under conditions of 3.0V ≤ VDD ≤ 5.5V, 8.0V ≤ VPWR ≤ 28V, -40°C ≤ TC ≤ 125°C, unless otherwise
noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C.
Characteristic
Symbol
Min
Typ
Max
Unit
SWITCH INPUT
Pulse Wetting Current Time
t
15
16
22
ms
(
)
PULSE ON
Interrupt Delay Time
Normal Mode
t
μs
INT-DLY
–
5.0
16
Sleep Mode Switch Scan Time
t
100
200
300
μs
SCAN
Calibrated Scan Timer Accuracy
Sleep Mode
t
%
SCAN TIMER
–
–
–
–
10
10
Calibrated Interrupt Timer Accuracy
Sleep Mode
t
%
INT TIMER
DIGITAL INTERFACE TIMING(13)
Required Low State Duration on VPWR for Reset(14)
t
μs
RESET
VPWR ≤ 0.2V
–
–
10
Falling Edge of CS to Rising Edge of SCLK
Required Setup Time
t
ns
ns
ns
ns
LEAD
100
50
–
–
–
–
–
–
Falling Edge of SCLK to Rising Edge of CS
Required Setup Time
t
LAG
SI to Falling Edge of SCLK
Required Setup Time
t
SI(SU
)
16
Falling Edge of SCLK to SI
Required Hold Time
t
SI(HOLD)
20
–
–
5.0
5.0
–
–
–
SI, CS, SCLK Signal Rise Time(15)
t
t
ns
ns
ns
ns
ns
(SI)
(SI)
R
F
SI, CS, SCLK Signal Fall Time(15)
–
–
Time from Falling Edge of CS to SO Low Impedance(16)
Time from Rising Edge of CS to SO High Impedance(17)
Time from Rising Edge of SCLK to SO Data Valid(18)
Notes
t
–
55
55
55
SO(
EN
)
t
–
–
SO(
t
)
DIS
–
25
VALID
13. These parameters are guaranteed by design. Production test equipment uses 4.16 MHz, 5.0V SPI interface.
14. This parameter is guaranteed by design but not production tested.
15. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
16. Time required for valid output status data to be available on the SO pin.
17. Time required for output states data to be terminated at the SO pin.
18. Time required to obtain valid data out from SO following the rise of SCLK with a 200pF load.
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
10
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
CS
0.2 VDD
t
t
LEAD
LAG
0.7 VDD
0.2 VDD
SCLK
t
t
SI(SU) SI(HOLD)
0.7 VDD
0.2 VDD
SI
MSB in
t
t
VALID
SO(EN)
t
SO(DIS)
0.7 VDD
0.2 VDD
SO
MSB out
LSB out
Figure 4. SPI Timing Characteristics
VPWR
VDD
WAKE
INT
Wake-Up From Interrupt
Timer Expire
CS
Wake-Up From
Closed Switch
SGn
Power-Up
Normal Mode
Tri-State
Command
(Disable Tri-State)
Sleep
Command
Sleep Mode
Normal
Mode
Sleep Command
Sleep Mode
Normal
Mode
Sleep Command
Figure 5. Sleep Mode to Normal Mode Operation
Switch state change with
CS low generates INT
Switch state change with
CS low generates INT
INT
CS
Latch switch status
on falling edge of CS
Rising edge of CS does not
clear INT because state change
occurred while CS was low
SGn
Switch open ‚Äö
Switch closed ‚Äö
1
1
0
0
1
0
SGn Bit in SPI Word
Switch
Switch
Switch
Switch
Status
Switch
Status
Switch
Status
Status
Status
Status
Command
Command
Command
Command
Command
Command
Figure 6. Normal Mode Interrupt Operation
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
FUNCTIONAL DESCRIPTIONS
INTRODUCTION
FUNCTIONAL DESCRIPTIONS
INTRODUCTION
The 33975 device is an integrated circuit designed to
provide systems with ultra-low quiescent sleep/wake-up
modes and a robust interface between switch contacts and a
microprocessor. The 33975 replaces many of the discrete
components required when interfacing to microprocessor-
based systems while providing switch ground offset
protection, contact wetting current, and system wake-up.
switch inputs may be read as analog inputs through the
analog multiplexer (AMUX). Other features include a
programmable wake-up timer, programmable interrupt timer,
programmable wake-up/interrupt bits, and programmable
wetting current settings.
This device is designed primarily for automotive
applications but may be used in a variety of other applications
such as computer, telecommunications, and industrial
controls.
The 33975 features 8-programmable switch-to-ground or
switch-to-battery inputs and 14 switch-to-ground inputs. All
FUNCTIONAL PIN DESCRIPTION
CHIP SELECT (CS)
SERIAL INPUT (SI)
The system MCU selects the 33975 to receive
The SI pin is used for serial instruction data input. SI
information is latched into the input register on the falling
edge of SCLK. A logic high state present on SI will program
a one in the command word on the rising edge of the CS
signal. To program a complete word, 24 bits of information
must be entered into the device.
communication using the chip select (CS) pin. With CS in a
logic low state, command words may be sent to the 33975 via
the serial input (SI) pin, and switch status information can be
received by the MCU via the serial output (SO) pin. The
falling edge of CS enables the SO output, latches the state of
the INT pin, and the state of the external switch inputs.
SERIAL OUTPUT (SO)
Rising edge of the CS initiates the following operation:
1. Disables the SO driver (high-impedance)
The SO pin is the output from the shift register. The SO pin
remains tri-stated until the CS pin transitions to a logic low
state. All open switches are reported as a zero, all closed
switches are reported as a one. The negative transition of CS
enables the SO driver.
1. INT pin is reset to logic [1], except when additional
switch changes occur during CS low (see Figure 6,
page 11).
1. Activates the received command word, allowing the
33975 to act upon new data from switch inputs.
The first positive transition of SCLK will make the status
data bit 24 available on the SO pin. Each successive positive
clock will make the next status data bit available for the MCU
to read on the falling edge of SCLK. The SI/SO shifting of the
data follows a first-in-first-out protocol, with both input and
output words transferring the most significant bit (MSB) first.
To avoid any spurious data, it is essential the high-to-low
and low-to-high transitions of the CS signal occur only when
SCLK is in a logic low state. A clean CS signal is needed to
ensure no incomplete SPI words are sent to the device.
Internal to the 33975 device is an active pull-up to VDD on CS.
In Sleep Mode the negative edge of CS (VDD applied) will
wake up the 33975 device. Data received from the device
during CS wake-up may not be accurate.
INTERRUPT OUTPUT (INT)
The INT pin is an interrupt output from the 33975 device.
The INT pin is an open-drain output with an internal pull-up to
VDD. In Normal mode, a switch state change will trigger the
INT pin (when enabled). The INT pin is latched on the falling
edge of CS, and cleared on the rising edge of CS. The INT pin
will not clear with rising edge of CS if a switch contact change
has occurred while the CS was low.
SERIAL CLOCK (SCLK)
The system clock (SCLK) pin clocks the internal shift
register of the 33975. The SI data is latched into the input
shift register on the falling edge of SCLK signal. The SO pin
shifts the switch status bits out on the rising edge of SCLK.
The SO data is available for the MCU to read on the falling
edge of SCLK. False clocking of the shift register must be
avoided to ensure validity of data. It is essential the SCLK pin
be in a logic low state whenever CS makes any transition. For
this reason, it is recommended, though not necessary, that
the SCLK pin is commanded to a low logic state as long as
the device is not accessed and CS is in a logic high state.
When the CS is in a logic high state, any signal on the SCLK
and SI pin will be ignored and the SO pin is tri-state.
In a multiple 33975 device system with WAKE high and
VDD in (Sleep mode), the falling edge of INT will place all
33975s in Normal mode.
WAKE INPUT (WAKE)
The WAKE pin is an open-drain output and a wake-up
input. The pin is designed to control a power supply Enable
pin. In the Normal mode, the WAKE pin is low. In the Sleep
mode, the WAKE pin is high. The WAKE pin has a pull-up to
the internal +5.0 V supply.
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
12
FUNCTIONAL DESCRIPTIONS
FUNCTIONAL PIN DESCRIPTION
In Sleep mode with the WAKE pin high, the falling edge of
WAKE will place the 33975 in Normal mode. In Sleep mode
with VDD applied, the INT pin must be high for a negative
edge of WAKE to wake up the device. If VDD is not applied to
the device in Sleep mode, INT does not affect the WAKE
operation.
PROGRAMMABLE SWITCHES (SP0–SP7)
The 33975 device has 8 switch inputs capable of being
programmed to read switch-to-ground or switch-to-battery
contacts. The input is compared with a 4.0 V reference.
When programmed to be switch-to-battery, voltages greater
than 4.0 V are considered closed. Voltages less than 4.0 V
are considered open. The opposite holds true when inputs
are programmed as switch-to-ground. Programming features
are defined in Table 6 through Table 11 in the Functional
Device Operation section of this datasheet beginning on
page 16. Voltages greater than the VPWR supply voltage will
source current through the SP inputs to the VPWR pin.
Transient battery voltages greater than 38/40 V must be
clamped by an external device.
LOAD SUPPLY VOLTAGE (VPWR)
The VPWR pin is battery input and Power-ON Reset to the
33975 IC. The VPWR pin requires external reverse battery
and transient protection. The maximum input voltage on
VPWR is 50 V. All wetting, sustain, and internal logic current is
provided from the VPWR pin.
LOGIC VOLTAGE (VDD)
SWITCH-TO-GROUND (SG0–SG13)
The VDD input pin is used to determine logic levels on the
microprocessor interface (SPI) pins. Current from VDD is
used to drive the SO output, and the pull-up current for CS
and INT pins. VDD must be applied for a wake-up from the
negative edge of CS or INT.
The SGn pins are switch-to-ground inputs only. The input
is compared with a 4.0 V reference. Voltages greater than
4.0 V are considered open. Voltages less than 4.0 V are
considered closed. Programming features are defined in
Table 6 through Table 11 in the Functional Device Operation
section of this datasheet beginning on page 16. Voltages
greater than the VPWR supply voltage will source current
through the SG inputs to the VPWR pin. Transient battery
voltages greater than 38/40 V must be clamped by an
external device.
GROUND (GND)
The GND pin provides ground for the IC as well as ground
for inputs programmed as switch-to-battery inputs.
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
FUNCTIONAL DESCRIPTIONS
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
MC33975 - Functional Block Diagram
Analog Control
Programmable
Monitor Inputs
SP0 - SP7
and Protection Circuitry
Bandgap
Voltage Regulation
Oscillator & Clock
Temp. Sense
MCU Interface and Control
Monitor Inputs
SG0 - SG13
Interrupt/Wake-up
SPI Interface
Multiplex Control
Control & Protection
Interface & Control
Prog. Monitor
Monitor
Figure 7. Functional Internal Block Description
The device also features a 22-to-1 analog multiplexer for
reading inputs as analog. The 33975 device has two modes
of operation, Normal and Sleep.
ANALOG CONTROL AND PROTECTION
CIRCUITRY:
The 33975 is designed to operate from 5.5 V to 38/40 V on
the VPWR pin. Characteristics are provided from 8.0 to 28 V
for the device. Switch contact currents and the internal logic
supply are generated from the VPWR pin. The VDD supply
pin is used to set the SPI communication voltage levels,
current source for the SO driver, and pull-up current on INT
and CS.
SWITCH PROGRAMMABLE INPUTS:
Programmable switch detection inputs. These 8 inputs can
selectively detect switch closures to ground or battery. The
33975 device has 8 switch inputs capable of being
programmed to read switch-to-ground or switch-to-battery
contacts. The input is compared with a 4.0 V reference.
When programmed to be switch-to-battery, voltages greater
than 4.0 V are considered closed. Voltages less than 4.0 V
are considered open. The opposite holds true when inputs
are programmed as switch-to-ground.
The on-chip voltage regulator and bandgap supplies the
required voltages to the internal monitor circuitry. The
temperature monitor is active in the Normal Mode.
MCU INTERFACE AND CONTROL:
The 33975 Multiple Switch Detection Interface with
Suppressed Wake-up is designed to detect the closing and
opening of up to 22 switch contacts. The switch status, either
open or closed, is transferred to the microprocessor unit
(MCU) through a serial peripheral interface (SPI).
SWITCH–TO-GROUND INPUTS:
Switch detection interface inputs. These 14 inputs can
detect switch closures to ground only. The input is compared
with a 4.0 V reference. Voltages greater than 4.0 V are
considered open. Voltages less than 4.0 V are considered
closed. Note: Each of these inputs may be used to supply
current to sensors external to a module.
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
14
FUNCTIONAL DESCRIPTIONS
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
MCU INTERFACE DESCRIPTION
The 33975 device directly interfaces to a 3.3 or 5.0 V
MC68HCXX
microcontroller unit (MCU). SPI serial clock frequencies up to
6.0 MHz may be used for programming and reading switch
input status (production tested at 4.16 MHz). Figure 8
illustrates the configuration between an MCU and one 33975.
Microcontroller
33975
MOSI
SI
Shift Register
MISO
SCLK
Serial peripheral interface (SPI) data is sent to the 33975
device through the SI input pin. As data is being clocked into
the SI pin, status information is being clocked out of the
device by the SO output pin. The response to a SPI
command will always return the switch status, reset flag, and
thermal flag. Input switch states are latched into the SO
register on the falling edge of the chip select (CS) pin.
Twenty-four bits are required to complete a transfer of
information between the 33975 and the MCU.
SO
SCLK
CS
Parallel
Ports
INT
INT
33975
SI
SO
SCLK
CS
MC68HCXX
Microcontroller
33975
INT
MOSI
MISO
SI
Shift Register
24-Bit Shift Register
Figure 9. SPI Parallel Interface with Microprocessor
SO
SCLK
INT
MC68HCXX
Microcontroller
33975
Receive
Buffer
To Logic
MOSI
SI
CS
Shift Register
Parallel
Ports
INT
MISO
SO
SCLK
SCLK
Parallel
Ports
CS
Figure 8. SPI Interface with Microprocessor
INT
Two or more 33975 devices may be used in a module
system. Multiple ICs may be SPI-configured in parallel or
serial. Figures 9 and 10 show the configurations. When using
the serial configuration, 48-clock cycles are required to
transfer data in/out of the ICs.
INT
33975
SI
SO
SCLK
CS
INT
Figure 10. SPI Serial Interface with Microprocessor
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
POWER SUPPLY
POWER-ON RESET (POR)
The 33975 is designed to operate from 5.5 to 38/40 V on
the VPWR pin. Characteristics are provided from 8.0 to 28 V
for the device. Switch contact currents and the internal logic
supply are generated from the VPWR pin. The VDD supply
pin is used to set the SPI communication voltage levels,
current source for the SO driver, and pull-up current on INT
and CS.
Applying VPWR to the device will cause a Power-ON Reset
and place the device in Normal mode.
Default settings from Power-ON Reset via a VPWR or
Reset Command are as follows:
• Programmable switch – Set to switch-to-battery
• All inputs set as wake-up
• Wetting current on (16 mA pull-down, 32 mA pull-up)
• Wetting current timer on (20 ms)
• All inputs tri-state
• Analog select 00000 (no input channel selected)
VDD supply may be removed from the device to reduce
quiescent current. If VDD is removed while the device is in
Normal mode, the device will remain in Normal mode. If VDD
is removed in Sleep mode, the device will remain in Sleep
mode until a wake-up input is received (WAKE high to low,
switch input or interrupt timer expires).
Note The 33975 device provides indication that a reset
has occurred by placing a logic [1] in bit 22 of the SO buffer.
The reset bit is cleared on rising edge of CS.
Removing VDD from the device disables SPI
communication and will not allow the device to wake up from
the INT and CS pins.
OPERATIONAL MODES
The 33975 has two operating modes, Normal mode and
Sleep mode. A discussion on Normal mode begins below. A
discussion on Sleep Mode begins on page 21.
• Tri-state Register (Tri-state Command)
• Analog Select Register (Analog Command)
• Calibration of Timers (Calibration Command)
• Reset (Reset Command)
NORMAL MODE
Figure 6, page 11, is a graphical description of the device
operation in Normal mode. Switch states are latched into the
input register on the falling edge of CS. The INT to the MCU
is cleared on the rising edge of CS. However, INT will not
clear on the rising edge of CS if a switch has closed during
SPI communication (CS low). This prevents switch states
from being missed by the MCU.
Normal mode may be entered by the following events:
• Application of VPWR to the IC
• Change-of-switch state (when enabled)
• Falling edge of WAKE
• Falling edge of INT (with VDD = 5.0 V and WAKE at
Logic [1])
• Falling edge of CS (with VDD = 5.0 V)
• Interrupt timer expires
PROGRAMMABLE SWITCH REGISTER
Inputs SP0 to SP7 may be programmable for switch-to-
battery or switch-to-ground. These inputs types are defined
using the settings command (refer to Table 6). To set an SPn
input for switch-to-battery, a logic [1] for the appropriate bit
must be set. To set an SPn input for switch-to-ground, a
logic [0] for the appropriate bit must be set. The MCU may
change or update the Programmable Switch Register via
software at any time in Normal mode. Regardless of the
setting, when the SPn input switch is closed a logic [1] will be
placed in the Serial Output Response Register (refer to
Table 17, page 21).
Only in Normal mode with VDD applied can the registers of
the 33975 be programmed through the SPI.
The registers that may be programmed in Normal mode
are listed below. Further explanation of each register is
provided in subsequent paragraphs.
• Programmable Switch Register (Settings Command)
• Wake-up/Interrupt Register (Wake-up/Interrupt
Command)
• Wetting Current Register (Metallic Command)
• Wetting Current Timer Register (Wetting Current Timer
Enable Command)
Table 6. Settings Command
Settings Command
Not used
Battery/Ground Select
23
0
22
0
21
0
20
0
19
0
18
0
17
0
16
1
15
X
14
X
13
X
12
X
11
X
10
X
9
8
7
6
5
4
3
2
1
0
X
X
sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
16
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
IC in Sleep mode (refer to Table 7). Programming the wake-
up/interrupt bit to logic [1] will enable the specific input to
generate an interrupt with switch change of state and will
enable the specific input as wake-up. The MCU may change
or update the Wake-up/Interrupt Register via software at any
time in Normal mode.
WAKE-UP/INTERRUPT REGISTER
The Wake-up/Interrupt Register defines the inputs that are
allowed to wake the 33975 from Sleep mode or set the INT
pin low in Normal mode. Programming the wake-up/interrupt
bit to logic [0] will disable the specific input from generating
an interrupt and will disable the specific input from waking the
Table 7. Wake-Up /Interrupt Command
Wake-up/Interrupt Command
Command Bits
23
0
22
0
21
0
20
0
19
0
18
0
17
1
16
0
15
X
14
X
13
X
12
X
11
X
10
X
9
8
7
6
5
4
3
2
1
0
X
X
sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0
0
0
0
0
0
0
1
1
X
X
sg1 sg1 sg1 sg1 sg9 sg8 sg7 sg6 sg5 sg4 sg3 sg2 sg1 sg0
3
2
1
0
WETTING CURRENT REGISTER
The 33975 has two levels of switch-to-ground contact
current, 32 and 4.0 mA, and two levels of switch-to-battery
contact current, 16 and 2.0 mA (see Figure 11). The metallic
command is used to set the switch contact current level (refer
to Table 8). Programming the metallic bit to logic [0] will set
the switch wetting current to 2.0 mA/4.0 mA. Programming
the metallic bit to logic [1] will set the switch contact wetting
current to 16 mA/32 mA. The MCU may change or update the
Wetting Current Register via software at any time in Normal
Mode.
Switch Contact Voltage
32 mA Switch Wetting Current
Wetting current is designed to provide higher levels of
current during switch closure. The higher level of current is
designed to keep switch contacts from building up oxides that
form on the switch contact surface.
4.0 mA Switch Sustain Current
20 ms Wetting Current Timer
Figure 11. Contact Wetting and Sustain Current
for Switch-to-Ground Input
Table 8. Metallic Command
Metallic Command
Command Bits
23
0
22
0
21
0
20
0
19
0
18
1
17
0
16
0
15
X
14
X
13
X
12
X
11
X
10
X
9
8
7
6
5
4
3
2
1
0
X
X
sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0
0
0
0
0
0
1
0
1
X
X
sg1 sg1 sg1 sg1 sg9 sg8 sg7 sg6 sg5 sg4 sg3 sg2 sg1 sg0
3
2
1
0
current timers disabled, power dissipation for the IC must be
considered.
WETTING CURRENT TIMER REGISTER
Each switch input has a designated 20 ms timer. The timer
starts when the specific switch input crosses the comparator
threshold (4.0 V). When the 20 ms timer expires, the contact
current is reduced from 16 to 2.0 mA for switch-to-battery
inputs and 32 to 4.0 mA for switch-to-ground inputs. The
wetting current timer may be disabled for a specific input.
When the timer is disabled, wetting current will continue to
flow through the closed switch contact. With multiple wetting
The MCU may change or update the Wetting Current
Timer Register via software at any time in Normal mode. This
allows the MCU to control the amount of time wetting current
is applied to the switch contact. Programming the wetting
current timer bit to logic [0] will disable the wetting current
timer. Programming the wetting current timer bit to logic [1]
will enable the wetting current timer (refer to Table 9).
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Table 9. Wetting Current Timer Enable Command
Wetting Current Timer Commands
Command Bits
23
0
22
0
21
0
20
0
19
0
18
1
17
1
16
1
15
X
14
X
13
X
12
X
11
X
10
X
9
8
7
6
5
4
3
2
1
0
X
X
sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0
0
0
0
0
1
0
0
0
X
X
sg1 sg1 sg1 sg1 sg9 sg8 sg7 sg6 sg5 sg4 sg3 sg2 sg1 sg0
3
2
1
0
comparator on each input remains active. This command
allows the use of each input as a comparator with a 4.0 V
threshold. The MCU may change or update the Tri-state
Register via software at any time in Normal mode.
TRI-STATE REGISTER
The tri-state command is use to set the SPn or SGn input
node as high-impedance (refer to Table 10). By setting the
Tri-state Register bit to logic [1], the input will be high-
impedance regardless of the metallic command setting. The
Table 10. Tri-state Command
Tri-State Commands
Command Bits
23 22 21 20 19 18 17 16 15 14
13
X
12
X
11
X
10
X
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
0
X
X
X
X
X
X
sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0
sg13 sg12 sg11 sg10 sg9 sg8 sg7 sg6 sg5 sg4 sg3 sg2 sg1 sg0
selects the input as high-impedance. Setting bit 6 and bit 5 to
0,1 selects 4.0 mA, and 1,0 selects 32 mA. Setting bit 6 and
bit 5 to 1,1 in the Analog Select Register is not allowed and
will place the input as an analog input with high-impedance.
ANALOG SELECT REGISTER
The analog voltage on switch inputs may be read by the
MCU using the analog command (refer to Table 11). Internal
to the IC is a 22-to-1 analog multiplexer. The voltage present
on the selected input pin is buffered and made available on
the AMUX output pin. The AMUX output pin is clamped to a
maximum of VDD volts regardless of the higher voltages
present on the input pin. After an input has been selected as
the analog, the corresponding bit in the next SO data stream
will be logic [0]. When selecting a channel to be read as
analog, the user must also set the desired current (32 mA,
4.0 mA, or high-impedance). Setting bit 6 and bit 5 to 0,0
Analog currents set by the analog command are pull-up
currents for all SGn and SPn inputs (refer to Table 11). The
analog command does not allow pull-down currents on the
SPn inputs. Setting the current to 32 or 4.0 mA may be useful
for reading sensor inputs. Further information is provided in
the Typical Applications section of this datasheet beginning
on page 23. The MCU may change or update the Analog
Select Register via software at any time in Normal mode.
Table 11. Analog Command
Current
Select
Analog Command
Not used
Analog Channel Select
23
0
22
0
21
0
20
0
19
0
18
1
17
1
16
0
15
X
14
X
13
X
12
11
X
10
9
8
7
6
5
4
0
3
0
2
0
1
0
0
0
X
X
X
X
X
32 4.0
mA mA
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
18
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Table 12. Analog Channel
Bits 43210
Analog Channel Select
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
No Input Selected
SG0
SG1
SG2
SG3
SG4
SG5
SG6
SG7
SG8
SG9
SG10
SG11
SG12
SG13
SP0
SP1
SP2
SP3
SP4
SP5
SP6
SP7
oscillator frequency changes with temperature, calibration is
required for an accurate time base. Calibrating the timers has
no affect on the quiescent current measurement. The
calibration command simply makes the time base more
accurate. The calibration command may be used to update
the device on a periodic basis. All reset conditions clear the
calibration register and places the device in the uncalibrated
state.
CALIBRATION OF TIMERS
In cases where an accurate time base is required, the user
may calibrate the internal timers using the calibration
command (refer to Table 13). After the 33975 device
receives the calibration command, the device expects 512 μs
logic [0] calibration pulse on the CS pin. The pulse is used to
calibrate the internal clock. No other SPI pins should
transition during this 512 μs calibration pulse. Because the
Table 13. Calibration Command
Calibration Command
Command Bits
23
0
22
0
21
0
20
0
19
1
18
0
17
1
16
1
15
X
14
X
13
X
12
X
11
X
10
X
9
8
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
X
X
or the paragraph entitled Power-ON Reset (POR) on page 16
of this datasheet.
RESET
The reset command resets all registers to Power-ON
Reset (POR) state. Refer to Table , page 20, for POR states
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Table 14. Reset Command
Reset Command
Command Bits
23
0
22
1
21
1
20
1
19
1
18
1
17
1
16
1
15
X
14
X
13
X
12
X
11
X
10
X
9
8
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
X
X
Output (SO) data for input voltages greater or less than the
threshold level. Open switches are always indicated with a
logic [0], closed switches are indicated with logic [1].
SPI COMMAND SUMMARY
Table below provides a comprehensive list of SPI
commands recognized by the 33975 and the reset state of
each register. Table 16 and Table 17 contain the Serial
Table 15. SPI Command Summar
MSB
Command Bits
Setting Bits
LSBI
23
0
22
0
21
0
20
0
19
0
18
0
17
0
16
0
15
X
14
13
X
12
X
11
X
10
X
9
8
7
6
5
4
3
2
1
0
Switch Status
Command
X
X
X
X
X
X
X
X
X
X
X
Settings
Command
0
0
0
0
0
0
0
1
X
X
X
X
X
X
X
X
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
Bat=1, Gnd=0
(Default state = 1)
Wake-up/Interrupt
Bit
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
X
X
X
X
X
X
X
X
X
X
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
SG1 SG1 SG1 SG1 SG9 SG8 SG7 SG6 SG5 SG4 SG3 SG2 SG1 SG0
3
Wake-up=1
2
1
0
Nonwake-up=0
(Default state = 1)
Metallic
Command
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
X
X
X
X
X
X
X
X
X
X
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
SG1 SG1 SG1 SG1 SG9 SG8 SG7 SG6 SG5 SG4 SG3 SG2 SG1 SG0
Metallic = 1
3
X
X
2
X
X
1
X
X
0
X
X
Non-metallic = 0
(Default state = 1)
Analog Command
0
0
0
0
0
1
1
0
X
X
X
X
X
X
X
32m 4.0
0
0
0
0
0
A
0
mA
0
Wetting Current
Timer
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
X
X
X
X
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
SG1 SG1 SG1 SG1 SG9 SG8 SG7 SG6 SG5 SG4 SG3 SG2 SG1 SG0
3
Enable Command
Timer ON = 1
2
1
0
Timer OFF = 0
(Default state = 1)
Tri-state
Command
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
0
X
X
X
X
X
X
X
X
X
X
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
SG1 SG1 SG1 SG1 SG9 SG8 SG7 SG6 SG5 SG4 SG3 SG2 SG1 SG0
3
Input Tri-state=1
2
1
0
Calibration
Command
0
0
0
0
0
1
0
0
1
0
0
1
1
1
1
0
1
1
1
0
1
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
(Default state -
uncalibrated)
Sleep Command
X
X
X
X
int
int
int sca sca sca
n
n
n
(See Sleep Mode
on page 21)
time time time
r
r
r
time time time
r
r
r
Reset Command
X
X
X
X
X
X
X
X
X
X
SO Response Will
Always Send
ther RST SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SG1 SG1 SG1 SG1 SG9 SG8 SG7 SG6 SG5 SG4 SG3 SG2 SG1 SG0
m
3
2
1
0
flg
flg
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
20
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Table 16. Serial Output (SO) Bit Data
Input
Programmed
Voltage on Input
Type of Input
SO SPI Bit
Pin
SP
Switch to Ground
Switch to Ground
Switch to Battery
Switch to Battery
N/A
SPn < 4.0 V
SPn > 4.0 V
SPn < 4.0 V
SPn > 4.0 V
SGn < 4.0 V
SGn > 4.0 V
1
0
0
1
1
0
SG
N/A
Table 17. Serial Output (SO) Response Register
SO Response
Will
Always Send
ther RST SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SG1 SG1 SG1 SG1 SG9 SG8 SG7 SG6 SG5 SG4 SG3 SG2 SG1 SG0
m
3
2
1
0
flg
flg
The 33975 device will exit the Normal mode and enter the
Sleep mode only with a valid sleep command.
EXAMPLE OF NORMAL MODE OPERATION
The operation of the device in Normal mode is defined by
the states of the programmable internal control registers. A
typical application may have the following settings:
SLEEP MODE
Sleep mode is used to reduce system quiescent currents.
Sleep mode may be entered only by sending the sleep
command. All register settings programmed in Normal mode
will be maintained in Sleep mode.
• Programmable switch – set to switch-to-ground
• All inputs set as wake-up
• Wetting current on (32 mA)
• Wetting current timer on (20 ms)
• All inputs tri-state-disabled (comparator is active)
• Analog select 00000 (no input channel selected)
The 33975 will exit Sleep mode and enter Normal mode
when any of the following events occur:
• Input switch change of state (when enabled)
• Interrupt timer expire
• Falling edge of WAKE
• Falling edge of INT (with VDD = 5.0 V and WAKE at
Logic [1])
• Falling edge of CS (with VDD = 5.0 V)
• Power-on reset (POR)
With the device programmed as above, an interrupt will be
generated with each switch contact change of state (open-to-
close or close-to-open) and 32 mA of contact wetting current
will be source for 20 ms. The INT pin will remain low until
switch status is acknowledged by the microprocessor. It is
critical to understand INT will not be cleared on the rising
edge of CS if a switch closure occurs while the CS is low. The
maximum duration a switch state change can exist without
acknowledgement depends on the software response time to
the interrupt. Figure 6, page 11, shows the interaction
between changing input states and the INT and CS pins.
The VDD supply may be removed from the device during
Sleep mode. However removing VDD from the device in
Sleep mode will disable a wake-up from falling edge of INT
and CS.
If desired the user may disable interrupts (wake-up/
interrupt command) from the 33975 device and read the
switch states on a periodic basis. Switch activation and
deactivation faster than the MCU read rate will not be
acknowledged.
Note: In cases where CS is used to wake the device, the
first SO data message is not valid.
The sleep command contains settings for two
programmable timers for Sleep mode, the interrupt timer and
the scan timer, as shown in Table 18.
Table 18. Sleep Command
Sleep Command
Command Bits
23
0
22
0
21
0
20
0
19
1
18
1
17
0
16
0
15
X
14
X
13
X
12
X
11
X
10
X
9
8
7
6
5
4
3
2
1
0
X
X
X
X
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
The interrupt timer is used as a periodic wake-up timer.
When the timer expires, an interrupt is generated and the
device enters Normal mode.
Figure 5, page 11, is a graphical description of how the
33975 device exits Sleep mode and enters Normal mode.
Notice that the device will exit Sleep mode when the interrupt
timer expires or when a switch change of state occurs. The
falling edge of INT triggers the MCU to wake from Sleep state.
Figure 12 illustrates the current consumed during Sleep
mode. During the 125 μs, the device is fully active and switch
states are read. The quiescent current is calculated by
integrating the normal running current over scan period plus
approximately 60 μA.
Note: The interrupt timer in the 33975 device may be
disabled by programming the interrupt bits to logic [1 1 1].
Table 19 shows the programmable settings of the Interrupt
timer.
The scan timer sets the polling period between input
switch reads in Sleep mode. The period is set in the sleep
command and may be set to 000 (no period) to 111 (64 ms).
In Sleep mode when the scan timer expires, inputs will
behave as programmed prior to sleep command. The 33975
will wake up for approximately 125 μs and read the switch
inputs. At the end of the 125 μs, the input switch states are
compared with the switch state prior to sleep command.
When switch state changes are detected, an interrupt (when
enabled; refer to wake-up/interrupt command description on
page 17) is generated and the device enters Normal mode.
Without switch state changes, the 33975 will reset the scan
timer, inputs become tri-state, and the Sleep mode continues
until the scan timer expires again.
I=V/R or 0.270V/100Ω=2.7mA
Table 20 shows the programmable settings of the Scan
timer.
Inputs active for
A
I=V/R or
Note: The interrupt and scan timers are disabled in the
Normal Mode.
125μs out of 32ms
6.0mV/100Ω=60μA
Table 19. Interrupt Timer
Figure 12. Sleep Current Waveform
TEMPERATURE MONITOR
Bits 543
Interrupt Period
000
001
010
011
100
101
110
111
32 ms
64 ms
With multiple switch inputs closed and the device
programmed with the wetting current timers disabled,
considerable power will be dissipated by the IC. For this
reason temperature monitoring has been implemented. The
temperature monitor is active in the Normal mode only. When
the IC temperature is above the thermal limit, the temperature
monitor will do all of the following:
128 ms
256 ms
512 ms
1.024 s
2.048 s
• Generate an interrupt.
• Force all wetting current sources to revert to 2.0 mA/
4.0 mA sustain currents
No interrupt wake-up
• Maintain the 2.0 mA/4.0 mA sustain currents and all
other functionality.
• Set the thermal flag bit in the SPI output register.
Table 20. Scan Timer
Bits 210
Scan Period
The thermal flag bit in the SPI word will be cleared on the
rising edge of CS provided the die temperature has cooled
below the thermal limit. When die temperature has cooled
below thermal limit, the device will resume previously
programmed settings.
000
001
010
011
100
101
110
111
No Scan
1.0 ms
2.0 ms
4.0 ms
8.0 ms
16 ms
32 ms
64 ms
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
22
TYPICAL APPLICATIONS
OPERATIONAL MODES
TYPICAL APPLICATIONS
The 33975’s primary function is the detection of open or
METALLIC/ELASTOMERIC SWITCH
closed switch contacts. However, there are many features
that allow the device to be used in a variety of applications.
The following is a list of applications to consider for the IC:
Metallic switch contacts often develop higher contact
resistance over time owing to contact corrosion. The
corrosion is induced by humidity, salt, and other elements
that exist in the environment. For this reason the 33975
provides two settings for contacts. When programmed for
metallic switches, the device provides higher wetting current
to keep switch contacts free of oxides. The higher current
occurs for the first 20 ms of switch closure. Where longer
duration of wetting current is desired, the user may send the
wetting current timer command and disable the timer. Wetting
current will be continuous to the closed switch. After the time
period set by the MCU, the wetting current timer command
may be sent again to enable the timer. The user must
consider power dissipation on the device when disabling the
timer. (Refer to the paragraph entitled Temperature Monitor,
page 22.)
• Sensor power supply
• Switch monitor for metallic or elastomeric switches
• Analog sensor inputs (Ratiometric)
• Power MOSFET/LED driver and monitor
• Multiple 33975 devices in a module system
The following paragraphs describe the applications in
detail.
SENSOR POWER SUPPLY
Each input may be used to supply current to sensors
external to a module. Many sensors such as Hall effect,
pressure sensors, and temperature sensors require a supply
voltage to power the sensor, and provide an open collector or
analog output. Figure 13 shows how the 33975 may be used
to supply power and interface to these types of sensors. In an
application where the input makes continuous transitions,
consider using the wake-up/interrupt command to disable
the interrupt for the particular input.
To increase the amount of wetting current for a switch
contact, the user has two options. Higher wetting current to a
switch may be achieved by paralleling SGn or SPn inputs.
This will increase wetting current by 32 mA for each input
added to the switch-to-ground contact and 16 mA for switch-
to-battery contacts. The second option is to simply add an
external resistor pull-up to the VPWR supply for switch-to-
ground inputs or a resistor to ground for a switch-to-battery
input. Adding an external resistor has no effect on the
operation of the device.
33975
VBAT
SP0
VPWR
SP1
Elastomeric switch contacts are made of carbon and have
a high contact resistance. Resistance of 1.0 kΩ is common.
In applications with elastomeric switches, the pull-up and
pull-down currents must be reduced to prevent excessive
power dissipation at the contact. Programming for a lower
current settings is provided in the Functional Device
Operation Section beginning on page 16 under Table 8,
Metallic Command.
V
DD
MCU
VDD
VBAT
SP7
WAKE
SI
MOSI
SCLK
SG0
SG1
SCLK
CS
VPWR VPWR
CS
SO
MISO
INT
32
mA
4.0
mA
INT
32 mA
ANALOG SENSOR INPUTS (RATIOMETRIC)
SG12
V
PWR VPWR
The 33975 features a 22-to-1 analog multiplexer. Setting
the binary code for a specific input in the analog command
allows the microcontroller to perform analog to digital
conversion on any of the 22 inputs. On rising edge of the CS,
the multiplexer connects a requested input to the AMUX pin.
The AMUX pin is clamped to max of VDD volts regardless of
the higher voltages present on the input pin. After an input
has been selected as the analog, the corresponding bit in the
next SO data stream will be logic [0].
Hall-Effect
Sensor
32
4.0
mA
mA
Reg
SG13
IOC[7:0]
Input Capture
Timer Port
AMUX
X
VDD
0V
VPWR
0V
AMUX
SG13
The input pin, when selected as analog, may be
configured as analog with high-impedance, analog with
4.0 mA pull-up, or analog with 32 mA pull-up. Figure 14,
page 24, shows how the 33975 may be used to provide a
ratiometric reading of variable resistive input.
Figure 13. Sensor Power Supply
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
TYPICAL APPLICATIONS
OPERATIONAL MODES
I1 x R1
I2 x R2
33975
VBAT
ADC =
x 255
SP0
SP1
VPWR
VDD
VDD
4.0mA x 1.0kΩ
4.0mA x 1.21kΩ
ADC =
x 255
MCU
VBAT
SP7
ADC = 210 counts
WAKE
SI
MOSI
SCLK
CS
Using the equation yields the following:
SG0
SCLK
CS
V
PWR VPWR
SG1
The ADC value of 213 counts is the value with 0% error
(neglecting the resistor tolerance and AMUX input offset
voltage). Now calculate the count value induced by the
mismatch in current sources. From a sample device the
maximum current source was measured at 3.979 mA and
minimum current source was measured at 3.933 mA. This
yields 1.16% error in A/D conversion due to the current
source mismatch. The A/D measurement will be as follows:
MISO
INT
SO
32
mA
4.0
mA
I
1
INT
4.0mA
SG12
AMUX
AN0
V
PWR VPWR
R1
Analog
Ports
32
mA
4.0
mA
Analog Sensor
or Analog Switch
SG13
I
2
4.36V to 5.32V
R2
4.0mA
3.933 mA x 1.0kΩ
V
ADC =
x 255
REF(H)
1.21k
Ω
3.979 mA x 1.21kΩ
0.1%
V
REF(L)
ADC = 208 counts
This A/D conversion is 1.16% low in value. The error
correction factor of 1.0115 may be used to correct the value:
Figure 14. Analog Ratiometric Conversion
To read a potentiometer sensor, the wiper should be
grounded and brought back to the module ground, as
illustrated in Figure 14. With the wiper changing the
impedance of the sensor, the analog voltage on the input will
represent the position of the sensor.
ADC = 208 counts x 1.0116
ADC = 210 counts
Using the Analog feature to provide 4.0 mA of pull-up
current to an analog sensor may induce error due to the
accuracy of the current source. For this reason, a ratiometric
conversion must be considered. Using two current sources
(one for the sensor and one to set the reference voltage to the
A/D converter) will yield a maximum error (owing to the
33975) of 4%.
An error correction factor may then be stored in E2
memory and used in the A/D calculation for the specific input.
Each input used as analog measurement will have a
dedicated calibrated error correction factor.
POWER MOSFET/LED DRIVER AND MONITOR
Higher accuracy may be achieved through module level
calibration. In this example, we use the resistor values from
Figure 14 and assume the current sources are 4% from each
other. The user may use the module end-of-line tester to
calculate the error in the A/D conversion. By placing a
1.0 kΩ, 0.1% resistor in the end-of-line test equipment and
assuming a perfect 4.0 mA current source from the 33975, a
calculated A/D conversion may be obtained.
Because of the flexible programming of the 33975 device,
it may be used to drive small loads like LEDs or MOSFET
gates. It was specifically designed to power up in the Normal
Mode with the inputs tri-state. This was done to ensure the
LEDs or MOSFETs connected to the 33975 power up in the
off-state. The Switch Programmable (SP0–SP7) inputs have
a source-and-sink capability, providing effective MOSFET
gate control. To complete the circuit, a pull-down resistor
should be used to keep the gate from floating during the
Sleep Modes. Figure 15, page 25, shows an application
where the SG0 input is used to monitor the drain-to-source
voltage of the external MOSFET. The 750 Ω resistor is used
to set the drain-to-source trip voltage. With the 4.0 mA
current source enabled, an interrupt will be generated when
the drain-to-source voltage is approximately 1.0 V.
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
24
TYPICAL APPLICATIONS
OPERATIONAL MODES
current to the 750 Ω resistor, the analog voltage on the SGn
pin will be approximately:
VBAT
V
V
PWR PWR
SG0
VSGn = ISGn x 750Ω + VDS
32
mA
4.0
mA
750Ω
SG0
AMUX
As the voltage on the drain of the MOSFET increases, so
does the voltage on the SGn pin. With the SGn pin selected
as analog, the MCU may perform the A/D conversion.
100kΩ
+
To SPI
4.0 V Ref
V
-
Comparator
Using this method for controlling unclamped inductive
loads is not recommended. Inductive fly-back voltages
greater than VPWR may damage the IC.
V
PWR
PWR
SG0
32
4.0
mA
mA
The SP0–SP7 pins of this device may also be used to
send signals from one module to another. Operation is similar
to the gate control of a MOSFET.
SP0
+
To SPI
4.0 V
Ref
-
16
For LED applications a resistor in series with the LED is
recommended but not required. The switch-to-ground inputs
are recommended for LED application. To drive the LED use
the following commands:
Comparator
mA
2.0 mA
V
V
PWR PWR
SG13
32
mA
4.0
mA
•
wetting current timer enable command –Disable SGn
wetting current timer.
SG13
•
metallic command –Set SGn to 32 mA.
+
From this point forward the LED may be turned on and off
To SPI
4.0 V Ref
-
using the tri-state command:
Comparator
•
•
tri-state command –Disable tri-state for SGn (LED ON).
tri-state command –Enable tri-state for SGn (LED
OFF).
Figure 15. MOSFET or LED Driver Output
These parameters are easily programmed via SPI
commands in Normal mode.
The sequence of commands (from Normal mode with
inputs tri-state) required to set up the device to drive a
MOSFET are as follows:
Multiple 33975 Devices in a Module System
•
•
•
•
wetting current timer enable command –Disable SPn
Connecting power to the 33975 and the MCU for Sleep
mode operation may be done in several ways. Table 21
shows several system configurations for power between the
MCU and the 33975 and their specific requirements for
functionality.
wetting current timer (refer to Table 9, page 18).
metallic command –Set SPn to 16/32 mA or 2.0/4.0 mA
gate drive current (refer to Table 8, page 17).
settings command –Set SPn as switch-to-battery (refer
to Table 6, page 16).
tri-state command –Disable tri-state for SPn (refer to
Table 10, page 18).
Table 21. Sleep Mode Power Supply
After the tri-state command has been sent (tri-state
disable), the MOSFET gate will be pulled to ground. From this
point forward the MOSFET may be turned on and off by
sending the settings command:
MCU
VDD
33975
VDD
Comments
All wake-up conditions apply. (Refer to Sleep
Mode, page 21.)
5.0V
5.0V
•
settings command –SPn as switch-to-ground
(MOSFET ON).
SPI wake-up is not possible.
5.0V
0V
0V
•
settings command –SPn as switch-to-battery
(MOSFET OFF).
Sleep mode is not possible. Current from the CS
pull-up will flow through the MCU to the VDD
that has been switched off. The negative edge
of CS will put 33975 in Normal mode.
5.0V
Monitoring of the MOSFET drain in the OFF state provides
open load detection. This is done by using an input
comparator. With the SGn input in tri-state, the load will pull
up the input to battery. With the load open, the SGn pin is
pulled down to ground through an external resistor. The open
load is indicated by a logic [1] in the SO data bit.
SPI wake-up is not possible.
0V
0V
Multiple 33975 devices may be used in a module system.
SPI control may be done in parallel or serial. However when
parallel mode is used, each device is addressed
The analog command may be used to monitor the drain
voltage in the MOSFET ON state. By sourcing 4.0 mA of
independently (refer to MCU Interface Description, page 15).
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
25
TYPICAL APPLICATIONS
OPERATIONAL MODES
Therefore, when sending the sleep command, one device will
enter sleep before the other. For multiple devices in a system,
it is recommended that the devices are controlled in serial (S0
from first device is connected to SI of second device). With
two devices, 48 clock pulses are required to shift data in.
When the WAKE feature is used to enable the power supply,
both WAKE pins should be connected to the enable pin on the
power supply. The INT pins may be connected to one
interrupt pin on the MCU, or may have their own dedicated
interrupt to the MCU.
The 33975 IC has an internal 5.0 V supply from the VPWR
pin. A POR circuit monitors the internal 5.0 V supply. In the
event of transients on the VPWR pin, an internal reset may
occur. Upon reset the 33975 will enter Normal mode with the
internal registers as defined in Table , page 20. Therefore it
is recommended that the MCU periodically update all
registers internal to the IC.
USING THE WAKE FEATURE
The 33975 provides a WAKE output and wake-up input
designed to control an enable pin on system power supply.
While in the Normal mode, the WAKE output is low, enabling
the power supply. In the Sleep mode, the WAKE pin is high,
disabling the power supply. The WAKE pin has a passive pull-
up to the internal 5.0 V supply but may be pulled up through
a resistor to VPWR supply (see Figure 17, page 27).
The transition from Normal to Sleep mode is done by
sending the sleep command. With the devices connected in
serial and the sleep command sent, both will enter Sleep
mode on the rising edge of CS. When Sleep mode is entered,
the WAKE pin will be logic [1]. If either device wakes up, the
WAKE pin will transition low, waking the other device.
A condition exists where the MCU is sending the sleep
command (CS logic [0]) and a switch input changes state.
With this event, the device that detects this input will not
transition to Sleep mode, while the second device will enter
Sleep mode. In this case, two switch status commands must
be sent to receive accurate switch status data. The first
switch status command will wake the device in Sleep mode.
Switch status data may not be valid from the first switch
status command because of the time required for the input
voltage to rise above the 4.0 V input comparator threshold.
This time is dependant on the impedance of SGn or SPn
node. The second switch status command will provide
accurate switch status information. It is recommended that
the software wait 10 to 20 ms between the two switch status
commands, allowing time for switch input voltages to
stabilize. With all switch states acknowledged by the MCU,
the sleep sequence may be initiated. All parameters for Sleep
mode should be updated prior to sending the sleep
command.
When the WAKE output is not used the pin should be
pulled up to the VDD supply through a resistor, as shown in
Figure 16, page 27).
During the Sleep mode, a switch closure will set the WAKE
pin low, causing the 33975 to enter the Normal mode. The
power supply will then be activated, supplying power to the
VDD pin and the microprocessor and the 33975. The
microprocessor can determine the source of the wake-up by
reading the interrupt flag.
COST AND FLEXIBILITY
Systems requiring a significant number of switch
interfaces have many discrete components. Discrete
components on standard PWB consume board space and
must be checked for solder joint integrity. An integrated
approach reduces solder joints, consumes less board space,
and offers wider operating voltage, analog interface
capability, and greater interfacing flexibility.
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
26
TYPICAL APPLICATIONS
OPERATIONAL MODES
VDD
VBAT
VBAT
Power
Supply
33975
VPWR
VPWR
SP0
SP1
VDD
VBAT
VDD
MC68HCXX
Microprocessor
SP7
WAKE
CS
CS
SG0
SG1
INT
SI
INT
MOSI
MISO
SO
SCLK
SCLK
AN0
AMUX
SG12
SG13
Figure 16. Power Supply Active in Sleep Mode
VDD
VBAT
VBAT
Power
Supply
33975
Enable
VPWR
VPWR
SP0
SP1
VDD
WAKE
VDD
VBAT
MC68HCXX
Microprocessor
SP7
CS
CS
SG0
SG1
INT
SI
INT
MOSI
MISO
SO
SCLK
SCLK
AN0
AMUX
SG12
SG13
Figure 17. Power Supply Shutdown in Sleep Mode
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
27
PACKAGING
PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
Important: For the most current revision of the package, visit www.freescale.com and perform a “keyword” search on the “98A”
number listed below.
EK SUFFIX
32-PIN EXPOSED PAD
98ASA10556D
REVISION D
33975
Analog Integrated Circuit Device Data
28
Freescale Semiconductor
PACKAGING
PACKAGE DIMENSIONS (CONTINUED)
PACKAGE DIMENSIONS (Continued)
EK SUFFIX
32-PIN EXPOSED PAD
98ASA10556D
REVISION D
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
29
PACKAGING
PACKAGE DIMENSIONS (CONTINUED)
EK SUFFIX
32-PIN EXPOSED PAD
98ASA10556D
REVISION D
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
30
REVISION HISTORY
REVISION HISTORY
REVISION
DATE
DESCRIPTION OF CHANGES
• Implemented Revision History page
6/2007
5
• Updated to Freescale form and style
• Added MCZ33975EK/R2 and MCZ33975AEK/R2
• Removed Peak Package Reflow Temperature During Reflow, and added Peak Package
Reflow Temperature During Reflow(5) (6)
,
• Removed MC33975AEK/R2 from the Ordering Information
• Replaced figures for 33975 Simplified Application Diagram, Power Supply Active in
Sleep Mode, and Power Supply Shutdown in Sleep Mode.
• Adjusted ESD voltages for Human Body Model(2) and Applies to all non-input Pins.
• Updated document form and style.
11/2007
6
2/2008
8/2008
8/2008
8/2011
• Minor changes to text
7
8
• Updated package drawing
• Revised wording of Features on Page 1 - No parameter /technical changes.
9.0
10.0
• Revised Ordering Information table by adding part numbers MC33975TEK/R2 and
MC33975ATEK/R2, and removing part numbers MC33975EK/R2, MCZ33975EK/R2
and MCZ33975AEK/R2.
• Updated document form and style.
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
31
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